edac updates for v4.3-rc1
-----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJV8giFAAoJEAhfPr2O5OEVYxsP/imxjTa1utbeYToA+oqut9Yw HbMB6yjscfZF/CwP/rB/T5jNTTww6pvavBntw29NewTmPIfREuvYMvvOtCkyKdQf yEVeME0cvJAiSdtiqeWoAMJYm3VMDKPh0p/cncvhcpip0ORU3prV9XEqNo1byvEU S4laHNfxgDbTHptVhvaT7Li/yN3KyenlaT61K3dYn0LtbPf6uxSsvqX+ExuZSix7 ZWS+wQrzX35hQHvL7Ax1iZv15uTfrC2kD2bwZrgetvl6wVdwBKx9vbWosaZ+XffV gv4dxJG5zNV2nFPfFUxqQZ++OcieuqP1yeWtwbuBPx3qibDKTb/IJYX8VvHAAc8n EgaDwFsYH6YnLsxNL58+W9PYigVyc2VS2Nfqz9uRuXmuryoyDbCpcgVmZYdmgYKn c1Rc4DzOqvOWrv5jdtSxYmdmAMqgf0LjlMzUmZ7shJYWprsqjgwqxevPXmH9xb7s myBpM604KofiWGPGqVNVYIdt8AldXc1QNnyCxGHcAAdIzEOn+7WEdeWqVQ665Vya x2Cp9h1IURPtcniw7Dx/0nqBu64Y6OMGz9W6H0SxBUWc2cC6QZZ4k9zOg2krtFkt c/S6RCYdIoxIcwTPfhyoBfCAHueSfUaJ8sIAWMrQLFUCgALN2f1WslIYEJVGcPOT UeQzSo1pe9wyZu5hQzji =DrsG -----END PGP SIGNATURE----- Merge tag 'edac/v4.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-edac Pull edac updates from Mauro Carvalho Chehab: "Two EDAC fixes for Intel systems (Haswell and Ivy Bridge)" * tag 'edac/v4.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-edac: sb_edac: correctly fetch DIMM width on Ivy Bridge and Haswell sb_edac: look harder for DDRIO on Haswell systems
This commit is contained in:
Linus Torvalds
Коммит
d9b44fe30f
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@ -280,6 +280,7 @@ struct sbridge_info {
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u8 max_interleave;
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u8 (*get_node_id)(struct sbridge_pvt *pvt);
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enum mem_type (*get_memory_type)(struct sbridge_pvt *pvt);
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enum dev_type (*get_width)(struct sbridge_pvt *pvt, u32 mtr);
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struct pci_dev *pci_vtd;
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};
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@ -471,6 +472,9 @@ static const struct pci_id_table pci_dev_descr_ibridge_table[] = {
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#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2 0x2f6c
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#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3 0x2f6d
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#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0 0x2fbd
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#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1 0x2fbf
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#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2 0x2fb9
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#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3 0x2fbb
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static const struct pci_id_descr pci_dev_descr_haswell[] = {
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/* first item must be the HA */
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{ PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0, 0) },
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@ -488,6 +492,9 @@ static const struct pci_id_descr pci_dev_descr_haswell[] = {
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{ PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3, 1) },
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{ PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0, 1) },
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{ PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1, 1) },
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{ PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2, 1) },
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{ PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3, 1) },
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{ PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA, 1) },
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{ PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_THERMAL, 1) },
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@ -762,6 +769,49 @@ out:
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return mtype;
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}
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static enum dev_type sbridge_get_width(struct sbridge_pvt *pvt, u32 mtr)
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{
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/* there's no way to figure out */
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return DEV_UNKNOWN;
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}
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static enum dev_type __ibridge_get_width(u32 mtr)
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{
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enum dev_type type;
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switch (mtr) {
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case 3:
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type = DEV_UNKNOWN;
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break;
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case 2:
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type = DEV_X16;
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break;
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case 1:
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type = DEV_X8;
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break;
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case 0:
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type = DEV_X4;
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break;
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}
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return type;
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}
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static enum dev_type ibridge_get_width(struct sbridge_pvt *pvt, u32 mtr)
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{
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/*
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* ddr3_width on the documentation but also valid for DDR4 on
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* Haswell
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*/
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return __ibridge_get_width(GET_BITFIELD(mtr, 7, 8));
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}
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static enum dev_type broadwell_get_width(struct sbridge_pvt *pvt, u32 mtr)
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{
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/* ddr3_width on the documentation but also valid for DDR4 */
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return __ibridge_get_width(GET_BITFIELD(mtr, 8, 9));
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}
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static u8 get_node_id(struct sbridge_pvt *pvt)
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{
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u32 reg;
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@ -966,17 +1016,7 @@ static int get_dimm_config(struct mem_ctl_info *mci)
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dimm->nr_pages = npages;
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dimm->grain = 32;
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switch (banks) {
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case 16:
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dimm->dtype = DEV_X16;
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break;
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case 8:
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dimm->dtype = DEV_X8;
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break;
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case 4:
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dimm->dtype = DEV_X4;
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break;
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}
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dimm->dtype = pvt->info.get_width(pvt, mtr);
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dimm->mtype = mtype;
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dimm->edac_mode = mode;
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snprintf(dimm->label, sizeof(dimm->label),
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@ -1869,7 +1909,11 @@ static int haswell_mci_bind_devs(struct mem_ctl_info *mci,
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}
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break;
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case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0:
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pvt->pci_ddrio = pdev;
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case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1:
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case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2:
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case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3:
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if (!pvt->pci_ddrio)
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pvt->pci_ddrio = pdev;
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break;
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case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1:
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pvt->pci_ha1 = pdev;
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@ -2361,6 +2405,7 @@ static int sbridge_register_mci(struct sbridge_dev *sbridge_dev, enum type type)
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pvt->info.interleave_list = ibridge_interleave_list;
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pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list);
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pvt->info.interleave_pkg = ibridge_interleave_pkg;
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pvt->info.get_width = ibridge_get_width;
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mci->ctl_name = kasprintf(GFP_KERNEL, "Ivy Bridge Socket#%d", mci->mc_idx);
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/* Store pci devices at mci for faster access */
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@ -2380,6 +2425,7 @@ static int sbridge_register_mci(struct sbridge_dev *sbridge_dev, enum type type)
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pvt->info.interleave_list = sbridge_interleave_list;
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pvt->info.max_interleave = ARRAY_SIZE(sbridge_interleave_list);
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pvt->info.interleave_pkg = sbridge_interleave_pkg;
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pvt->info.get_width = sbridge_get_width;
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mci->ctl_name = kasprintf(GFP_KERNEL, "Sandy Bridge Socket#%d", mci->mc_idx);
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/* Store pci devices at mci for faster access */
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@ -2399,6 +2445,7 @@ static int sbridge_register_mci(struct sbridge_dev *sbridge_dev, enum type type)
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pvt->info.interleave_list = ibridge_interleave_list;
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pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list);
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pvt->info.interleave_pkg = ibridge_interleave_pkg;
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pvt->info.get_width = ibridge_get_width;
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mci->ctl_name = kasprintf(GFP_KERNEL, "Haswell Socket#%d", mci->mc_idx);
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/* Store pci devices at mci for faster access */
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@ -2418,6 +2465,7 @@ static int sbridge_register_mci(struct sbridge_dev *sbridge_dev, enum type type)
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pvt->info.interleave_list = ibridge_interleave_list;
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pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list);
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pvt->info.interleave_pkg = ibridge_interleave_pkg;
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pvt->info.get_width = broadwell_get_width;
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mci->ctl_name = kasprintf(GFP_KERNEL, "Broadwell Socket#%d", mci->mc_idx);
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/* Store pci devices at mci for faster access */
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