drm/i915/ringbuffer: Serialize load of PD_DIR
After triggering the mm switch with a load of PD_DIR, which may be deferred unto the MI_SET_CONTEXT on rcs, serialise the next commands with that load by posting a read of PD_DIR (or else those subsequent commands may access the stale page tables). Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Cc: Matthew Auld <matthew.william.auld@gmail.com> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180611171825.13678-2-chris@chris-wilson.co.uk
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@ -499,7 +499,8 @@ void intel_engine_setup_common(struct intel_engine_cs *engine)
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intel_engine_init_cmd_parser(engine);
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}
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int intel_engine_create_scratch(struct intel_engine_cs *engine, int size)
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int intel_engine_create_scratch(struct intel_engine_cs *engine,
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unsigned int size)
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{
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struct drm_i915_gem_object *obj;
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struct i915_vma *vma;
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@ -533,7 +534,7 @@ err_unref:
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return ret;
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}
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static void intel_engine_cleanup_scratch(struct intel_engine_cs *engine)
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void intel_engine_cleanup_scratch(struct intel_engine_cs *engine)
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{
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i915_vma_unpin_and_release(&engine->scratch);
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}
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@ -1361,8 +1361,9 @@ intel_ring_context_pin(struct intel_engine_cs *engine,
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static int intel_init_ring_buffer(struct intel_engine_cs *engine)
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{
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struct intel_ring *ring;
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struct i915_timeline *timeline;
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struct intel_ring *ring;
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unsigned int size;
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int err;
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intel_engine_setup_common(engine);
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@ -1388,12 +1389,21 @@ static int intel_init_ring_buffer(struct intel_engine_cs *engine)
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GEM_BUG_ON(engine->buffer);
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engine->buffer = ring;
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err = intel_engine_init_common(engine);
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size = PAGE_SIZE;
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if (HAS_BROKEN_CS_TLB(engine->i915))
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size = I830_WA_SIZE;
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err = intel_engine_create_scratch(engine, size);
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if (err)
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goto err_unpin;
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err = intel_engine_init_common(engine);
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if (err)
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goto err_scratch;
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return 0;
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err_scratch:
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intel_engine_cleanup_scratch(engine);
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err_unpin:
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intel_ring_unpin(ring);
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err_ring:
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@ -1455,6 +1465,25 @@ static int load_pd_dir(struct i915_request *rq,
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return 0;
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}
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static int flush_pd_dir(struct i915_request *rq)
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{
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const struct intel_engine_cs * const engine = rq->engine;
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u32 *cs;
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cs = intel_ring_begin(rq, 4);
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if (IS_ERR(cs))
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return PTR_ERR(cs);
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/* Stall until the page table load is complete */
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*cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
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*cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine));
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*cs++ = i915_ggtt_offset(engine->scratch);
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*cs++ = MI_NOOP;
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intel_ring_advance(rq, cs);
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return 0;
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}
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static inline int mi_set_context(struct i915_request *rq, u32 flags)
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{
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struct drm_i915_private *i915 = rq->i915;
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@ -1638,6 +1667,12 @@ static int switch_context(struct i915_request *rq)
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goto err_mm;
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}
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if (ppgtt) {
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ret = flush_pd_dir(rq);
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if (ret)
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goto err_mm;
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}
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if (ctx->remap_slice) {
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for (i = 0; i < MAX_L3_SLICES; i++) {
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if (!(ctx->remap_slice & BIT(i)))
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@ -2158,16 +2193,6 @@ int intel_init_render_ring_buffer(struct intel_engine_cs *engine)
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if (ret)
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return ret;
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if (INTEL_GEN(dev_priv) >= 6) {
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ret = intel_engine_create_scratch(engine, PAGE_SIZE);
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if (ret)
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return ret;
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} else if (HAS_BROKEN_CS_TLB(dev_priv)) {
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ret = intel_engine_create_scratch(engine, I830_WA_SIZE);
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if (ret)
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return ret;
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}
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return 0;
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}
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@ -869,9 +869,12 @@ void intel_engine_init_global_seqno(struct intel_engine_cs *engine, u32 seqno);
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void intel_engine_setup_common(struct intel_engine_cs *engine);
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int intel_engine_init_common(struct intel_engine_cs *engine);
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int intel_engine_create_scratch(struct intel_engine_cs *engine, int size);
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void intel_engine_cleanup_common(struct intel_engine_cs *engine);
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int intel_engine_create_scratch(struct intel_engine_cs *engine,
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unsigned int size);
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void intel_engine_cleanup_scratch(struct intel_engine_cs *engine);
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int intel_init_render_ring_buffer(struct intel_engine_cs *engine);
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int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine);
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int intel_init_blt_ring_buffer(struct intel_engine_cs *engine);
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