[ARM] 3029/1: Add HWUART support for PXA 255/26x
Patch from Matt Reimer Adds support for HWUART on PXA 255 / 26x. This patch originally came from http://svn.rungie.com/svn/gumstix-buildroot/trunk/sources/kernel-patches/000-gumstix-hwuart.patch and has been tweaked by me. Signed-off-by: Matt Reimer <mreimer@vpop.net> Signed-off-by: Nicolas Pitre <nico@cam.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Matt Reimer
Russell King
Родитель
80a18573ce
Коммит
d9e2964987
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@ -253,6 +253,10 @@ static struct platform_device stuart_device = {
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.name = "pxa2xx-uart",
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.id = 2,
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};
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static struct platform_device hwuart_device = {
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.name = "pxa2xx-uart",
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.id = 3,
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};
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static struct resource i2c_resources[] = {
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{
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@ -310,7 +314,19 @@ static struct platform_device *devices[] __initdata = {
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static int __init pxa_init(void)
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{
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return platform_add_devices(devices, ARRAY_SIZE(devices));
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int cpuid, ret;
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ret = platform_add_devices(devices, ARRAY_SIZE(devices));
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if (ret)
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return ret;
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/* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */
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cpuid = read_cpuid(CPUID_ID);
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if (((cpuid >> 4) & 0xfff) == 0x2d0 ||
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((cpuid >> 4) & 0xfff) == 0x290)
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ret = platform_device_register(&hwuart_device);
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return ret;
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}
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subsys_initcall(pxa_init);
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@ -358,6 +358,9 @@ static int serial_pxa_startup(struct uart_port *port)
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unsigned long flags;
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int retval;
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if (port->line == 3) /* HWUART */
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up->mcr |= UART_MCR_AFE;
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else
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up->mcr = 0;
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/*
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@ -481,8 +484,10 @@ serial_pxa_set_termios(struct uart_port *port, struct termios *termios,
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if ((up->port.uartclk / quot) < (2400 * 16))
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fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR1;
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else
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else if ((up->port.uartclk / quot) < (230400 * 16))
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fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR8;
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else
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fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR32;
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/*
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* Ok, we're now changing the port state. Do it with
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@ -772,6 +777,20 @@ static struct uart_pxa_port serial_pxa_ports[] = {
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.ops = &serial_pxa_pops,
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.line = 2,
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},
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}, { /* HWUART */
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.name = "HWUART",
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.cken = CKEN4_HWUART,
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.port = {
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.type = PORT_PXA,
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.iotype = UPIO_MEM,
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.membase = (void *)&HWUART,
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.mapbase = __PREG(HWUART),
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.irq = IRQ_HWUART,
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.uartclk = 921600 * 16,
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.fifosize = 64,
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.ops = &serial_pxa_pops,
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.line = 3,
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},
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}
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};
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@ -326,6 +326,25 @@
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#define STDLL __REG(0x40700000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
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#define STDLH __REG(0x40700004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
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/* Hardware UART (HWUART) */
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#define HWUART HWRBR
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#define HWRBR __REG(0x41600000) /* Receive Buffer Register (read only) */
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#define HWTHR __REG(0x41600000) /* Transmit Holding Register (write only) */
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#define HWIER __REG(0x41600004) /* Interrupt Enable Register (read/write) */
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#define HWIIR __REG(0x41600008) /* Interrupt ID Register (read only) */
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#define HWFCR __REG(0x41600008) /* FIFO Control Register (write only) */
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#define HWLCR __REG(0x4160000C) /* Line Control Register (read/write) */
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#define HWMCR __REG(0x41600010) /* Modem Control Register (read/write) */
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#define HWLSR __REG(0x41600014) /* Line Status Register (read only) */
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#define HWMSR __REG(0x41600018) /* Modem Status Register (read only) */
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#define HWSPR __REG(0x4160001C) /* Scratch Pad Register (read/write) */
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#define HWISR __REG(0x41600020) /* Infrared Selection Register (read/write) */
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#define HWFOR __REG(0x41600024) /* Receive FIFO Occupancy Register (read only) */
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#define HWABR __REG(0x41600028) /* Auto-Baud Control Register (read/write) */
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#define HWACR __REG(0x4160002C) /* Auto-Baud Count Register (read only) */
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#define HWDLL __REG(0x41600000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
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#define HWDLH __REG(0x41600004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
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#define IER_DMAE (1 << 7) /* DMA Requests Enable */
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#define IER_UUE (1 << 6) /* UART Unit Enable */
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#define IER_NRZE (1 << 5) /* NRZ coding Enable */
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@ -1250,9 +1269,13 @@
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#define GPIO40_FFDTR 40 /* FFUART data terminal Ready */
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#define GPIO41_FFRTS 41 /* FFUART request to send */
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#define GPIO42_BTRXD 42 /* BTUART receive data */
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#define GPIO42_HWRXD 42 /* HWUART receive data */
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#define GPIO43_BTTXD 43 /* BTUART transmit data */
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#define GPIO43_HWTXD 43 /* HWUART transmit data */
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#define GPIO44_BTCTS 44 /* BTUART clear to send */
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#define GPIO44_HWCTS 44 /* HWUART clear to send */
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#define GPIO45_BTRTS 45 /* BTUART request to send */
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#define GPIO45_HWRTS 45 /* HWUART request to send */
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#define GPIO45_AC97_SYSCLK 45 /* AC97 System Clock */
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#define GPIO46_ICPRXD 46 /* ICP receive data */
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#define GPIO46_STRXD 46 /* STD_UART receive data */
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@ -1378,17 +1401,26 @@
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#define GPIO40_FFDTR_MD (40 | GPIO_ALT_FN_2_OUT)
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#define GPIO41_FFRTS_MD (41 | GPIO_ALT_FN_2_OUT)
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#define GPIO42_BTRXD_MD (42 | GPIO_ALT_FN_1_IN)
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#define GPIO42_HWRXD_MD (42 | GPIO_ALT_FN_3_IN)
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#define GPIO43_BTTXD_MD (43 | GPIO_ALT_FN_2_OUT)
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#define GPIO43_HWTXD_MD (43 | GPIO_ALT_FN_3_OUT)
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#define GPIO44_BTCTS_MD (44 | GPIO_ALT_FN_1_IN)
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#define GPIO44_HWCTS_MD (44 | GPIO_ALT_FN_3_IN)
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#define GPIO45_BTRTS_MD (45 | GPIO_ALT_FN_2_OUT)
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#define GPIO45_HWRTS_MD (45 | GPIO_ALT_FN_3_OUT)
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#define GPIO45_SYSCLK_AC97_MD (45 | GPIO_ALT_FN_1_OUT)
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#define GPIO46_ICPRXD_MD (46 | GPIO_ALT_FN_1_IN)
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#define GPIO46_STRXD_MD (46 | GPIO_ALT_FN_2_IN)
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#define GPIO47_ICPTXD_MD (47 | GPIO_ALT_FN_2_OUT)
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#define GPIO47_STTXD_MD (47 | GPIO_ALT_FN_1_OUT)
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#define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT)
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#define GPIO48_HWTXD_MD (48 | GPIO_ALT_FN_1_OUT)
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#define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT)
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#define GPIO49_HWRXD_MD (49 | GPIO_ALT_FN_1_IN)
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#define GPIO49_nPWE_MD (49 | GPIO_ALT_FN_2_OUT)
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#define GPIO50_nPIOR_MD (50 | GPIO_ALT_FN_2_OUT)
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#define GPIO50_HWCTS_MD (50 | GPIO_ALT_FN_1_IN)
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#define GPIO51_HWRTS_MD (51 | GPIO_ALT_FN_1_OUT)
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#define GPIO51_nPIOW_MD (51 | GPIO_ALT_FN_2_OUT)
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#define GPIO52_nPCE_1_MD (52 | GPIO_ALT_FN_2_OUT)
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#define GPIO53_nPCE_2_MD (53 | GPIO_ALT_FN_2_OUT)
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@ -1763,6 +1795,7 @@
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#define CKEN7_BTUART (1 << 7) /* BTUART Unit Clock Enable */
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#define CKEN6_FFUART (1 << 6) /* FFUART Unit Clock Enable */
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#define CKEN5_STUART (1 << 5) /* STUART Unit Clock Enable */
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#define CKEN4_HWUART (1 << 4) /* HWUART Unit Clock Enable */
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#define CKEN4_SSP3 (1 << 4) /* SSP3 Unit Clock Enable */
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#define CKEN3_SSP (1 << 3) /* SSP Unit Clock Enable */
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#define CKEN3_SSP2 (1 << 3) /* SSP2 Unit Clock Enable */
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@ -12,6 +12,7 @@
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#define FFUART ((volatile unsigned long *)0x40100000)
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#define BTUART ((volatile unsigned long *)0x40200000)
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#define STUART ((volatile unsigned long *)0x40700000)
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#define HWUART ((volatile unsigned long *)0x41600000)
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#define UART FFUART
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