drm/i915: Remove the magic AUX_CTL is at DP + foo tricks
Currently we determine the location of the AUX registers in a confusing way. First we assume the PCH registers are used always, but then we override it for everything but HSW/BDW to use DP+0x10. Very confusing. Let's just make it straightforward and simply add a few functions to pick the right AUX_CTL based on the DP port. To deal with VLV/CHV we'll include the display_mmio_offset into the AUX register defines. v2: Reorder patches (Chris) Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> (v1) Link: http://patchwork.freedesktop.org/patch/msgid/1447266856-30249-5-git-send-email-ville.syrjala@linux.intel.com
This commit is contained in:
Ville Syrjälä
Родитель
750a951fd3
Коммит
da00bdcfb2
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@ -4228,33 +4228,33 @@ enum skl_disp_power_wells {
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* is 20 bytes in each direction, hence the 5 fixed
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* data registers
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*/
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#define _DPA_AUX_CH_CTL 0x64010
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#define _DPA_AUX_CH_DATA1 0x64014
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#define _DPA_AUX_CH_DATA2 0x64018
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#define _DPA_AUX_CH_DATA3 0x6401c
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#define _DPA_AUX_CH_DATA4 0x64020
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#define _DPA_AUX_CH_DATA5 0x64024
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#define _DPA_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64010)
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#define _DPA_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64014)
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#define _DPA_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64018)
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#define _DPA_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6401c)
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#define _DPA_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64020)
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#define _DPA_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64024)
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#define _DPB_AUX_CH_CTL 0x64110
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#define _DPB_AUX_CH_DATA1 0x64114
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#define _DPB_AUX_CH_DATA2 0x64118
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#define _DPB_AUX_CH_DATA3 0x6411c
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#define _DPB_AUX_CH_DATA4 0x64120
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#define _DPB_AUX_CH_DATA5 0x64124
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#define _DPB_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64110)
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#define _DPB_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64114)
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#define _DPB_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64118)
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#define _DPB_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6411c)
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#define _DPB_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64120)
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#define _DPB_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64124)
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#define _DPC_AUX_CH_CTL 0x64210
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#define _DPC_AUX_CH_DATA1 0x64214
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#define _DPC_AUX_CH_DATA2 0x64218
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#define _DPC_AUX_CH_DATA3 0x6421c
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#define _DPC_AUX_CH_DATA4 0x64220
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#define _DPC_AUX_CH_DATA5 0x64224
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#define _DPC_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64210)
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#define _DPC_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64214)
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#define _DPC_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64218)
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#define _DPC_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6421c)
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#define _DPC_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64220)
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#define _DPC_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64224)
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#define _DPD_AUX_CH_CTL 0x64310
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#define _DPD_AUX_CH_DATA1 0x64314
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#define _DPD_AUX_CH_DATA2 0x64318
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#define _DPD_AUX_CH_DATA3 0x6431c
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#define _DPD_AUX_CH_DATA4 0x64320
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#define _DPD_AUX_CH_DATA5 0x64324
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#define _DPD_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64310)
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#define _DPD_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64314)
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#define _DPD_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64318)
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#define _DPD_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6431c)
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#define _DPD_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64320)
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#define _DPD_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64324)
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#define DP_AUX_CH_CTL(port) _PORT(port, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
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#define DP_AUX_CH_DATA(port, i) (_PORT(port, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
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@ -1008,6 +1008,78 @@ intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
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return ret;
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}
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static uint32_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
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enum port port)
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{
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switch (port) {
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case PORT_B:
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case PORT_C:
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case PORT_D:
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return DP_AUX_CH_CTL(port);
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default:
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MISSING_CASE(port);
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return DP_AUX_CH_CTL(PORT_B);
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}
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}
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static uint32_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
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enum port port)
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{
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switch (port) {
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case PORT_A:
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return DP_AUX_CH_CTL(port);
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case PORT_B:
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case PORT_C:
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case PORT_D:
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return PCH_DP_AUX_CH_CTL(port);
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default:
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MISSING_CASE(port);
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return DP_AUX_CH_CTL(PORT_A);
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}
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}
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/*
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* On SKL we don't have Aux for port E so we rely
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* on VBT to set a proper alternate aux channel.
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*/
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static enum port skl_porte_aux_port(struct drm_i915_private *dev_priv)
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{
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const struct ddi_vbt_port_info *info =
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&dev_priv->vbt.ddi_port_info[PORT_E];
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switch (info->alternate_aux_channel) {
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case DP_AUX_A:
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return PORT_A;
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case DP_AUX_B:
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return PORT_B;
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case DP_AUX_C:
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return PORT_C;
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case DP_AUX_D:
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return PORT_D;
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default:
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MISSING_CASE(info->alternate_aux_channel);
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return PORT_A;
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}
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}
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static uint32_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
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enum port port)
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{
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if (port == PORT_E)
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port = skl_porte_aux_port(dev_priv);
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switch (port) {
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case PORT_A:
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case PORT_B:
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case PORT_C:
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case PORT_D:
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return DP_AUX_CH_CTL(port);
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default:
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MISSING_CASE(port);
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return DP_AUX_CH_CTL(PORT_A);
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}
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}
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static void
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intel_dp_aux_fini(struct intel_dp *intel_dp)
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{
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@ -1022,57 +1094,14 @@ intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
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enum port port = intel_dig_port->port;
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struct ddi_vbt_port_info *info = &dev_priv->vbt.ddi_port_info[port];
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uint32_t porte_aux_ctl_reg = DP_AUX_CH_CTL(PORT_A);
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int ret;
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/* On SKL we don't have Aux for port E so we rely on VBT to set
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* a proper alternate aux channel.
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*/
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if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && port == PORT_E) {
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switch (info->alternate_aux_channel) {
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case DP_AUX_B:
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porte_aux_ctl_reg = DP_AUX_CH_CTL(PORT_B);
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break;
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case DP_AUX_C:
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porte_aux_ctl_reg = DP_AUX_CH_CTL(PORT_C);
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break;
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case DP_AUX_D:
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porte_aux_ctl_reg = DP_AUX_CH_CTL(PORT_D);
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break;
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case DP_AUX_A:
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default:
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porte_aux_ctl_reg = DP_AUX_CH_CTL(PORT_A);
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}
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}
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switch (port) {
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case PORT_A:
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intel_dp->aux_ch_ctl_reg = DP_AUX_CH_CTL(port);
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break;
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case PORT_B:
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case PORT_C:
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case PORT_D:
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intel_dp->aux_ch_ctl_reg = PCH_DP_AUX_CH_CTL(port);
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break;
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case PORT_E:
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intel_dp->aux_ch_ctl_reg = porte_aux_ctl_reg;
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break;
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default:
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BUG();
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}
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/*
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* The AUX_CTL register is usually DP_CTL + 0x10.
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*
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* On Haswell and Broadwell though:
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* - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU
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* - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU
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*
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* Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU.
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*/
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if (!IS_HASWELL(dev) && !IS_BROADWELL(dev) && port != PORT_E)
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intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
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if (INTEL_INFO(dev_priv)->gen >= 9)
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intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg(dev_priv, port);
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else if (HAS_PCH_SPLIT(dev_priv))
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intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg(dev_priv, port);
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else
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intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg(dev_priv, port);
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intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port));
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if (!intel_dp->aux.name)
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