phy: cadence-torrent: Add PHY registers for DP in array format
Add PHY registers for single link DP in array format to simplify code and to improve readability. This supports already supported frequencies for DP of 19.2MHz and 25MHz. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20210728145454.15945-6-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Swapnil Jakhade
Vinod Koul
Родитель
6a2338a5bf
Коммит
da055e5503
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@ -572,50 +572,6 @@ static const struct coefficients vltg_coeff[4][4] = {
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}
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};
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static
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void cdns_torrent_dp_pma_cmn_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy)
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{
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struct regmap *regmap = cdns_phy->regmap_common_cdb;
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/* refclock registers - assumes 19.2 MHz refclock */
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cdns_torrent_phy_write(regmap, CMN_SSM_BIAS_TMR, 0x0014);
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cdns_torrent_phy_write(regmap, CMN_PLLSM0_PLLPRE_TMR, 0x0027);
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cdns_torrent_phy_write(regmap, CMN_PLLSM0_PLLLOCK_TMR, 0x00A1);
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cdns_torrent_phy_write(regmap, CMN_PLLSM1_PLLPRE_TMR, 0x0027);
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cdns_torrent_phy_write(regmap, CMN_PLLSM1_PLLLOCK_TMR, 0x00A1);
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cdns_torrent_phy_write(regmap, CMN_BGCAL_INIT_TMR, 0x0060);
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cdns_torrent_phy_write(regmap, CMN_BGCAL_ITER_TMR, 0x0060);
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cdns_torrent_phy_write(regmap, CMN_IBCAL_INIT_TMR, 0x0014);
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cdns_torrent_phy_write(regmap, CMN_TXPUCAL_INIT_TMR, 0x0018);
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cdns_torrent_phy_write(regmap, CMN_TXPUCAL_ITER_TMR, 0x0005);
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cdns_torrent_phy_write(regmap, CMN_TXPDCAL_INIT_TMR, 0x0018);
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cdns_torrent_phy_write(regmap, CMN_TXPDCAL_ITER_TMR, 0x0005);
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cdns_torrent_phy_write(regmap, CMN_RXCAL_INIT_TMR, 0x0240);
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cdns_torrent_phy_write(regmap, CMN_RXCAL_ITER_TMR, 0x0005);
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cdns_torrent_phy_write(regmap, CMN_SD_CAL_INIT_TMR, 0x0002);
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cdns_torrent_phy_write(regmap, CMN_SD_CAL_ITER_TMR, 0x0002);
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cdns_torrent_phy_write(regmap, CMN_SD_CAL_REFTIM_START, 0x000B);
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cdns_torrent_phy_write(regmap, CMN_SD_CAL_PLLCNT_START, 0x0137);
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/* PLL registers */
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cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509);
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cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00);
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cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08);
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cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004);
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cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509);
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cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00);
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cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08);
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cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004);
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cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_INIT_TMR, 0x00C0);
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cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_ITER_TMR, 0x0004);
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cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_INIT_TMR, 0x00C0);
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cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_ITER_TMR, 0x0004);
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cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_REFTIM_START, 0x0260);
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cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_TCTRL, 0x0003);
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cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_REFTIM_START, 0x0260);
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cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_TCTRL, 0x0003);
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}
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/*
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* Set registers responsible for enabling and configuring SSC, with second and
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* third register values provided by parameters.
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@ -647,148 +603,88 @@ void cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy,
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/* Setting VCO for 10.8GHz */
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case 2700:
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case 5400:
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cdns_torrent_phy_write(regmap,
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CMN_PLL0_INTDIV_M0, 0x0119);
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cdns_torrent_phy_write(regmap,
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CMN_PLL0_FRACDIVL_M0, 0x4000);
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cdns_torrent_phy_write(regmap,
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CMN_PLL0_FRACDIVH_M0, 0x0002);
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cdns_torrent_phy_write(regmap,
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CMN_PLL0_HIGH_THR_M0, 0x00BC);
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cdns_torrent_phy_write(regmap,
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CMN_PDIAG_PLL0_CTRL_M0, 0x0012);
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cdns_torrent_phy_write(regmap,
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CMN_PLL1_INTDIV_M0, 0x0119);
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cdns_torrent_phy_write(regmap,
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CMN_PLL1_FRACDIVL_M0, 0x4000);
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cdns_torrent_phy_write(regmap,
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CMN_PLL1_FRACDIVH_M0, 0x0002);
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cdns_torrent_phy_write(regmap,
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CMN_PLL1_HIGH_THR_M0, 0x00BC);
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cdns_torrent_phy_write(regmap,
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CMN_PDIAG_PLL1_CTRL_M0, 0x0012);
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cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0119);
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cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x4000);
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cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
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cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x00BC);
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cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0012);
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cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0119);
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cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x4000);
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cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
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cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x00BC);
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cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0012);
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if (ssc)
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cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x033A,
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0x006A);
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cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x033A, 0x006A);
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break;
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/* Setting VCO for 9.72GHz */
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case 1620:
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case 2430:
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case 3240:
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cdns_torrent_phy_write(regmap,
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CMN_PLL0_INTDIV_M0, 0x01FA);
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cdns_torrent_phy_write(regmap,
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CMN_PLL0_FRACDIVL_M0, 0x4000);
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cdns_torrent_phy_write(regmap,
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CMN_PLL0_FRACDIVH_M0, 0x0002);
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cdns_torrent_phy_write(regmap,
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CMN_PLL0_HIGH_THR_M0, 0x0152);
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cdns_torrent_phy_write(regmap,
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CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
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cdns_torrent_phy_write(regmap,
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CMN_PLL1_INTDIV_M0, 0x01FA);
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cdns_torrent_phy_write(regmap,
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CMN_PLL1_FRACDIVL_M0, 0x4000);
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cdns_torrent_phy_write(regmap,
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CMN_PLL1_FRACDIVH_M0, 0x0002);
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cdns_torrent_phy_write(regmap,
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CMN_PLL1_HIGH_THR_M0, 0x0152);
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cdns_torrent_phy_write(regmap,
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CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
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cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01FA);
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cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x4000);
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cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
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cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0152);
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cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
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cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01FA);
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cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x4000);
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cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
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cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0152);
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cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
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if (ssc)
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cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x05DD,
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0x0069);
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cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x05DD, 0x0069);
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break;
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/* Setting VCO for 8.64GHz */
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case 2160:
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case 4320:
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cdns_torrent_phy_write(regmap,
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CMN_PLL0_INTDIV_M0, 0x01C2);
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cdns_torrent_phy_write(regmap,
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CMN_PLL0_FRACDIVL_M0, 0x0000);
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cdns_torrent_phy_write(regmap,
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CMN_PLL0_FRACDIVH_M0, 0x0002);
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cdns_torrent_phy_write(regmap,
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CMN_PLL0_HIGH_THR_M0, 0x012C);
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cdns_torrent_phy_write(regmap,
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CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
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cdns_torrent_phy_write(regmap,
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CMN_PLL1_INTDIV_M0, 0x01C2);
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cdns_torrent_phy_write(regmap,
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CMN_PLL1_FRACDIVL_M0, 0x0000);
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cdns_torrent_phy_write(regmap,
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CMN_PLL1_FRACDIVH_M0, 0x0002);
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cdns_torrent_phy_write(regmap,
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CMN_PLL1_HIGH_THR_M0, 0x012C);
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cdns_torrent_phy_write(regmap,
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CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
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cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01C2);
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cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x0000);
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cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
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cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x012C);
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cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
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cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01C2);
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cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x0000);
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cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
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cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x012C);
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cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
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if (ssc)
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cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x0536,
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0x0069);
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cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x0536, 0x0069);
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break;
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/* Setting VCO for 8.1GHz */
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case 8100:
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cdns_torrent_phy_write(regmap,
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CMN_PLL0_INTDIV_M0, 0x01A5);
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cdns_torrent_phy_write(regmap,
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CMN_PLL0_FRACDIVL_M0, 0xE000);
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cdns_torrent_phy_write(regmap,
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CMN_PLL0_FRACDIVH_M0, 0x0002);
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cdns_torrent_phy_write(regmap,
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CMN_PLL0_HIGH_THR_M0, 0x011A);
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cdns_torrent_phy_write(regmap,
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CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
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cdns_torrent_phy_write(regmap,
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CMN_PLL1_INTDIV_M0, 0x01A5);
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cdns_torrent_phy_write(regmap,
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CMN_PLL1_FRACDIVL_M0, 0xE000);
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cdns_torrent_phy_write(regmap,
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CMN_PLL1_FRACDIVH_M0, 0x0002);
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cdns_torrent_phy_write(regmap,
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CMN_PLL1_HIGH_THR_M0, 0x011A);
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cdns_torrent_phy_write(regmap,
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CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
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cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01A5);
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cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0xE000);
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cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
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cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x011A);
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cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
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cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01A5);
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cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0xE000);
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cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
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cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x011A);
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cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
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if (ssc)
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cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x04D7,
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0x006A);
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cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x04D7, 0x006A);
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break;
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}
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if (ssc) {
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cdns_torrent_phy_write(regmap,
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CMN_PLL0_VCOCAL_PLLCNT_START, 0x025E);
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cdns_torrent_phy_write(regmap,
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CMN_PLL0_LOCK_PLLCNT_THR, 0x0005);
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cdns_torrent_phy_write(regmap,
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CMN_PLL1_VCOCAL_PLLCNT_START, 0x025E);
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cdns_torrent_phy_write(regmap,
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CMN_PLL1_LOCK_PLLCNT_THR, 0x0005);
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cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_PLLCNT_START, 0x025E);
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cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_THR, 0x0005);
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cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_PLLCNT_START, 0x025E);
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cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_THR, 0x0005);
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} else {
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cdns_torrent_phy_write(regmap,
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CMN_PLL0_VCOCAL_PLLCNT_START, 0x0260);
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cdns_torrent_phy_write(regmap,
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CMN_PLL1_VCOCAL_PLLCNT_START, 0x0260);
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cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_PLLCNT_START, 0x0260);
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cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_PLLCNT_START, 0x0260);
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/* Set reset register values to disable SSC */
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cdns_torrent_phy_write(regmap,
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CMN_PLL0_SS_CTRL1_M0, 0x0002);
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cdns_torrent_phy_write(regmap,
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CMN_PLL0_SS_CTRL2_M0, 0x0000);
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cdns_torrent_phy_write(regmap,
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CMN_PLL0_SS_CTRL3_M0, 0x0000);
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cdns_torrent_phy_write(regmap,
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CMN_PLL0_SS_CTRL4_M0, 0x0000);
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cdns_torrent_phy_write(regmap,
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CMN_PLL0_LOCK_PLLCNT_THR, 0x0003);
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cdns_torrent_phy_write(regmap,
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CMN_PLL1_SS_CTRL1_M0, 0x0002);
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cdns_torrent_phy_write(regmap,
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CMN_PLL1_SS_CTRL2_M0, 0x0000);
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cdns_torrent_phy_write(regmap,
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CMN_PLL1_SS_CTRL3_M0, 0x0000);
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cdns_torrent_phy_write(regmap,
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CMN_PLL1_SS_CTRL4_M0, 0x0000);
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cdns_torrent_phy_write(regmap,
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CMN_PLL1_LOCK_PLLCNT_THR, 0x0003);
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cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0002);
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cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL2_M0, 0x0000);
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cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL3_M0, 0x0000);
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cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0000);
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cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_THR, 0x0003);
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cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0002);
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cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL2_M0, 0x0000);
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cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL3_M0, 0x0000);
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cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0000);
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cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_THR, 0x0003);
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}
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cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_REFCNT_START, 0x0099);
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@ -797,50 +693,6 @@ void cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy,
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cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_START, 0x0099);
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}
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static
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void cdns_torrent_dp_pma_cmn_cfg_25mhz(struct cdns_torrent_phy *cdns_phy)
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{
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struct regmap *regmap = cdns_phy->regmap_common_cdb;
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/* refclock registers - assumes 25 MHz refclock */
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cdns_torrent_phy_write(regmap, CMN_SSM_BIAS_TMR, 0x0019);
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cdns_torrent_phy_write(regmap, CMN_PLLSM0_PLLPRE_TMR, 0x0032);
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cdns_torrent_phy_write(regmap, CMN_PLLSM0_PLLLOCK_TMR, 0x00D1);
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cdns_torrent_phy_write(regmap, CMN_PLLSM1_PLLPRE_TMR, 0x0032);
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cdns_torrent_phy_write(regmap, CMN_PLLSM1_PLLLOCK_TMR, 0x00D1);
|
||||
cdns_torrent_phy_write(regmap, CMN_BGCAL_INIT_TMR, 0x007D);
|
||||
cdns_torrent_phy_write(regmap, CMN_BGCAL_ITER_TMR, 0x007D);
|
||||
cdns_torrent_phy_write(regmap, CMN_IBCAL_INIT_TMR, 0x0019);
|
||||
cdns_torrent_phy_write(regmap, CMN_TXPUCAL_INIT_TMR, 0x001E);
|
||||
cdns_torrent_phy_write(regmap, CMN_TXPUCAL_ITER_TMR, 0x0006);
|
||||
cdns_torrent_phy_write(regmap, CMN_TXPDCAL_INIT_TMR, 0x001E);
|
||||
cdns_torrent_phy_write(regmap, CMN_TXPDCAL_ITER_TMR, 0x0006);
|
||||
cdns_torrent_phy_write(regmap, CMN_RXCAL_INIT_TMR, 0x02EE);
|
||||
cdns_torrent_phy_write(regmap, CMN_RXCAL_ITER_TMR, 0x0006);
|
||||
cdns_torrent_phy_write(regmap, CMN_SD_CAL_INIT_TMR, 0x0002);
|
||||
cdns_torrent_phy_write(regmap, CMN_SD_CAL_ITER_TMR, 0x0002);
|
||||
cdns_torrent_phy_write(regmap, CMN_SD_CAL_REFTIM_START, 0x000E);
|
||||
cdns_torrent_phy_write(regmap, CMN_SD_CAL_PLLCNT_START, 0x012B);
|
||||
|
||||
/* PLL registers */
|
||||
cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509);
|
||||
cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00);
|
||||
cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08);
|
||||
cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004);
|
||||
cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509);
|
||||
cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00);
|
||||
cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08);
|
||||
cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004);
|
||||
cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_INIT_TMR, 0x00FA);
|
||||
cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_ITER_TMR, 0x0004);
|
||||
cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_INIT_TMR, 0x00FA);
|
||||
cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_ITER_TMR, 0x0004);
|
||||
cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_REFTIM_START, 0x0317);
|
||||
cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_TCTRL, 0x0003);
|
||||
cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_REFTIM_START, 0x0317);
|
||||
cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_TCTRL, 0x0003);
|
||||
}
|
||||
|
||||
/*
|
||||
* Set registers responsible for enabling and configuring SSC, with second
|
||||
* register value provided by a parameter.
|
||||
|
|
@ -964,66 +816,6 @@ void cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(struct cdns_torrent_phy *cdns_phy,
|
|||
cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_START, 0x00C7);
|
||||
}
|
||||
|
||||
static void cdns_torrent_dp_pma_lane_cfg(struct cdns_torrent_phy *cdns_phy,
|
||||
unsigned int lane)
|
||||
{
|
||||
/* Per lane, refclock-dependent receiver detection setting */
|
||||
if (cdns_phy->ref_clk_rate == CLK_19_2_MHZ)
|
||||
cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
|
||||
TX_RCVDET_ST_TMR, 0x0780);
|
||||
else if (cdns_phy->ref_clk_rate == CLK_25_MHZ)
|
||||
cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
|
||||
TX_RCVDET_ST_TMR, 0x09C4);
|
||||
|
||||
/* Writing Tx/Rx Power State Controllers registers */
|
||||
cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
|
||||
TX_PSC_A0, 0x00FB);
|
||||
cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
|
||||
TX_PSC_A2, 0x04AA);
|
||||
cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
|
||||
TX_PSC_A3, 0x04AA);
|
||||
cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane],
|
||||
RX_PSC_A0, 0x0000);
|
||||
cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane],
|
||||
RX_PSC_A2, 0x0000);
|
||||
cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane],
|
||||
RX_PSC_A3, 0x0000);
|
||||
|
||||
cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane],
|
||||
RX_PSC_CAL, 0x0000);
|
||||
|
||||
cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane],
|
||||
RX_REE_GCSM1_CTRL, 0x0000);
|
||||
cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane],
|
||||
RX_REE_GCSM2_CTRL, 0x0000);
|
||||
cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane],
|
||||
RX_REE_PERGCSM_CTRL, 0x0000);
|
||||
|
||||
cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
|
||||
XCVR_DIAG_BIDI_CTRL, 0x000F);
|
||||
cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
|
||||
XCVR_DIAG_PLLDRC_CTRL, 0x0001);
|
||||
cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
|
||||
XCVR_DIAG_HSCLK_SEL, 0x0000);
|
||||
}
|
||||
|
||||
static void cdns_torrent_dp_pma_cfg(struct cdns_torrent_phy *cdns_phy,
|
||||
struct cdns_torrent_inst *inst)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
if (cdns_phy->ref_clk_rate == CLK_19_2_MHZ)
|
||||
/* PMA common configuration 19.2MHz */
|
||||
cdns_torrent_dp_pma_cmn_cfg_19_2mhz(cdns_phy);
|
||||
else if (cdns_phy->ref_clk_rate == CLK_25_MHZ)
|
||||
/* PMA common configuration 25MHz */
|
||||
cdns_torrent_dp_pma_cmn_cfg_25mhz(cdns_phy);
|
||||
|
||||
/* PMA lane configuration to deal with multi-link operation */
|
||||
for (i = 0; i < inst->num_lanes; i++)
|
||||
cdns_torrent_dp_pma_lane_cfg(cdns_phy, i);
|
||||
}
|
||||
|
||||
/*
|
||||
* Enable or disable PLL for selected lanes.
|
||||
*/
|
||||
|
|
@ -1196,9 +988,6 @@ static void cdns_torrent_dp_pma_cmn_rate(struct cdns_torrent_phy *cdns_phy,
|
|||
unsigned int hsclk_div_val = 0;
|
||||
unsigned int i;
|
||||
|
||||
/* 16'h0000 for single DP link configuration */
|
||||
regmap_field_write(cdns_phy->phy_pll_cfg, 0x0);
|
||||
|
||||
switch (rate) {
|
||||
case 1620:
|
||||
clk_sel_val = 0x0f01;
|
||||
|
|
@ -1243,8 +1032,7 @@ static void cdns_torrent_dp_pma_cmn_rate(struct cdns_torrent_phy *cdns_phy,
|
|||
static int cdns_torrent_dp_configure_rate(struct cdns_torrent_phy *cdns_phy,
|
||||
struct phy_configure_opts_dp *dp)
|
||||
{
|
||||
u32 ret;
|
||||
u32 read_val;
|
||||
u32 read_val, ret;
|
||||
|
||||
/* Disable the cmn_pll0_en before re-programming the new data rate. */
|
||||
regmap_field_write(cdns_phy->phy_pma_pll_raw_ctrl, 0x0);
|
||||
|
|
@ -1262,17 +1050,12 @@ static int cdns_torrent_dp_configure_rate(struct cdns_torrent_phy *cdns_phy,
|
|||
ndelay(200);
|
||||
|
||||
/* DP Rate Change - VCO Output settings. */
|
||||
if (cdns_phy->ref_clk_rate == CLK_19_2_MHZ) {
|
||||
if (cdns_phy->ref_clk_rate == CLK_19_2_MHZ)
|
||||
/* PMA common configuration 19.2MHz */
|
||||
cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(cdns_phy, dp->link_rate,
|
||||
dp->ssc);
|
||||
cdns_torrent_dp_pma_cmn_cfg_19_2mhz(cdns_phy);
|
||||
} else if (cdns_phy->ref_clk_rate == CLK_25_MHZ) {
|
||||
cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(cdns_phy, dp->link_rate, dp->ssc);
|
||||
else if (cdns_phy->ref_clk_rate == CLK_25_MHZ)
|
||||
/* PMA common configuration 25MHz */
|
||||
cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy, dp->link_rate,
|
||||
dp->ssc);
|
||||
cdns_torrent_dp_pma_cmn_cfg_25mhz(cdns_phy);
|
||||
}
|
||||
cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy, dp->link_rate, dp->ssc);
|
||||
cdns_torrent_dp_pma_cmn_rate(cdns_phy, dp->link_rate, dp->lanes);
|
||||
|
||||
/* Enable the cmn_pll0_en. */
|
||||
|
|
@ -1621,9 +1404,6 @@ static int cdns_torrent_dp_init(struct phy *phy)
|
|||
|
||||
cdns_torrent_dp_write(regmap, PHY_AUX_CTRL, 0x0003); /* enable AUX */
|
||||
|
||||
/* PHY PMA registers configuration function */
|
||||
cdns_torrent_dp_pma_cfg(cdns_phy, inst);
|
||||
|
||||
/*
|
||||
* Set lines power state to A0
|
||||
* Set lines pll clk enable to 0
|
||||
|
|
@ -1957,9 +1737,6 @@ static int cdns_torrent_phy_init(struct phy *phy)
|
|||
if (cdns_phy->nsubnodes > 1)
|
||||
return 0;
|
||||
|
||||
if (phy_type == TYPE_DP)
|
||||
return cdns_torrent_dp_init(phy);
|
||||
|
||||
/**
|
||||
* Spread spectrum generation is not required or supported
|
||||
* for SGMII/QSGMII
|
||||
|
|
@ -2045,6 +1822,9 @@ static int cdns_torrent_phy_init(struct phy *phy)
|
|||
}
|
||||
}
|
||||
|
||||
if (phy_type == TYPE_DP)
|
||||
return cdns_torrent_dp_init(phy);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -2569,6 +2349,168 @@ static int cdns_torrent_phy_remove(struct platform_device *pdev)
|
|||
return 0;
|
||||
}
|
||||
|
||||
/* Single DisplayPort(DP) link configuration */
|
||||
static struct cdns_reg_pairs sl_dp_link_cmn_regs[] = {
|
||||
{0x0000, PHY_PLL_CFG},
|
||||
};
|
||||
|
||||
static struct cdns_reg_pairs sl_dp_xcvr_diag_ln_regs[] = {
|
||||
{0x0000, XCVR_DIAG_HSCLK_SEL},
|
||||
{0x0001, XCVR_DIAG_PLLDRC_CTRL}
|
||||
};
|
||||
|
||||
static struct cdns_torrent_vals sl_dp_link_cmn_vals = {
|
||||
.reg_pairs = sl_dp_link_cmn_regs,
|
||||
.num_regs = ARRAY_SIZE(sl_dp_link_cmn_regs),
|
||||
};
|
||||
|
||||
static struct cdns_torrent_vals sl_dp_xcvr_diag_ln_vals = {
|
||||
.reg_pairs = sl_dp_xcvr_diag_ln_regs,
|
||||
.num_regs = ARRAY_SIZE(sl_dp_xcvr_diag_ln_regs),
|
||||
};
|
||||
|
||||
/* Single DP, 19.2 MHz Ref clk, no SSC */
|
||||
static struct cdns_reg_pairs sl_dp_19_2_no_ssc_cmn_regs[] = {
|
||||
{0x0014, CMN_SSM_BIAS_TMR},
|
||||
{0x0027, CMN_PLLSM0_PLLPRE_TMR},
|
||||
{0x00A1, CMN_PLLSM0_PLLLOCK_TMR},
|
||||
{0x0027, CMN_PLLSM1_PLLPRE_TMR},
|
||||
{0x00A1, CMN_PLLSM1_PLLLOCK_TMR},
|
||||
{0x0060, CMN_BGCAL_INIT_TMR},
|
||||
{0x0060, CMN_BGCAL_ITER_TMR},
|
||||
{0x0014, CMN_IBCAL_INIT_TMR},
|
||||
{0x0018, CMN_TXPUCAL_INIT_TMR},
|
||||
{0x0005, CMN_TXPUCAL_ITER_TMR},
|
||||
{0x0018, CMN_TXPDCAL_INIT_TMR},
|
||||
{0x0005, CMN_TXPDCAL_ITER_TMR},
|
||||
{0x0240, CMN_RXCAL_INIT_TMR},
|
||||
{0x0005, CMN_RXCAL_ITER_TMR},
|
||||
{0x0002, CMN_SD_CAL_INIT_TMR},
|
||||
{0x0002, CMN_SD_CAL_ITER_TMR},
|
||||
{0x000B, CMN_SD_CAL_REFTIM_START},
|
||||
{0x0137, CMN_SD_CAL_PLLCNT_START},
|
||||
{0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
|
||||
{0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
|
||||
{0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
|
||||
{0x0004, CMN_PLL0_DSM_DIAG_M0},
|
||||
{0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
|
||||
{0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
|
||||
{0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
|
||||
{0x0004, CMN_PLL1_DSM_DIAG_M0},
|
||||
{0x00C0, CMN_PLL0_VCOCAL_INIT_TMR},
|
||||
{0x0004, CMN_PLL0_VCOCAL_ITER_TMR},
|
||||
{0x00C0, CMN_PLL1_VCOCAL_INIT_TMR},
|
||||
{0x0004, CMN_PLL1_VCOCAL_ITER_TMR},
|
||||
{0x0260, CMN_PLL0_VCOCAL_REFTIM_START},
|
||||
{0x0003, CMN_PLL0_VCOCAL_TCTRL},
|
||||
{0x0260, CMN_PLL1_VCOCAL_REFTIM_START},
|
||||
{0x0003, CMN_PLL1_VCOCAL_TCTRL}
|
||||
};
|
||||
|
||||
static struct cdns_reg_pairs sl_dp_19_2_no_ssc_tx_ln_regs[] = {
|
||||
{0x0780, TX_RCVDET_ST_TMR},
|
||||
{0x00FB, TX_PSC_A0},
|
||||
{0x04AA, TX_PSC_A2},
|
||||
{0x04AA, TX_PSC_A3},
|
||||
{0x000F, XCVR_DIAG_BIDI_CTRL}
|
||||
};
|
||||
|
||||
static struct cdns_reg_pairs sl_dp_19_2_no_ssc_rx_ln_regs[] = {
|
||||
{0x0000, RX_PSC_A0},
|
||||
{0x0000, RX_PSC_A2},
|
||||
{0x0000, RX_PSC_A3},
|
||||
{0x0000, RX_PSC_CAL},
|
||||
{0x0000, RX_REE_GCSM1_CTRL},
|
||||
{0x0000, RX_REE_GCSM2_CTRL},
|
||||
{0x0000, RX_REE_PERGCSM_CTRL}
|
||||
};
|
||||
|
||||
static struct cdns_torrent_vals sl_dp_19_2_no_ssc_cmn_vals = {
|
||||
.reg_pairs = sl_dp_19_2_no_ssc_cmn_regs,
|
||||
.num_regs = ARRAY_SIZE(sl_dp_19_2_no_ssc_cmn_regs),
|
||||
};
|
||||
|
||||
static struct cdns_torrent_vals sl_dp_19_2_no_ssc_tx_ln_vals = {
|
||||
.reg_pairs = sl_dp_19_2_no_ssc_tx_ln_regs,
|
||||
.num_regs = ARRAY_SIZE(sl_dp_19_2_no_ssc_tx_ln_regs),
|
||||
};
|
||||
|
||||
static struct cdns_torrent_vals sl_dp_19_2_no_ssc_rx_ln_vals = {
|
||||
.reg_pairs = sl_dp_19_2_no_ssc_rx_ln_regs,
|
||||
.num_regs = ARRAY_SIZE(sl_dp_19_2_no_ssc_rx_ln_regs),
|
||||
};
|
||||
|
||||
/* Single DP, 25 MHz Ref clk, no SSC */
|
||||
static struct cdns_reg_pairs sl_dp_25_no_ssc_cmn_regs[] = {
|
||||
{0x0019, CMN_SSM_BIAS_TMR},
|
||||
{0x0032, CMN_PLLSM0_PLLPRE_TMR},
|
||||
{0x00D1, CMN_PLLSM0_PLLLOCK_TMR},
|
||||
{0x0032, CMN_PLLSM1_PLLPRE_TMR},
|
||||
{0x00D1, CMN_PLLSM1_PLLLOCK_TMR},
|
||||
{0x007D, CMN_BGCAL_INIT_TMR},
|
||||
{0x007D, CMN_BGCAL_ITER_TMR},
|
||||
{0x0019, CMN_IBCAL_INIT_TMR},
|
||||
{0x001E, CMN_TXPUCAL_INIT_TMR},
|
||||
{0x0006, CMN_TXPUCAL_ITER_TMR},
|
||||
{0x001E, CMN_TXPDCAL_INIT_TMR},
|
||||
{0x0006, CMN_TXPDCAL_ITER_TMR},
|
||||
{0x02EE, CMN_RXCAL_INIT_TMR},
|
||||
{0x0006, CMN_RXCAL_ITER_TMR},
|
||||
{0x0002, CMN_SD_CAL_INIT_TMR},
|
||||
{0x0002, CMN_SD_CAL_ITER_TMR},
|
||||
{0x000E, CMN_SD_CAL_REFTIM_START},
|
||||
{0x012B, CMN_SD_CAL_PLLCNT_START},
|
||||
{0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
|
||||
{0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
|
||||
{0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
|
||||
{0x0004, CMN_PLL0_DSM_DIAG_M0},
|
||||
{0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
|
||||
{0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
|
||||
{0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
|
||||
{0x0004, CMN_PLL1_DSM_DIAG_M0},
|
||||
{0x00FA, CMN_PLL0_VCOCAL_INIT_TMR},
|
||||
{0x0004, CMN_PLL0_VCOCAL_ITER_TMR},
|
||||
{0x00FA, CMN_PLL1_VCOCAL_INIT_TMR},
|
||||
{0x0004, CMN_PLL1_VCOCAL_ITER_TMR},
|
||||
{0x0317, CMN_PLL0_VCOCAL_REFTIM_START},
|
||||
{0x0003, CMN_PLL0_VCOCAL_TCTRL},
|
||||
{0x0317, CMN_PLL1_VCOCAL_REFTIM_START},
|
||||
{0x0003, CMN_PLL1_VCOCAL_TCTRL}
|
||||
};
|
||||
|
||||
static struct cdns_reg_pairs sl_dp_25_no_ssc_tx_ln_regs[] = {
|
||||
{0x09C4, TX_RCVDET_ST_TMR},
|
||||
{0x00FB, TX_PSC_A0},
|
||||
{0x04AA, TX_PSC_A2},
|
||||
{0x04AA, TX_PSC_A3},
|
||||
{0x000F, XCVR_DIAG_BIDI_CTRL}
|
||||
};
|
||||
|
||||
static struct cdns_reg_pairs sl_dp_25_no_ssc_rx_ln_regs[] = {
|
||||
{0x0000, RX_PSC_A0},
|
||||
{0x0000, RX_PSC_A2},
|
||||
{0x0000, RX_PSC_A3},
|
||||
{0x0000, RX_PSC_CAL},
|
||||
{0x0000, RX_REE_GCSM1_CTRL},
|
||||
{0x0000, RX_REE_GCSM2_CTRL},
|
||||
{0x0000, RX_REE_PERGCSM_CTRL}
|
||||
};
|
||||
|
||||
static struct cdns_torrent_vals sl_dp_25_no_ssc_cmn_vals = {
|
||||
.reg_pairs = sl_dp_25_no_ssc_cmn_regs,
|
||||
.num_regs = ARRAY_SIZE(sl_dp_25_no_ssc_cmn_regs),
|
||||
};
|
||||
|
||||
static struct cdns_torrent_vals sl_dp_25_no_ssc_tx_ln_vals = {
|
||||
.reg_pairs = sl_dp_25_no_ssc_tx_ln_regs,
|
||||
.num_regs = ARRAY_SIZE(sl_dp_25_no_ssc_tx_ln_regs),
|
||||
};
|
||||
|
||||
static struct cdns_torrent_vals sl_dp_25_no_ssc_rx_ln_vals = {
|
||||
.reg_pairs = sl_dp_25_no_ssc_rx_ln_regs,
|
||||
.num_regs = ARRAY_SIZE(sl_dp_25_no_ssc_rx_ln_regs),
|
||||
};
|
||||
|
||||
/* USB and SGMII/QSGMII link configuration */
|
||||
static struct cdns_reg_pairs usb_sgmii_link_cmn_regs[] = {
|
||||
{0x0002, PHY_PLL_CFG},
|
||||
|
|
@ -3307,6 +3249,11 @@ static const struct cdns_torrent_data cdns_map_torrent = {
|
|||
.block_offset_shift = 0x2,
|
||||
.reg_offset_shift = 0x2,
|
||||
.link_cmn_vals = {
|
||||
[TYPE_DP] = {
|
||||
[TYPE_NONE] = {
|
||||
[NO_SSC] = &sl_dp_link_cmn_vals,
|
||||
},
|
||||
},
|
||||
[TYPE_PCIE] = {
|
||||
[TYPE_NONE] = {
|
||||
[NO_SSC] = NULL,
|
||||
|
|
@ -3383,6 +3330,11 @@ static const struct cdns_torrent_data cdns_map_torrent = {
|
|||
},
|
||||
},
|
||||
.xcvr_diag_vals = {
|
||||
[TYPE_DP] = {
|
||||
[TYPE_NONE] = {
|
||||
[NO_SSC] = &sl_dp_xcvr_diag_ln_vals,
|
||||
},
|
||||
},
|
||||
[TYPE_PCIE] = {
|
||||
[TYPE_NONE] = {
|
||||
[NO_SSC] = NULL,
|
||||
|
|
@ -3483,6 +3435,20 @@ static const struct cdns_torrent_data cdns_map_torrent = {
|
|||
},
|
||||
},
|
||||
.cmn_vals = {
|
||||
[CLK_19_2_MHZ] = {
|
||||
[TYPE_DP] = {
|
||||
[TYPE_NONE] = {
|
||||
[NO_SSC] = &sl_dp_19_2_no_ssc_cmn_vals,
|
||||
},
|
||||
},
|
||||
},
|
||||
[CLK_25_MHZ] = {
|
||||
[TYPE_DP] = {
|
||||
[TYPE_NONE] = {
|
||||
[NO_SSC] = &sl_dp_25_no_ssc_cmn_vals,
|
||||
},
|
||||
},
|
||||
},
|
||||
[CLK_100_MHZ] = {
|
||||
[TYPE_PCIE] = {
|
||||
[TYPE_NONE] = {
|
||||
|
|
@ -3561,6 +3527,20 @@ static const struct cdns_torrent_data cdns_map_torrent = {
|
|||
},
|
||||
},
|
||||
.tx_ln_vals = {
|
||||
[CLK_19_2_MHZ] = {
|
||||
[TYPE_DP] = {
|
||||
[TYPE_NONE] = {
|
||||
[NO_SSC] = &sl_dp_19_2_no_ssc_tx_ln_vals,
|
||||
},
|
||||
},
|
||||
},
|
||||
[CLK_25_MHZ] = {
|
||||
[TYPE_DP] = {
|
||||
[TYPE_NONE] = {
|
||||
[NO_SSC] = &sl_dp_25_no_ssc_tx_ln_vals,
|
||||
},
|
||||
},
|
||||
},
|
||||
[CLK_100_MHZ] = {
|
||||
[TYPE_PCIE] = {
|
||||
[TYPE_NONE] = {
|
||||
|
|
@ -3639,6 +3619,20 @@ static const struct cdns_torrent_data cdns_map_torrent = {
|
|||
},
|
||||
},
|
||||
.rx_ln_vals = {
|
||||
[CLK_19_2_MHZ] = {
|
||||
[TYPE_DP] = {
|
||||
[TYPE_NONE] = {
|
||||
[NO_SSC] = &sl_dp_19_2_no_ssc_rx_ln_vals,
|
||||
},
|
||||
},
|
||||
},
|
||||
[CLK_25_MHZ] = {
|
||||
[TYPE_DP] = {
|
||||
[TYPE_NONE] = {
|
||||
[NO_SSC] = &sl_dp_25_no_ssc_rx_ln_vals,
|
||||
},
|
||||
},
|
||||
},
|
||||
[CLK_100_MHZ] = {
|
||||
[TYPE_PCIE] = {
|
||||
[TYPE_NONE] = {
|
||||
|
|
@ -3722,6 +3716,11 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = {
|
|||
.block_offset_shift = 0x0,
|
||||
.reg_offset_shift = 0x1,
|
||||
.link_cmn_vals = {
|
||||
[TYPE_DP] = {
|
||||
[TYPE_NONE] = {
|
||||
[NO_SSC] = &sl_dp_link_cmn_vals,
|
||||
},
|
||||
},
|
||||
[TYPE_PCIE] = {
|
||||
[TYPE_NONE] = {
|
||||
[NO_SSC] = NULL,
|
||||
|
|
@ -3798,6 +3797,11 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = {
|
|||
},
|
||||
},
|
||||
.xcvr_diag_vals = {
|
||||
[TYPE_DP] = {
|
||||
[TYPE_NONE] = {
|
||||
[NO_SSC] = &sl_dp_xcvr_diag_ln_vals,
|
||||
},
|
||||
},
|
||||
[TYPE_PCIE] = {
|
||||
[TYPE_NONE] = {
|
||||
[NO_SSC] = NULL,
|
||||
|
|
@ -3898,6 +3902,20 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = {
|
|||
},
|
||||
},
|
||||
.cmn_vals = {
|
||||
[CLK_19_2_MHZ] = {
|
||||
[TYPE_DP] = {
|
||||
[TYPE_NONE] = {
|
||||
[NO_SSC] = &sl_dp_19_2_no_ssc_cmn_vals,
|
||||
},
|
||||
},
|
||||
},
|
||||
[CLK_25_MHZ] = {
|
||||
[TYPE_DP] = {
|
||||
[TYPE_NONE] = {
|
||||
[NO_SSC] = &sl_dp_25_no_ssc_cmn_vals,
|
||||
},
|
||||
},
|
||||
},
|
||||
[CLK_100_MHZ] = {
|
||||
[TYPE_PCIE] = {
|
||||
[TYPE_NONE] = {
|
||||
|
|
@ -3976,6 +3994,20 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = {
|
|||
},
|
||||
},
|
||||
.tx_ln_vals = {
|
||||
[CLK_19_2_MHZ] = {
|
||||
[TYPE_DP] = {
|
||||
[TYPE_NONE] = {
|
||||
[NO_SSC] = &sl_dp_19_2_no_ssc_tx_ln_vals,
|
||||
},
|
||||
},
|
||||
},
|
||||
[CLK_25_MHZ] = {
|
||||
[TYPE_DP] = {
|
||||
[TYPE_NONE] = {
|
||||
[NO_SSC] = &sl_dp_25_no_ssc_tx_ln_vals,
|
||||
},
|
||||
},
|
||||
},
|
||||
[CLK_100_MHZ] = {
|
||||
[TYPE_PCIE] = {
|
||||
[TYPE_NONE] = {
|
||||
|
|
@ -4054,6 +4086,20 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = {
|
|||
},
|
||||
},
|
||||
.rx_ln_vals = {
|
||||
[CLK_19_2_MHZ] = {
|
||||
[TYPE_DP] = {
|
||||
[TYPE_NONE] = {
|
||||
[NO_SSC] = &sl_dp_19_2_no_ssc_rx_ln_vals,
|
||||
},
|
||||
},
|
||||
},
|
||||
[CLK_25_MHZ] = {
|
||||
[TYPE_DP] = {
|
||||
[TYPE_NONE] = {
|
||||
[NO_SSC] = &sl_dp_25_no_ssc_rx_ln_vals,
|
||||
},
|
||||
},
|
||||
},
|
||||
[CLK_100_MHZ] = {
|
||||
[TYPE_PCIE] = {
|
||||
[TYPE_NONE] = {
|
||||
|
|
|
|||
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