qla2xxx: Avoid side effects when using endianizer macros.
Signed-off-by: Joe Carnuccio <joe.carnuccio@qlogic.com> Signed-off-by: Himanshu Madhani <himanshu.madhani@qlogic.com> Reviewed-by: Johannes Thumshirn <jthumshirn@suse.de> Reviewed-by: Hannes Reinecke <hare@suse.de> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
Родитель
243de6768d
Коммит
da08ef5c30
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@ -272,8 +272,8 @@ qla2x00_sysfs_write_nvram(struct file *filp, struct kobject *kobj,
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iter = (uint32_t *)buf;
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chksum = 0;
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for (cnt = 0; cnt < ((count >> 2) - 1); cnt++)
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chksum += le32_to_cpu(*iter++);
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for (cnt = 0; cnt < ((count >> 2) - 1); cnt++, iter++)
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chksum += le32_to_cpu(*iter);
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chksum = ~chksum + 1;
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*iter = cpu_to_le32(chksum);
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} else {
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@ -294,8 +294,8 @@ qla24xx_read_window(struct device_reg_24xx __iomem *reg, uint32_t iobase,
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WRT_REG_DWORD(®->iobase_addr, iobase);
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dmp_reg = ®->iobase_window;
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while (count--)
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*buf++ = htonl(RD_REG_DWORD(dmp_reg++));
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for ( ; count--; dmp_reg++)
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*buf++ = htonl(RD_REG_DWORD(dmp_reg));
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return buf;
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}
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@ -457,8 +457,8 @@ qla2xxx_read_window(struct device_reg_2xxx __iomem *reg, uint32_t count,
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{
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uint16_t __iomem *dmp_reg = ®->u.isp2300.fb_cmd;
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while (count--)
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*buf++ = htons(RD_REG_WORD(dmp_reg++));
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for ( ; count--; dmp_reg++)
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*buf++ = htons(RD_REG_WORD(dmp_reg));
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}
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static inline void *
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@ -733,16 +733,18 @@ qla2300_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
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if (rval == QLA_SUCCESS) {
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dmp_reg = ®->flash_address;
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for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
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fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
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for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++, dmp_reg++)
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fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg));
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dmp_reg = ®->u.isp2300.req_q_in;
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for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2; cnt++)
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fw->risc_host_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
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for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2;
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cnt++, dmp_reg++)
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fw->risc_host_reg[cnt] = htons(RD_REG_WORD(dmp_reg));
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dmp_reg = ®->u.isp2300.mailbox0;
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for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
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fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
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for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2;
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cnt++, dmp_reg++)
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fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg));
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WRT_REG_WORD(®->ctrl_status, 0x40);
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qla2xxx_read_window(reg, 32, fw->resp_dma_reg);
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@ -752,8 +754,9 @@ qla2300_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
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WRT_REG_WORD(®->ctrl_status, 0x00);
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dmp_reg = ®->risc_hw;
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for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
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fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
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for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2;
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cnt++, dmp_reg++)
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fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg));
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WRT_REG_WORD(®->pcr, 0x2000);
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qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
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@ -896,25 +899,25 @@ qla2100_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
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}
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if (rval == QLA_SUCCESS) {
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dmp_reg = ®->flash_address;
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for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
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fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
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for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++, dmp_reg++)
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fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg));
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dmp_reg = ®->u.isp2100.mailbox0;
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for (cnt = 0; cnt < ha->mbx_count; cnt++) {
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for (cnt = 0; cnt < ha->mbx_count; cnt++, dmp_reg++) {
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if (cnt == 8)
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dmp_reg = ®->u_end.isp2200.mailbox8;
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fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
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fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg));
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}
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dmp_reg = ®->u.isp2100.unused_2[0];
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for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++)
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fw->dma_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
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for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++, dmp_reg++)
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fw->dma_reg[cnt] = htons(RD_REG_WORD(dmp_reg));
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WRT_REG_WORD(®->ctrl_status, 0x00);
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dmp_reg = ®->risc_hw;
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for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
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fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
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for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++, dmp_reg++)
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fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg));
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WRT_REG_WORD(®->pcr, 0x2000);
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qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
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@ -1096,8 +1099,8 @@ qla24xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
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/* Host interface registers. */
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dmp_reg = ®->flash_addr;
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for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
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fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
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for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++, dmp_reg++)
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fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg));
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/* Disable interrupts. */
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WRT_REG_DWORD(®->ictrl, 0);
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@ -1129,8 +1132,8 @@ qla24xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
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/* Mailbox registers. */
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mbx_reg = ®->mailbox0;
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for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
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fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
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for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++, dmp_reg++)
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fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg));
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/* Transfer sequence registers. */
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iter_reg = fw->xseq_gp_reg;
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@ -1168,20 +1171,20 @@ qla24xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
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iter_reg = fw->req0_dma_reg;
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iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
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dmp_reg = ®->iobase_q;
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for (cnt = 0; cnt < 7; cnt++)
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*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
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for (cnt = 0; cnt < 7; cnt++, dmp_reg++)
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*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg));
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iter_reg = fw->resp0_dma_reg;
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iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
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dmp_reg = ®->iobase_q;
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for (cnt = 0; cnt < 7; cnt++)
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*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
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for (cnt = 0; cnt < 7; cnt++, dmp_reg++)
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*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg));
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iter_reg = fw->req1_dma_reg;
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iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
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dmp_reg = ®->iobase_q;
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for (cnt = 0; cnt < 7; cnt++)
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*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
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for (cnt = 0; cnt < 7; cnt++, dmp_reg++)
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*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg));
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/* Transmit DMA registers. */
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iter_reg = fw->xmt0_dma_reg;
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@ -1359,8 +1362,10 @@ qla25xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
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RD_REG_DWORD(®->iobase_addr);
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WRT_REG_DWORD(®->iobase_window, 0x01);
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dmp_reg = ®->iobase_c4;
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fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
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fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
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fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg));
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dmp_reg++;
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fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg));
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dmp_reg++;
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fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
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fw->pcie_regs[3] = htonl(RD_REG_DWORD(®->iobase_window));
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@ -1369,8 +1374,8 @@ qla25xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
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/* Host interface registers. */
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dmp_reg = ®->flash_addr;
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for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
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fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
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for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++, dmp_reg++)
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fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg));
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/* Disable interrupts. */
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WRT_REG_DWORD(®->ictrl, 0);
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@ -1418,8 +1423,8 @@ qla25xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
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/* Mailbox registers. */
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mbx_reg = ®->mailbox0;
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for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
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fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
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for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++, mbx_reg++)
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fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg));
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/* Transfer sequence registers. */
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iter_reg = fw->xseq_gp_reg;
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@ -1482,20 +1487,20 @@ qla25xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
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iter_reg = fw->req0_dma_reg;
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iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
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dmp_reg = ®->iobase_q;
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for (cnt = 0; cnt < 7; cnt++)
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*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
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for (cnt = 0; cnt < 7; cnt++, dmp_reg++)
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*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg));
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iter_reg = fw->resp0_dma_reg;
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iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
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dmp_reg = ®->iobase_q;
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for (cnt = 0; cnt < 7; cnt++)
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*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
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for (cnt = 0; cnt < 7; cnt++, dmp_reg++)
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*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg));
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iter_reg = fw->req1_dma_reg;
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iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
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dmp_reg = ®->iobase_q;
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for (cnt = 0; cnt < 7; cnt++)
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*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
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for (cnt = 0; cnt < 7; cnt++, dmp_reg++)
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*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg));
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/* Transmit DMA registers. */
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iter_reg = fw->xmt0_dma_reg;
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@ -1680,8 +1685,10 @@ qla81xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
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RD_REG_DWORD(®->iobase_addr);
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WRT_REG_DWORD(®->iobase_window, 0x01);
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dmp_reg = ®->iobase_c4;
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fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
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fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
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fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg));
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dmp_reg++;
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fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg));
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dmp_reg++;
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fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
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fw->pcie_regs[3] = htonl(RD_REG_DWORD(®->iobase_window));
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@ -1690,8 +1697,8 @@ qla81xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
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/* Host interface registers. */
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dmp_reg = ®->flash_addr;
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for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
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fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
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for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++, dmp_reg++)
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fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg));
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/* Disable interrupts. */
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WRT_REG_DWORD(®->ictrl, 0);
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@ -1739,8 +1746,8 @@ qla81xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
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/* Mailbox registers. */
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mbx_reg = ®->mailbox0;
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for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
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fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
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for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++, mbx_reg++)
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fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg));
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/* Transfer sequence registers. */
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iter_reg = fw->xseq_gp_reg;
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@ -1803,20 +1810,20 @@ qla81xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
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iter_reg = fw->req0_dma_reg;
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iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
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dmp_reg = ®->iobase_q;
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for (cnt = 0; cnt < 7; cnt++)
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*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
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for (cnt = 0; cnt < 7; cnt++, dmp_reg++)
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*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg));
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iter_reg = fw->resp0_dma_reg;
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iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
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dmp_reg = ®->iobase_q;
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for (cnt = 0; cnt < 7; cnt++)
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*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
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for (cnt = 0; cnt < 7; cnt++, dmp_reg++)
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*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg));
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iter_reg = fw->req1_dma_reg;
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iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
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dmp_reg = ®->iobase_q;
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for (cnt = 0; cnt < 7; cnt++)
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*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
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for (cnt = 0; cnt < 7; cnt++, dmp_reg++)
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*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg));
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/* Transmit DMA registers. */
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iter_reg = fw->xmt0_dma_reg;
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@ -2023,8 +2030,10 @@ qla83xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
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RD_REG_DWORD(®->iobase_addr);
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WRT_REG_DWORD(®->iobase_window, 0x01);
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dmp_reg = ®->iobase_c4;
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fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
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fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
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fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg));
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dmp_reg++;
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fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg));
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dmp_reg++;
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fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
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fw->pcie_regs[3] = htonl(RD_REG_DWORD(®->iobase_window));
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@ -2033,8 +2042,8 @@ qla83xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
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/* Host interface registers. */
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dmp_reg = ®->flash_addr;
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for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
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fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
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for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++, dmp_reg++)
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fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg));
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/* Disable interrupts. */
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WRT_REG_DWORD(®->ictrl, 0);
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@ -2082,8 +2091,8 @@ qla83xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
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/* Mailbox registers. */
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mbx_reg = ®->mailbox0;
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for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
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fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
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for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++, dmp_reg++)
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fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg));
|
||||
|
||||
/* Transfer sequence registers. */
|
||||
iter_reg = fw->xseq_gp_reg;
|
||||
|
@ -2178,20 +2187,20 @@ qla83xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
|
|||
iter_reg = fw->req0_dma_reg;
|
||||
iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
|
||||
dmp_reg = ®->iobase_q;
|
||||
for (cnt = 0; cnt < 7; cnt++)
|
||||
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
||||
for (cnt = 0; cnt < 7; cnt++, dmp_reg++)
|
||||
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg));
|
||||
|
||||
iter_reg = fw->resp0_dma_reg;
|
||||
iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
|
||||
dmp_reg = ®->iobase_q;
|
||||
for (cnt = 0; cnt < 7; cnt++)
|
||||
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
||||
for (cnt = 0; cnt < 7; cnt++, dmp_reg++)
|
||||
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg));
|
||||
|
||||
iter_reg = fw->req1_dma_reg;
|
||||
iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
|
||||
dmp_reg = ®->iobase_q;
|
||||
for (cnt = 0; cnt < 7; cnt++)
|
||||
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
|
||||
for (cnt = 0; cnt < 7; cnt++, dmp_reg++)
|
||||
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg));
|
||||
|
||||
/* Transmit DMA registers. */
|
||||
iter_reg = fw->xmt0_dma_reg;
|
||||
|
|
|
@ -5125,8 +5125,8 @@ qla24xx_nvram_config(scsi_qla_host_t *vha)
|
|||
dptr = (uint32_t *)nv;
|
||||
ha->isp_ops->read_nvram(vha, (uint8_t *)dptr, ha->nvram_base,
|
||||
ha->nvram_size);
|
||||
for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++)
|
||||
chksum += le32_to_cpu(*dptr++);
|
||||
for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++, dptr++)
|
||||
chksum += le32_to_cpu(*dptr);
|
||||
|
||||
ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x006a,
|
||||
"Contents of NVRAM\n");
|
||||
|
@ -5379,8 +5379,8 @@ uint8_t qla27xx_find_valid_image(struct scsi_qla_host *vha)
|
|||
wptr = (uint32_t *)(&pri_image_status);
|
||||
cnt = size;
|
||||
|
||||
for (chksum = 0; cnt; cnt--)
|
||||
chksum += le32_to_cpu(*wptr++);
|
||||
for (chksum = 0; cnt--; wptr++)
|
||||
chksum += le32_to_cpu(*wptr);
|
||||
if (chksum) {
|
||||
ql_dbg(ql_dbg_init, vha, 0x018c,
|
||||
"Checksum validation failed for primary image (0x%x)\n",
|
||||
|
@ -5407,8 +5407,8 @@ check_sec_image:
|
|||
|
||||
wptr = (uint32_t *)(&sec_image_status);
|
||||
cnt = size;
|
||||
for (chksum = 0; cnt; cnt--)
|
||||
chksum += le32_to_cpu(*wptr++);
|
||||
for (chksum = 0; cnt--; wptr++)
|
||||
chksum += le32_to_cpu(*wptr);
|
||||
if (chksum) {
|
||||
ql_dbg(ql_dbg_init, vha, 0x018e,
|
||||
"Checksum validation failed for secondary image (0x%x)\n",
|
||||
|
@ -6161,8 +6161,8 @@ qla81xx_nvram_config(scsi_qla_host_t *vha)
|
|||
ha->isp_ops->read_optrom(vha, ha->nvram, ha->flt_region_nvram << 2,
|
||||
ha->nvram_size);
|
||||
dptr = (uint32_t *)nv;
|
||||
for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++)
|
||||
chksum += le32_to_cpu(*dptr++);
|
||||
for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++, dptr++)
|
||||
chksum += le32_to_cpu(*dptr);
|
||||
|
||||
ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0111,
|
||||
"Contents of NVRAM:\n");
|
||||
|
|
|
@ -87,8 +87,8 @@ host_to_adap(uint8_t *src, uint8_t *dst, uint32_t bsize)
|
|||
__le32 *odest = (__le32 *) dst;
|
||||
uint32_t iter = bsize >> 2;
|
||||
|
||||
for (; iter ; iter--)
|
||||
*odest++ = cpu_to_le32(*isrc++);
|
||||
for ( ; iter--; isrc++)
|
||||
*odest++ = cpu_to_le32(*isrc);
|
||||
}
|
||||
|
||||
static inline void
|
||||
|
|
|
@ -2759,7 +2759,7 @@ qla2x00_get_link_status(scsi_qla_host_t *vha, uint16_t loop_id,
|
|||
int rval;
|
||||
mbx_cmd_t mc;
|
||||
mbx_cmd_t *mcp = &mc;
|
||||
uint32_t *siter, *diter, dwords;
|
||||
uint32_t *iter, dwords;
|
||||
struct qla_hw_data *ha = vha->hw;
|
||||
|
||||
ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1084,
|
||||
|
@ -2801,9 +2801,9 @@ qla2x00_get_link_status(scsi_qla_host_t *vha, uint16_t loop_id,
|
|||
"Done %s.\n", __func__);
|
||||
dwords = offsetof(struct link_statistics,
|
||||
link_up_cnt) / 4;
|
||||
siter = diter = &stats->link_fail_cnt;
|
||||
while (dwords--)
|
||||
*diter++ = le32_to_cpu(*siter++);
|
||||
iter = &stats->link_fail_cnt;
|
||||
for ( ; dwords--; iter++)
|
||||
le32_to_cpus(iter);
|
||||
}
|
||||
} else {
|
||||
/* Failed. */
|
||||
|
@ -2820,7 +2820,7 @@ qla24xx_get_isp_stats(scsi_qla_host_t *vha, struct link_statistics *stats,
|
|||
int rval;
|
||||
mbx_cmd_t mc;
|
||||
mbx_cmd_t *mcp = &mc;
|
||||
uint32_t *siter, *diter, dwords;
|
||||
uint32_t *iter, dwords;
|
||||
|
||||
ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1088,
|
||||
"Entered %s.\n", __func__);
|
||||
|
@ -2849,9 +2849,9 @@ qla24xx_get_isp_stats(scsi_qla_host_t *vha, struct link_statistics *stats,
|
|||
"Done %s.\n", __func__);
|
||||
/* Copy over data -- firmware data is LE. */
|
||||
dwords = sizeof(struct link_statistics) / 4;
|
||||
siter = diter = &stats->link_fail_cnt;
|
||||
while (dwords--)
|
||||
*diter++ = le32_to_cpu(*siter++);
|
||||
iter = &stats->link_fail_cnt;
|
||||
for ( ; dwords--; iter++)
|
||||
le32_to_cpus(iter);
|
||||
}
|
||||
} else {
|
||||
/* Failed. */
|
||||
|
|
|
@ -610,8 +610,8 @@ qla2xxx_find_flt_start(scsi_qla_host_t *vha, uint32_t *start)
|
|||
|
||||
wptr = (uint16_t *)req->ring;
|
||||
cnt = sizeof(struct qla_flt_location) >> 1;
|
||||
for (chksum = 0; cnt; cnt--)
|
||||
chksum += le16_to_cpu(*wptr++);
|
||||
for (chksum = 0; cnt--; wptr++)
|
||||
chksum += le16_to_cpu(*wptr);
|
||||
if (chksum) {
|
||||
ql_log(ql_log_fatal, vha, 0x0045,
|
||||
"Inconsistent FLTL detected: checksum=0x%x.\n", chksum);
|
||||
|
@ -702,8 +702,8 @@ qla2xxx_get_flt_info(scsi_qla_host_t *vha, uint32_t flt_addr)
|
|||
}
|
||||
|
||||
cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1;
|
||||
for (chksum = 0; cnt; cnt--)
|
||||
chksum += le16_to_cpu(*wptr++);
|
||||
for (chksum = 0; cnt--; wptr++)
|
||||
chksum += le16_to_cpu(*wptr);
|
||||
if (chksum) {
|
||||
ql_log(ql_log_fatal, vha, 0x0048,
|
||||
"Inconsistent FLT detected: version=0x%x length=0x%x checksum=0x%x.\n",
|
||||
|
@ -930,9 +930,8 @@ qla2xxx_get_fdt_info(scsi_qla_host_t *vha)
|
|||
fdt->sig[3] != 'D')
|
||||
goto no_flash_data;
|
||||
|
||||
for (cnt = 0, chksum = 0; cnt < sizeof(struct qla_fdt_layout) >> 1;
|
||||
cnt++)
|
||||
chksum += le16_to_cpu(*wptr++);
|
||||
for (cnt = 0, chksum = 0; cnt < sizeof(*fdt) >> 1; cnt++, wptr++)
|
||||
chksum += le16_to_cpu(*wptr);
|
||||
if (chksum) {
|
||||
ql_dbg(ql_dbg_init, vha, 0x004c,
|
||||
"Inconsistent FDT detected:"
|
||||
|
@ -1027,7 +1026,8 @@ qla2xxx_get_idc_param(scsi_qla_host_t *vha)
|
|||
ha->fcoe_dev_init_timeout = QLA82XX_ROM_DEV_INIT_TIMEOUT;
|
||||
ha->fcoe_reset_timeout = QLA82XX_ROM_DRV_RESET_ACK_TIMEOUT;
|
||||
} else {
|
||||
ha->fcoe_dev_init_timeout = le32_to_cpu(*wptr++);
|
||||
ha->fcoe_dev_init_timeout = le32_to_cpu(*wptr);
|
||||
wptr++;
|
||||
ha->fcoe_reset_timeout = le32_to_cpu(*wptr);
|
||||
}
|
||||
ql_dbg(ql_dbg_init, vha, 0x004e,
|
||||
|
@ -1104,10 +1104,9 @@ qla2xxx_flash_npiv_conf(scsi_qla_host_t *vha)
|
|||
ha->isp_ops->read_optrom(vha, (uint8_t *)data,
|
||||
ha->flt_region_npiv_conf << 2, NPIV_CONFIG_SIZE);
|
||||
|
||||
cnt = (sizeof(struct qla_npiv_header) + le16_to_cpu(hdr.entries) *
|
||||
sizeof(struct qla_npiv_entry)) >> 1;
|
||||
for (wptr = data, chksum = 0; cnt; cnt--)
|
||||
chksum += le16_to_cpu(*wptr++);
|
||||
cnt = (sizeof(hdr) + le16_to_cpu(hdr.entries) * sizeof(*entry)) >> 1;
|
||||
for (wptr = data, chksum = 0; cnt--; wptr++)
|
||||
chksum += le16_to_cpu(*wptr);
|
||||
if (chksum) {
|
||||
ql_dbg(ql_dbg_user, vha, 0x7092,
|
||||
"Inconsistent NPIV-Config "
|
||||
|
|
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