ARM: Add the clock framework for Telechips TCC8xxx processors.
This adds definitions and low-level functions to handle clocks in TCC8xxx processors. Signed-off-by: "Hans J. Koch" <hjk@linutronix.de> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This commit is contained in:
Hans J. Koch
Thomas Gleixner
Родитель
83ef3338a2
Коммит
da15797eae
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@ -0,0 +1,6 @@
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#
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# Makefile for TCC8K boards and common files.
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#
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# Common support
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obj-y += clock.o
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@ -0,0 +1,566 @@
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/*
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* Lowlevel clock handling for Telechips TCC8xxx SoCs
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*
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* Copyright (C) 2010 by Hans J. Koch <hjk@linutronix.de>
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*
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* Licensed under the terms of the GPL v2
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/spinlock.h>
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#include <asm/clkdev.h>
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#include <mach/clock.h>
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#include <mach/irqs.h>
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#include <mach/tcc8k-regs.h>
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#include "common.h"
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#define BCLKCTR0 (CKC_BASE + BCLKCTR0_OFFS)
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#define BCLKCTR1 (CKC_BASE + BCLKCTR1_OFFS)
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#define ACLKREF (CKC_BASE + ACLKREF_OFFS)
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#define ACLKUART0 (CKC_BASE + ACLKUART0_OFFS)
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#define ACLKUART1 (CKC_BASE + ACLKUART1_OFFS)
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#define ACLKUART2 (CKC_BASE + ACLKUART2_OFFS)
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#define ACLKUART3 (CKC_BASE + ACLKUART3_OFFS)
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#define ACLKUART4 (CKC_BASE + ACLKUART4_OFFS)
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#define ACLKI2C (CKC_BASE + ACLKI2C_OFFS)
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#define ACLKADC (CKC_BASE + ACLKADC_OFFS)
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#define ACLKUSBH (CKC_BASE + ACLKUSBH_OFFS)
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#define ACLKLCD (CKC_BASE + ACLKLCD_OFFS)
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#define ACLKSDH0 (CKC_BASE + ACLKSDH0_OFFS)
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#define ACLKSDH1 (CKC_BASE + ACLKSDH1_OFFS)
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#define ACLKSPI0 (CKC_BASE + ACLKSPI0_OFFS)
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#define ACLKSPI1 (CKC_BASE + ACLKSPI1_OFFS)
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#define ACLKSPDIF (CKC_BASE + ACLKSPDIF_OFFS)
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#define ACLKC3DEC (CKC_BASE + ACLKC3DEC_OFFS)
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#define ACLKCAN0 (CKC_BASE + ACLKCAN0_OFFS)
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#define ACLKCAN1 (CKC_BASE + ACLKCAN1_OFFS)
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#define ACLKGSB0 (CKC_BASE + ACLKGSB0_OFFS)
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#define ACLKGSB1 (CKC_BASE + ACLKGSB1_OFFS)
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#define ACLKGSB2 (CKC_BASE + ACLKGSB2_OFFS)
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#define ACLKGSB3 (CKC_BASE + ACLKGSB3_OFFS)
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#define ACLKUSBH (CKC_BASE + ACLKUSBH_OFFS)
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#define ACLKTCT (CKC_BASE + ACLKTCT_OFFS)
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#define ACLKTCX (CKC_BASE + ACLKTCX_OFFS)
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#define ACLKTCZ (CKC_BASE + ACLKTCZ_OFFS)
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/* Crystal frequencies */
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static unsigned long xi_rate, xti_rate;
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static void __iomem *pll_cfg_addr(int pll)
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{
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switch (pll) {
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case 0: return (CKC_BASE + PLL0CFG_OFFS);
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case 1: return (CKC_BASE + PLL1CFG_OFFS);
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case 2: return (CKC_BASE + PLL2CFG_OFFS);
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default:
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BUG();
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}
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}
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static int pll_enable(int pll, int enable)
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{
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u32 reg;
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void __iomem *addr = pll_cfg_addr(pll);
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reg = __raw_readl(addr);
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if (enable)
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reg &= ~PLLxCFG_PD;
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else
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reg |= PLLxCFG_PD;
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__raw_writel(reg, addr);
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return 0;
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}
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static int xi_enable(int enable)
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{
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u32 reg;
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reg = __raw_readl(CKC_BASE + CLKCTRL_OFFS);
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if (enable)
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reg |= CLKCTRL_XE;
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else
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reg &= ~CLKCTRL_XE;
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__raw_writel(reg, CKC_BASE + CLKCTRL_OFFS);
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return 0;
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}
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static int root_clk_enable(enum root_clks src)
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{
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switch (src) {
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case CLK_SRC_PLL0: return pll_enable(0, 1);
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case CLK_SRC_PLL1: return pll_enable(1, 1);
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case CLK_SRC_PLL2: return pll_enable(2, 1);
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case CLK_SRC_XI: return xi_enable(1);
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default:
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BUG();
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}
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return 0;
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}
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static int root_clk_disable(enum root_clks root_src)
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{
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switch (root_src) {
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case CLK_SRC_PLL0: return pll_enable(0, 0);
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case CLK_SRC_PLL1: return pll_enable(1, 0);
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case CLK_SRC_PLL2: return pll_enable(2, 0);
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case CLK_SRC_XI: return xi_enable(0);
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default:
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BUG();
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}
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return 0;
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}
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static int enable_clk(struct clk *clk)
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{
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u32 reg;
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if (clk->root_id != CLK_SRC_NOROOT)
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return root_clk_enable(clk->root_id);
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if (clk->aclkreg) {
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reg = __raw_readl(clk->aclkreg);
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reg |= ACLK_EN;
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__raw_writel(reg, clk->aclkreg);
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}
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if (clk->bclkctr) {
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reg = __raw_readl(clk->bclkctr);
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reg |= 1 << clk->bclk_shift;
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__raw_writel(reg, clk->bclkctr);
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}
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return 0;
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}
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static void disable_clk(struct clk *clk)
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{
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u32 reg;
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if (clk->root_id != CLK_SRC_NOROOT) {
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root_clk_disable(clk->root_id);
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return;
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}
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if (clk->bclkctr) {
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reg = __raw_readl(clk->bclkctr);
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reg &= ~(1 << clk->bclk_shift);
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__raw_writel(reg, clk->bclkctr);
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}
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if (clk->aclkreg) {
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reg = __raw_readl(clk->aclkreg);
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reg &= ~ACLK_EN;
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__raw_writel(reg, clk->aclkreg);
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}
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}
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static unsigned long get_rate_pll(int pll)
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{
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u32 reg;
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unsigned long s, m, p;
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void __iomem *addr = pll_cfg_addr(pll);
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reg = __raw_readl(addr);
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s = (reg >> 16) & 0x07;
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m = (reg >> 8) & 0xff;
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p = reg & 0x3f;
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return (m * xi_rate) / (p * (1 << s));
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}
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static unsigned long get_rate_pll_div(int pll)
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{
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u32 reg;
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unsigned long div = 0;
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void __iomem *addr;
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switch (pll) {
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case 0:
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addr = CKC_BASE + CLKDIVC0_OFFS;
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reg = __raw_readl(addr);
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if (reg & CLKDIVC0_P0E)
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div = (reg >> 24) & 0x3f;
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break;
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case 1:
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addr = CKC_BASE + CLKDIVC0_OFFS;
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reg = __raw_readl(addr);
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if (reg & CLKDIVC0_P1E)
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div = (reg >> 16) & 0x3f;
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break;
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case 2:
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addr = CKC_BASE + CLKDIVC1_OFFS;
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reg = __raw_readl(addr);
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if (reg & CLKDIVC1_P2E)
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div = __raw_readl(addr) & 0x3f;
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break;
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}
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return get_rate_pll(pll) / (div + 1);
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}
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static unsigned long get_rate_xi_div(void)
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{
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unsigned long div = 0;
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u32 reg = __raw_readl(CKC_BASE + CLKDIVC0_OFFS);
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if (reg & CLKDIVC0_XE)
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div = (reg >> 8) & 0x3f;
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return xi_rate / (div + 1);
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}
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static unsigned long get_rate_xti_div(void)
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{
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unsigned long div = 0;
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u32 reg = __raw_readl(CKC_BASE + CLKDIVC0_OFFS);
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if (reg & CLKDIVC0_XTE)
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div = reg & 0x3f;
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return xti_rate / (div + 1);
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}
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static unsigned long root_clk_get_rate(enum root_clks src)
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{
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switch (src) {
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case CLK_SRC_PLL0: return get_rate_pll(0);
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case CLK_SRC_PLL1: return get_rate_pll(1);
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case CLK_SRC_PLL2: return get_rate_pll(2);
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case CLK_SRC_PLL0DIV: return get_rate_pll_div(0);
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case CLK_SRC_PLL1DIV: return get_rate_pll_div(1);
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case CLK_SRC_PLL2DIV: return get_rate_pll_div(2);
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case CLK_SRC_XI: return xi_rate;
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case CLK_SRC_XTI: return xti_rate;
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case CLK_SRC_XIDIV: return get_rate_xi_div();
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case CLK_SRC_XTIDIV: return get_rate_xti_div();
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default: return 0;
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}
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}
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static unsigned long aclk_get_rate(struct clk *clk)
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{
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u32 reg;
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unsigned long div;
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unsigned int src;
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reg = __raw_readl(clk->aclkreg);
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div = reg & 0x0fff;
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src = (reg >> ACLK_SEL_SHIFT) & CLK_SRC_MASK;
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return root_clk_get_rate(src) / (div + 1);
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}
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static unsigned long aclk_best_div(struct clk *clk, unsigned long rate)
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{
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unsigned long div, src, freq, r1, r2;
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src = __raw_readl(clk->aclkreg) >> ACLK_SEL_SHIFT;
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src &= CLK_SRC_MASK;
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freq = root_clk_get_rate(src);
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div = freq / rate + 1;
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r1 = freq / div;
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r2 = freq / (div + 1);
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if (r2 >= rate)
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return div + 1;
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if ((rate - r2) < (r1 - rate))
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return div + 1;
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return div;
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}
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static unsigned long aclk_round_rate(struct clk *clk, unsigned long rate)
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{
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unsigned int src;
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src = __raw_readl(clk->aclkreg) >> ACLK_SEL_SHIFT;
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src &= CLK_SRC_MASK;
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return root_clk_get_rate(src) / aclk_best_div(clk, rate);
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}
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static int aclk_set_rate(struct clk *clk, unsigned long rate)
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{
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u32 reg;
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reg = __raw_readl(clk->aclkreg) & ~ACLK_DIV_MASK;
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reg |= aclk_best_div(clk, rate);
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return 0;
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}
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static unsigned long get_rate_sys(struct clk *clk)
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{
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unsigned int src;
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src = __raw_readl(CKC_BASE + CLKCTRL_OFFS) & CLK_SRC_MASK;
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return root_clk_get_rate(src);
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}
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static unsigned long get_rate_bus(struct clk *clk)
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{
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unsigned int div;
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div = (__raw_readl(CKC_BASE + CLKCTRL_OFFS) >> 4) & 0xff;
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return get_rate_sys(clk) / (div + 1);
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}
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static unsigned long get_rate_cpu(struct clk *clk)
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{
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unsigned int reg, div, fsys, fbus;
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fbus = get_rate_bus(clk);
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reg = __raw_readl(CKC_BASE + CLKCTRL_OFFS);
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if (reg & (1 << 29))
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return fbus;
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fsys = get_rate_sys(clk);
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div = (reg >> 16) & 0x0f;
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return fbus + ((fsys - fbus) * (div + 1)) / 16;
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}
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static unsigned long get_rate_root(struct clk *clk)
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{
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return root_clk_get_rate(clk->root_id);
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}
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static int aclk_set_parent(struct clk *clock, struct clk *parent)
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{
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u32 reg;
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if (clock->parent == parent)
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return 0;
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clock->parent = parent;
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if (!parent)
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return 0;
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if (parent->root_id == CLK_SRC_NOROOT)
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return 0;
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reg = __raw_readl(clock->aclkreg);
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reg &= ~ACLK_SEL_MASK;
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reg |= (parent->root_id << ACLK_SEL_SHIFT) & ACLK_SEL_MASK;
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__raw_writel(reg, clock->aclkreg);
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return 0;
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}
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#define DEFINE_ROOT_CLOCK(name, ri, p) \
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static struct clk name = { \
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.root_id = ri, \
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.get_rate = get_rate_root, \
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.enable = enable_clk, \
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.disable = disable_clk, \
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.parent = p, \
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};
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#define DEFINE_SPECIAL_CLOCK(name, gr, p) \
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static struct clk name = { \
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.root_id = CLK_SRC_NOROOT, \
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.get_rate = gr, \
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.parent = p, \
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};
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#define DEFINE_ACLOCK(name, bc, bs, ar) \
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static struct clk name = { \
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.root_id = CLK_SRC_NOROOT, \
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.bclkctr = bc, \
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.bclk_shift = bs, \
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.aclkreg = ar, \
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.get_rate = aclk_get_rate, \
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.set_rate = aclk_set_rate, \
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.round_rate = aclk_round_rate, \
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.enable = enable_clk, \
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.disable = disable_clk, \
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.set_parent = aclk_set_parent, \
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};
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#define DEFINE_BCLOCK(name, bc, bs, gr, p) \
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static struct clk name = { \
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.root_id = CLK_SRC_NOROOT, \
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.bclkctr = bc, \
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.bclk_shift = bs, \
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.get_rate = gr, \
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.enable = enable_clk, \
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.disable = disable_clk, \
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.parent = p, \
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};
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DEFINE_ROOT_CLOCK(xi, CLK_SRC_XI, NULL)
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DEFINE_ROOT_CLOCK(xti, CLK_SRC_XTI, NULL)
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DEFINE_ROOT_CLOCK(xidiv, CLK_SRC_XIDIV, &xi)
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DEFINE_ROOT_CLOCK(xtidiv, CLK_SRC_XTIDIV, &xti)
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DEFINE_ROOT_CLOCK(pll0, CLK_SRC_PLL0, &xi)
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DEFINE_ROOT_CLOCK(pll1, CLK_SRC_PLL1, &xi)
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DEFINE_ROOT_CLOCK(pll2, CLK_SRC_PLL2, &xi)
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DEFINE_ROOT_CLOCK(pll0div, CLK_SRC_PLL0DIV, &pll0)
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DEFINE_ROOT_CLOCK(pll1div, CLK_SRC_PLL1DIV, &pll1)
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DEFINE_ROOT_CLOCK(pll2div, CLK_SRC_PLL2DIV, &pll2)
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/* The following 3 clocks are special and are initialized explicitly later */
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DEFINE_SPECIAL_CLOCK(sys, get_rate_sys, NULL)
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DEFINE_SPECIAL_CLOCK(bus, get_rate_bus, &sys)
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DEFINE_SPECIAL_CLOCK(cpu, get_rate_cpu, &sys)
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DEFINE_ACLOCK(tct, NULL, 0, ACLKTCT)
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DEFINE_ACLOCK(tcx, NULL, 0, ACLKTCX)
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DEFINE_ACLOCK(tcz, NULL, 0, ACLKTCZ)
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DEFINE_ACLOCK(ref, NULL, 0, ACLKREF)
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DEFINE_ACLOCK(uart0, BCLKCTR0, 5, ACLKUART0)
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DEFINE_ACLOCK(uart1, BCLKCTR0, 23, ACLKUART1)
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DEFINE_ACLOCK(uart2, BCLKCTR0, 6, ACLKUART2)
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DEFINE_ACLOCK(uart3, BCLKCTR0, 8, ACLKUART3)
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DEFINE_ACLOCK(uart4, BCLKCTR1, 6, ACLKUART4)
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DEFINE_ACLOCK(i2c, BCLKCTR0, 7, ACLKI2C)
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DEFINE_ACLOCK(adc, BCLKCTR0, 10, ACLKADC)
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DEFINE_ACLOCK(usbh0, BCLKCTR0, 11, ACLKUSBH)
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DEFINE_ACLOCK(lcd, BCLKCTR0, 13, ACLKLCD)
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DEFINE_ACLOCK(sd0, BCLKCTR0, 17, ACLKSDH0)
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DEFINE_ACLOCK(sd1, BCLKCTR1, 5, ACLKSDH1)
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DEFINE_ACLOCK(spi0, BCLKCTR0, 24, ACLKSPI0)
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DEFINE_ACLOCK(spi1, BCLKCTR0, 30, ACLKSPI1)
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DEFINE_ACLOCK(spdif, BCLKCTR1, 2, ACLKSPDIF)
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DEFINE_ACLOCK(c3dec, BCLKCTR1, 9, ACLKC3DEC)
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DEFINE_ACLOCK(can0, BCLKCTR1, 10, ACLKCAN0)
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DEFINE_ACLOCK(can1, BCLKCTR1, 11, ACLKCAN1)
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DEFINE_ACLOCK(gsb0, BCLKCTR1, 13, ACLKGSB0)
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DEFINE_ACLOCK(gsb1, BCLKCTR1, 14, ACLKGSB1)
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DEFINE_ACLOCK(gsb2, BCLKCTR1, 15, ACLKGSB2)
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DEFINE_ACLOCK(gsb3, BCLKCTR1, 16, ACLKGSB3)
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DEFINE_ACLOCK(usbh1, BCLKCTR1, 20, ACLKUSBH)
|
||||
|
||||
DEFINE_BCLOCK(dai0, BCLKCTR0, 0, NULL, NULL)
|
||||
DEFINE_BCLOCK(pic, BCLKCTR0, 1, NULL, NULL)
|
||||
DEFINE_BCLOCK(tc, BCLKCTR0, 2, NULL, NULL)
|
||||
DEFINE_BCLOCK(gpio, BCLKCTR0, 3, NULL, NULL)
|
||||
DEFINE_BCLOCK(usbd, BCLKCTR0, 4, NULL, NULL)
|
||||
DEFINE_BCLOCK(ecc, BCLKCTR0, 9, NULL, NULL)
|
||||
DEFINE_BCLOCK(gdma0, BCLKCTR0, 12, NULL, NULL)
|
||||
DEFINE_BCLOCK(rtc, BCLKCTR0, 15, NULL, NULL)
|
||||
DEFINE_BCLOCK(nfc, BCLKCTR0, 16, NULL, NULL)
|
||||
DEFINE_BCLOCK(g2d, BCLKCTR0, 18, NULL, NULL)
|
||||
DEFINE_BCLOCK(gdma1, BCLKCTR0, 22, NULL, NULL)
|
||||
DEFINE_BCLOCK(mscl, BCLKCTR0, 25, NULL, NULL)
|
||||
DEFINE_BCLOCK(bdma, BCLKCTR1, 0, NULL, NULL)
|
||||
DEFINE_BCLOCK(adma0, BCLKCTR1, 1, NULL, NULL)
|
||||
DEFINE_BCLOCK(scfg, BCLKCTR1, 3, NULL, NULL)
|
||||
DEFINE_BCLOCK(cid, BCLKCTR1, 4, NULL, NULL)
|
||||
DEFINE_BCLOCK(dai1, BCLKCTR1, 7, NULL, NULL)
|
||||
DEFINE_BCLOCK(adma1, BCLKCTR1, 8, NULL, NULL)
|
||||
DEFINE_BCLOCK(gps, BCLKCTR1, 12, NULL, NULL)
|
||||
DEFINE_BCLOCK(gdma2, BCLKCTR1, 17, NULL, NULL)
|
||||
DEFINE_BCLOCK(gdma3, BCLKCTR1, 18, NULL, NULL)
|
||||
DEFINE_BCLOCK(ddrc, BCLKCTR1, 19, NULL, NULL)
|
||||
|
||||
#define _REGISTER_CLOCK(d, n, c) \
|
||||
{ \
|
||||
.dev_id = d, \
|
||||
.con_id = n, \
|
||||
.clk = &c, \
|
||||
},
|
||||
|
||||
static struct clk_lookup lookups[] = {
|
||||
_REGISTER_CLOCK(NULL, "bus", bus)
|
||||
_REGISTER_CLOCK(NULL, "cpu", cpu)
|
||||
_REGISTER_CLOCK(NULL, "tct", tct)
|
||||
_REGISTER_CLOCK(NULL, "tcx", tcx)
|
||||
_REGISTER_CLOCK(NULL, "tcz", tcz)
|
||||
_REGISTER_CLOCK(NULL, "ref", ref)
|
||||
_REGISTER_CLOCK(NULL, "dai0", dai0)
|
||||
_REGISTER_CLOCK(NULL, "pic", pic)
|
||||
_REGISTER_CLOCK(NULL, "tc", tc)
|
||||
_REGISTER_CLOCK(NULL, "gpio", gpio)
|
||||
_REGISTER_CLOCK(NULL, "usbd", usbd)
|
||||
_REGISTER_CLOCK("tcc-uart.0", NULL, uart0)
|
||||
_REGISTER_CLOCK("tcc-uart.2", NULL, uart2)
|
||||
_REGISTER_CLOCK("tcc-i2c", NULL, i2c)
|
||||
_REGISTER_CLOCK("tcc-uart.3", NULL, uart3)
|
||||
_REGISTER_CLOCK(NULL, "ecc", ecc)
|
||||
_REGISTER_CLOCK(NULL, "adc", adc)
|
||||
_REGISTER_CLOCK("tcc-usbh.0", "usb", usbh0)
|
||||
_REGISTER_CLOCK(NULL, "gdma0", gdma0)
|
||||
_REGISTER_CLOCK(NULL, "lcd", lcd)
|
||||
_REGISTER_CLOCK(NULL, "rtc", rtc)
|
||||
_REGISTER_CLOCK(NULL, "nfc", nfc)
|
||||
_REGISTER_CLOCK("tcc-mmc.0", NULL, sd0)
|
||||
_REGISTER_CLOCK(NULL, "g2d", g2d)
|
||||
_REGISTER_CLOCK(NULL, "gdma1", gdma1)
|
||||
_REGISTER_CLOCK("tcc-uart.1", NULL, uart1)
|
||||
_REGISTER_CLOCK("tcc-spi.0", NULL, spi0)
|
||||
_REGISTER_CLOCK(NULL, "mscl", mscl)
|
||||
_REGISTER_CLOCK("tcc-spi.1", NULL, spi1)
|
||||
_REGISTER_CLOCK(NULL, "bdma", bdma)
|
||||
_REGISTER_CLOCK(NULL, "adma0", adma0)
|
||||
_REGISTER_CLOCK(NULL, "spdif", spdif)
|
||||
_REGISTER_CLOCK(NULL, "scfg", scfg)
|
||||
_REGISTER_CLOCK(NULL, "cid", cid)
|
||||
_REGISTER_CLOCK("tcc-mmc.1", NULL, sd1)
|
||||
_REGISTER_CLOCK("tcc-uart.4", NULL, uart4)
|
||||
_REGISTER_CLOCK(NULL, "dai1", dai1)
|
||||
_REGISTER_CLOCK(NULL, "adma1", adma1)
|
||||
_REGISTER_CLOCK(NULL, "c3dec", c3dec)
|
||||
_REGISTER_CLOCK("tcc-can.0", NULL, can0)
|
||||
_REGISTER_CLOCK("tcc-can.1", NULL, can1)
|
||||
_REGISTER_CLOCK(NULL, "gps", gps)
|
||||
_REGISTER_CLOCK("tcc-gsb.0", NULL, gsb0)
|
||||
_REGISTER_CLOCK("tcc-gsb.1", NULL, gsb1)
|
||||
_REGISTER_CLOCK("tcc-gsb.2", NULL, gsb2)
|
||||
_REGISTER_CLOCK("tcc-gsb.3", NULL, gsb3)
|
||||
_REGISTER_CLOCK(NULL, "gdma2", gdma2)
|
||||
_REGISTER_CLOCK(NULL, "gdma3", gdma3)
|
||||
_REGISTER_CLOCK(NULL, "ddrc", ddrc)
|
||||
_REGISTER_CLOCK("tcc-usbh.1", "usb", usbh1)
|
||||
};
|
||||
|
||||
static struct clk *root_clk_by_index(enum root_clks src)
|
||||
{
|
||||
switch (src) {
|
||||
case CLK_SRC_PLL0: return &pll0;
|
||||
case CLK_SRC_PLL1: return &pll1;
|
||||
case CLK_SRC_PLL2: return &pll2;
|
||||
case CLK_SRC_PLL0DIV: return &pll0div;
|
||||
case CLK_SRC_PLL1DIV: return &pll1div;
|
||||
case CLK_SRC_PLL2DIV: return &pll2div;
|
||||
case CLK_SRC_XI: return ξ
|
||||
case CLK_SRC_XTI: return &xti;
|
||||
case CLK_SRC_XIDIV: return &xidiv;
|
||||
case CLK_SRC_XTIDIV: return &xtidiv;
|
||||
default: return NULL;
|
||||
}
|
||||
}
|
||||
|
||||
static void find_aclk_parent(struct clk *clk)
|
||||
{
|
||||
unsigned int src;
|
||||
struct clk *clock;
|
||||
|
||||
if (!clk->aclkreg)
|
||||
return;
|
||||
|
||||
src = __raw_readl(clk->aclkreg) >> ACLK_SEL_SHIFT;
|
||||
src &= CLK_SRC_MASK;
|
||||
|
||||
clock = root_clk_by_index(src);
|
||||
if (!clock)
|
||||
return;
|
||||
|
||||
clk->parent = clock;
|
||||
clk->set_parent = aclk_set_parent;
|
||||
}
|
||||
|
||||
void __init tcc_clocks_init(unsigned long xi_freq, unsigned long xti_freq)
|
||||
{
|
||||
int i;
|
||||
|
||||
xi_rate = xi_freq;
|
||||
xti_rate = xti_freq;
|
||||
|
||||
/* fixup parents and add the clock */
|
||||
for (i = 0; i < ARRAY_SIZE(lookups); i++) {
|
||||
find_aclk_parent(lookups[i].clk);
|
||||
clkdev_add(&lookups[i]);
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
#ifndef MACH_TCC8K_COMMON_H
|
||||
#define MACH_TCC8K_COMMON_H
|
||||
|
||||
extern void tcc_clocks_init(unsigned long xi_freq, unsigned long xti_freq);
|
||||
|
||||
#endif
|
||||
|
|
@ -1,3 +1,3 @@
|
|||
# "Telechips Platform Common Modules"
|
||||
|
||||
obj-y := system.o
|
||||
obj-y := clock.o system.o
|
||||
|
|
|
|||
|
|
@ -0,0 +1,179 @@
|
|||
/*
|
||||
* Clock framework for Telechips SoCs
|
||||
* Based on arch/arm/plat-mxc/clock.c
|
||||
*
|
||||
* Copyright (C) 2004 - 2005 Nokia corporation
|
||||
* Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
|
||||
* Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
|
||||
* Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
|
||||
* Copyright 2010 Hans J. Koch, hjk@linutronix.de
|
||||
*
|
||||
* Licensed under the terms of the GPL v2.
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/mutex.h>
|
||||
#include <linux/string.h>
|
||||
|
||||
#include <mach/clock.h>
|
||||
#include <mach/hardware.h>
|
||||
|
||||
static DEFINE_MUTEX(clocks_mutex);
|
||||
|
||||
/*-------------------------------------------------------------------------
|
||||
* Standard clock functions defined in include/linux/clk.h
|
||||
*-------------------------------------------------------------------------*/
|
||||
|
||||
static void __clk_disable(struct clk *clk)
|
||||
{
|
||||
BUG_ON(clk->refcount == 0);
|
||||
|
||||
if (!(--clk->refcount) && clk->disable) {
|
||||
/* Unconditionally disable the clock in hardware */
|
||||
clk->disable(clk);
|
||||
/* recursively disable parents */
|
||||
if (clk->parent)
|
||||
__clk_disable(clk->parent);
|
||||
}
|
||||
}
|
||||
|
||||
static int __clk_enable(struct clk *clk)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
if (clk->refcount++ == 0 && clk->enable) {
|
||||
if (clk->parent)
|
||||
ret = __clk_enable(clk->parent);
|
||||
if (ret)
|
||||
return ret;
|
||||
else
|
||||
return clk->enable(clk);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* This function increments the reference count on the clock and enables the
|
||||
* clock if not already enabled. The parent clock tree is recursively enabled
|
||||
*/
|
||||
int clk_enable(struct clk *clk)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
if (!clk)
|
||||
return -EINVAL;
|
||||
|
||||
mutex_lock(&clocks_mutex);
|
||||
ret = __clk_enable(clk);
|
||||
mutex_unlock(&clocks_mutex);
|
||||
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(clk_enable);
|
||||
|
||||
/* This function decrements the reference count on the clock and disables
|
||||
* the clock when reference count is 0. The parent clock tree is
|
||||
* recursively disabled
|
||||
*/
|
||||
void clk_disable(struct clk *clk)
|
||||
{
|
||||
if (!clk)
|
||||
return;
|
||||
|
||||
mutex_lock(&clocks_mutex);
|
||||
__clk_disable(clk);
|
||||
mutex_unlock(&clocks_mutex);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(clk_disable);
|
||||
|
||||
/* Retrieve the *current* clock rate. If the clock itself
|
||||
* does not provide a special calculation routine, ask
|
||||
* its parent and so on, until one is able to return
|
||||
* a valid clock rate
|
||||
*/
|
||||
unsigned long clk_get_rate(struct clk *clk)
|
||||
{
|
||||
if (!clk)
|
||||
return 0UL;
|
||||
|
||||
if (clk->get_rate)
|
||||
return clk->get_rate(clk);
|
||||
|
||||
return clk_get_rate(clk->parent);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(clk_get_rate);
|
||||
|
||||
/* Round the requested clock rate to the nearest supported
|
||||
* rate that is less than or equal to the requested rate.
|
||||
* This is dependent on the clock's current parent.
|
||||
*/
|
||||
long clk_round_rate(struct clk *clk, unsigned long rate)
|
||||
{
|
||||
if (!clk)
|
||||
return 0;
|
||||
if (!clk->round_rate)
|
||||
return 0;
|
||||
|
||||
return clk->round_rate(clk, rate);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(clk_round_rate);
|
||||
|
||||
/* Set the clock to the requested clock rate. The rate must
|
||||
* match a supported rate exactly based on what clk_round_rate returns
|
||||
*/
|
||||
int clk_set_rate(struct clk *clk, unsigned long rate)
|
||||
{
|
||||
int ret = -EINVAL;
|
||||
|
||||
if (!clk)
|
||||
return ret;
|
||||
if (!clk->set_rate || !rate)
|
||||
return ret;
|
||||
|
||||
mutex_lock(&clocks_mutex);
|
||||
ret = clk->set_rate(clk, rate);
|
||||
mutex_unlock(&clocks_mutex);
|
||||
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(clk_set_rate);
|
||||
|
||||
/* Set the clock's parent to another clock source */
|
||||
int clk_set_parent(struct clk *clk, struct clk *parent)
|
||||
{
|
||||
struct clk *old;
|
||||
int ret = -EINVAL;
|
||||
|
||||
if (!clk)
|
||||
return ret;
|
||||
if (!clk->set_parent || !parent)
|
||||
return ret;
|
||||
|
||||
mutex_lock(&clocks_mutex);
|
||||
old = clk->parent;
|
||||
if (clk->refcount)
|
||||
__clk_enable(parent);
|
||||
ret = clk->set_parent(clk, parent);
|
||||
if (ret)
|
||||
old = parent;
|
||||
if (clk->refcount)
|
||||
__clk_disable(old);
|
||||
mutex_unlock(&clocks_mutex);
|
||||
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(clk_set_parent);
|
||||
|
||||
/* Retrieve the clock's parent clock source */
|
||||
struct clk *clk_get_parent(struct clk *clk)
|
||||
{
|
||||
if (!clk)
|
||||
return NULL;
|
||||
|
||||
return clk->parent;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(clk_get_parent);
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
#ifndef __ASM_MACH_CLKDEV_H
|
||||
#define __ASM_MACH_CLKDEV_H
|
||||
|
||||
#define __clk_get(clk) ({ 1; })
|
||||
#define __clk_put(clk) do { } while (0)
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
/*
|
||||
* Low level clock header file for Telechips TCC architecture
|
||||
* (C) 2010 Hans J. Koch <hjk@linutronix.de>
|
||||
*
|
||||
* Licensed under the GPL v2.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_TCC_CLOCK_H__
|
||||
#define __ASM_ARCH_TCC_CLOCK_H__
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
struct clk {
|
||||
struct clk *parent;
|
||||
/* id number of a root clock, 0 for normal clocks */
|
||||
int root_id;
|
||||
/* Reference count of clock enable/disable */
|
||||
int refcount;
|
||||
/* Address of associated BCLKCTRx register. Must be set. */
|
||||
void __iomem *bclkctr;
|
||||
/* Bit position for BCLKCTRx. Must be set. */
|
||||
int bclk_shift;
|
||||
/* Address of ACLKxxx register, if any. */
|
||||
void __iomem *aclkreg;
|
||||
/* get the current clock rate (always a fresh value) */
|
||||
unsigned long (*get_rate) (struct clk *);
|
||||
/* Function ptr to set the clock to a new rate. The rate must match a
|
||||
supported rate returned from round_rate. Leave blank if clock is not
|
||||
programmable */
|
||||
int (*set_rate) (struct clk *, unsigned long);
|
||||
/* Function ptr to round the requested clock rate to the nearest
|
||||
supported rate that is less than or equal to the requested rate. */
|
||||
unsigned long (*round_rate) (struct clk *, unsigned long);
|
||||
/* Function ptr to enable the clock. Leave blank if clock can not
|
||||
be gated. */
|
||||
int (*enable) (struct clk *);
|
||||
/* Function ptr to disable the clock. Leave blank if clock can not
|
||||
be gated. */
|
||||
void (*disable) (struct clk *);
|
||||
/* Function ptr to set the parent clock of the clock. */
|
||||
int (*set_parent) (struct clk *, struct clk *);
|
||||
};
|
||||
|
||||
int clk_register(struct clk *clk);
|
||||
void clk_unregister(struct clk *clk);
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ASM_ARCH_MXC_CLOCK_H__ */
|
||||
|
|
@ -30,13 +30,13 @@
|
|||
#define EXT_MEM_CTRL_BASE 0xf0000000
|
||||
#define EXT_MEM_CTRL_SIZE SZ_4K
|
||||
|
||||
#define CS1_BASE_VIRT 0xf7000000
|
||||
#define AHB_PERI_BASE_VIRT 0xf4000000
|
||||
#define APB0_PERI_BASE_VIRT 0xf1000000
|
||||
#define APB1_PERI_BASE_VIRT 0xf2000000
|
||||
#define EXT_MEM_CTRL_BASE_VIRT 0xf3000000
|
||||
#define INT_SRAM_BASE_VIRT 0xf5000000
|
||||
#define DATA_TCM_BASE_VIRT 0xf6000000
|
||||
#define CS1_BASE_VIRT (void __iomem *)0xf7000000
|
||||
#define AHB_PERI_BASE_VIRT (void __iomem *)0xf4000000
|
||||
#define APB0_PERI_BASE_VIRT (void __iomem *)0xf1000000
|
||||
#define APB1_PERI_BASE_VIRT (void __iomem *)0xf2000000
|
||||
#define EXT_MEM_CTRL_BASE_VIRT (void __iomem *)0xf3000000
|
||||
#define INT_SRAM_BASE_VIRT (void __iomem *)0xf5000000
|
||||
#define DATA_TCM_BASE_VIRT (void __iomem *)0xf6000000
|
||||
|
||||
#define __REG(x) (*((volatile u32 *)(x)))
|
||||
|
||||
|
|
@ -649,8 +649,7 @@
|
|||
#define PMGPIO_APB_OFFS 0x800
|
||||
|
||||
/* Clock controller registers */
|
||||
#define CKC_BASE (APB1_PERI_BASE_VIRT + 0x6000)
|
||||
#define CKC_BASE_PHYS (APB1_PERI_BASE + 0x6000)
|
||||
#define CKC_BASE ((void __iomem *)(APB1_PERI_BASE_VIRT + 0x6000))
|
||||
|
||||
#define CLKCTRL_OFFS 0x00
|
||||
#define PLL0CFG_OFFS 0x04
|
||||
|
|
@ -724,8 +723,20 @@
|
|||
/* SWRESET1 bits */
|
||||
#define SWRESET1_USBH1 (1 << 20)
|
||||
|
||||
/* System clock sources */
|
||||
/* System clock sources.
|
||||
* Note: These are the clock sources that serve as parents for
|
||||
* all other clocks. They have no parents themselves.
|
||||
*
|
||||
* These values are used for struct clk->root_id. All clocks
|
||||
* that are not system clock sources have this value set to
|
||||
* CLK_SRC_NOROOT.
|
||||
* The values for system clocks start with CLK_SRC_PLL0 == 0
|
||||
* because this gives us exactly the values needed for the lower
|
||||
* 4 bits of ACLK_* registers. Therefore, CLK_SRC_NOROOT is
|
||||
* defined as -1 to not disturb the order.
|
||||
*/
|
||||
enum root_clks {
|
||||
CLK_SRC_NOROOT = -1,
|
||||
CLK_SRC_PLL0 = 0,
|
||||
CLK_SRC_PLL1,
|
||||
CLK_SRC_PLL0DIV,
|
||||
|
|
|
|||
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