ARM: socfpga: dts: add clocks to the Arria10 platform
Add all the clock nodes for the Arria10 platform. At the same time, update the peripherals with their respective clocks property. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> --- v2: Add the l4_sys_free_clk node
This commit is contained in:
Dinh Nguyen
Родитель
c01e8cdb7b
Коммит
da29d824a6
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@ -86,6 +86,21 @@
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#address-cells = <1>;
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#size-cells = <0>;
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cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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};
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cb_intosc_ls_clk: cb_intosc_ls_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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};
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f2s_free_clk: f2s_free_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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};
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osc1: osc1 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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@ -95,16 +110,286 @@
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#address-cells = <1>;
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#size-cells = <0>;
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#clock-cells = <0>;
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compatible = "altr,socfpga-pll-clock";
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clocks = <&osc1>;
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compatible = "altr,socfpga-a10-pll-clock";
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clocks = <&osc1>, <&cb_intosc_ls_clk>,
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<&f2s_free_clk>;
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reg = <0x40>;
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main_mpu_base_clk: main_mpu_base_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&main_pll>;
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div-reg = <0x140 0 11>;
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};
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main_noc_base_clk: main_noc_base_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&main_pll>;
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div-reg = <0x144 0 11>;
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};
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main_emaca_clk: main_emaca_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&main_pll>;
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reg = <0x68>;
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};
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main_emacb_clk: main_emacb_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&main_pll>;
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reg = <0x6C>;
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};
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main_emac_ptp_clk: main_emac_ptp_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&main_pll>;
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reg = <0x70>;
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};
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main_gpio_db_clk: main_gpio_db_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&main_pll>;
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reg = <0x74>;
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};
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main_sdmmc_clk: main_sdmmc_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk"
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;
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clocks = <&main_pll>;
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reg = <0x78>;
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};
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main_s2f_usr0_clk: main_s2f_usr0_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&main_pll>;
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reg = <0x7C>;
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};
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main_s2f_usr1_clk: main_s2f_usr1_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&main_pll>;
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reg = <0x80>;
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};
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main_hmc_pll_ref_clk: main_hmc_pll_ref_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&main_pll>;
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reg = <0x84>;
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};
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main_periph_ref_clk: main_periph_ref_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&main_pll>;
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reg = <0x9C>;
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};
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};
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periph_pll: periph_pll {
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#address-cells = <1>;
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#size-cells = <0>;
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#clock-cells = <0>;
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compatible = "altr,socfpga-pll-clock";
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clocks = <&osc1>;
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compatible = "altr,socfpga-a10-pll-clock";
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clocks = <&osc1>, <&cb_intosc_ls_clk>,
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<&f2s_free_clk>, <&main_periph_ref_clk>;
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reg = <0xC0>;
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peri_mpu_base_clk: peri_mpu_base_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&periph_pll>;
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div-reg = <0x140 16 11>;
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};
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peri_noc_base_clk: peri_noc_base_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&periph_pll>;
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div-reg = <0x144 16 11>;
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};
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peri_emaca_clk: peri_emaca_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&periph_pll>;
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reg = <0xE8>;
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};
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peri_emacb_clk: peri_emacb_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&periph_pll>;
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reg = <0xEC>;
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};
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peri_emac_ptp_clk: peri_emac_ptp_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&periph_pll>;
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reg = <0xF0>;
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};
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peri_gpio_db_clk: peri_gpio_db_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&periph_pll>;
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reg = <0xF4>;
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};
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peri_sdmmc_clk: peri_sdmmc_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&periph_pll>;
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reg = <0xF8>;
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};
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peri_s2f_usr0_clk: peri_s2f_usr0_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&periph_pll>;
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reg = <0xFC>;
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};
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peri_s2f_usr1_clk: peri_s2f_usr1_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&periph_pll>;
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reg = <0x100>;
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};
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peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&periph_pll>;
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reg = <0x104>;
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};
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};
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mpu_free_clk: mpu_free_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>,
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<&osc1>, <&cb_intosc_hs_div2_clk>,
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<&f2s_free_clk>;
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reg = <0x60>;
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};
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noc_free_clk: noc_free_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>,
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<&osc1>, <&cb_intosc_hs_div2_clk>,
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<&f2s_free_clk>;
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reg = <0x64>;
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};
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s2f_user1_free_clk: s2f_user1_free_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>,
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<&osc1>, <&cb_intosc_hs_div2_clk>,
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<&f2s_free_clk>;
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reg = <0x104>;
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};
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sdmmc_free_clk: sdmmc_free_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>,
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<&osc1>, <&cb_intosc_hs_div2_clk>,
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<&f2s_free_clk>;
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fixed-divider = <4>;
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reg = <0xF8>;
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};
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l4_sys_free_clk: l4_sys_free_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-perip-clk";
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clocks = <&noc_free_clk>;
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fixed-divider = <4>;
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};
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l4_main_clk: l4_main_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-gate-clk";
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clocks = <&noc_free_clk>;
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div-reg = <0xA8 0 2>;
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clk-gate = <0x48 1>;
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};
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l4_mp_clk: l4_mp_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-gate-clk";
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clocks = <&noc_free_clk>;
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div-reg = <0xA8 8 2>;
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clk-gate = <0x48 2>;
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};
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l4_sp_clk: l4_sp_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-gate-clk";
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clocks = <&noc_free_clk>;
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div-reg = <0xA8 16 2>;
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clk-gate = <0x48 3>;
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};
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mpu_periph_clk: mpu_periph_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-gate-clk";
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clocks = <&mpu_free_clk>;
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fixed-divider = <4>;
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clk-gate = <0x48 0>;
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};
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sdmmc_clk: sdmmc_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-gate-clk";
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clocks = <&sdmmc_free_clk>;
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clk-gate = <0xC8 5>;
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};
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qspi_clk: qspi_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-gate-clk";
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clocks = <&l4_main_clk>;
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clk-gate = <0xC8 11>;
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};
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nand_clk: nand_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-gate-clk";
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clocks = <&l4_mp_clk>;
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clk-gate = <0xC8 10>;
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};
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spi_m_clk: spi_m_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-gate-clk";
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clocks = <&l4_main_clk>;
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clk-gate = <0xC8 9>;
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};
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usb_clk: usb_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-gate-clk";
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clocks = <&l4_mp_clk>;
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clk-gate = <0xC8 8>;
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};
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s2f_usr1_clk: s2f_usr1_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-a10-gate-clk";
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clocks = <&peri_s2f_usr1_clk>;
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clk-gate = <0xC8 6>;
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};
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};
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};
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@ -266,6 +551,8 @@
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reg = <0xff808000 0x1000>;
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interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
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fifo-depth = <0x400>;
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clocks = <&l4_mp_clk>, <&sdmmc_free_clk>;
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clock-names = "biu", "ciu";
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status = "disabled";
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};
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@ -291,30 +578,39 @@
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0xffffc600 0x100>;
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interrupts = <1 13 0xf04>;
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clocks = <&mpu_periph_clk>;
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};
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timer0: timer0@ffc02700 {
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compatible = "snps,dw-apb-timer";
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interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xffc02700 0x100>;
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clocks = <&l4_sp_clk>;
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clock-names = "timer";
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};
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timer1: timer1@ffc02800 {
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compatible = "snps,dw-apb-timer";
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interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xffc02800 0x100>;
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clocks = <&l4_sp_clk>;
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clock-names = "timer";
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};
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timer2: timer2@ffd00000 {
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compatible = "snps,dw-apb-timer";
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interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xffd00000 0x100>;
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clocks = <&l4_sys_free_clk>;
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clock-names = "timer";
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};
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timer3: timer3@ffd00100 {
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compatible = "snps,dw-apb-timer";
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interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xffd01000 0x100>;
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clocks = <&l4_sys_free_clk>;
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clock-names = "timer";
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};
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uart0: serial0@ffc02000 {
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@ -332,6 +628,7 @@
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interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&l4_sp_clk>;
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status = "disabled";
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};
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@ -345,6 +642,8 @@
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compatible = "snps,dwc2";
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reg = <0xffb00000 0xffff>;
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interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&usb_clk>;
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clock-names = "otg";
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phys = <&usbphy0>;
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phy-names = "usb2-phy";
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status = "disabled";
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@ -363,6 +662,7 @@
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compatible = "snps,dw-wdt";
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reg = <0xffd00200 0x100>;
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interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&l4_sys_free_clk>;
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status = "disabled";
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};
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@ -370,6 +670,7 @@
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compatible = "snps,dw-wdt";
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reg = <0xffd00300 0x100>;
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interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&l4_sys_free_clk>;
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status = "disabled";
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};
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};
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