drm/radeon/kms: add common dpm infrastructure
This adds the common dpm (dynamic power management) infrastructure: - dpm callbacks - dpm init/fini/suspend/resume - dpm power state selection No device specific code is enabled yet. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher
Родитель
ca361b6538
Коммит
da321c8a6a
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@ -96,6 +96,7 @@ extern int radeon_pcie_gen2;
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extern int radeon_msi;
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extern int radeon_lockup_timeout;
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extern int radeon_fastfb;
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extern int radeon_dpm;
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/*
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* Copy from radeon_drv.h so we don't have to include both and have conflicting
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@ -1043,6 +1044,7 @@ struct radeon_wb {
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enum radeon_pm_method {
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PM_METHOD_PROFILE,
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PM_METHOD_DYNPM,
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PM_METHOD_DPM,
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};
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enum radeon_dynpm_state {
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@ -1068,11 +1070,23 @@ enum radeon_voltage_type {
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};
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enum radeon_pm_state_type {
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/* not used for dpm */
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POWER_STATE_TYPE_DEFAULT,
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POWER_STATE_TYPE_POWERSAVE,
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/* user selectable states */
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POWER_STATE_TYPE_BATTERY,
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POWER_STATE_TYPE_BALANCED,
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POWER_STATE_TYPE_PERFORMANCE,
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/* internal states */
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POWER_STATE_TYPE_INTERNAL_UVD,
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POWER_STATE_TYPE_INTERNAL_UVD_SD,
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POWER_STATE_TYPE_INTERNAL_UVD_HD,
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POWER_STATE_TYPE_INTERNAL_UVD_HD2,
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POWER_STATE_TYPE_INTERNAL_UVD_MVC,
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POWER_STATE_TYPE_INTERNAL_BOOT,
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POWER_STATE_TYPE_INTERNAL_THERMAL,
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POWER_STATE_TYPE_INTERNAL_ACPI,
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POWER_STATE_TYPE_INTERNAL_ULV,
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};
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enum radeon_pm_profile_type {
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@ -1101,12 +1115,16 @@ struct radeon_pm_profile {
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enum radeon_int_thermal_type {
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THERMAL_TYPE_NONE,
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THERMAL_TYPE_EXTERNAL,
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THERMAL_TYPE_EXTERNAL_GPIO,
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THERMAL_TYPE_RV6XX,
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THERMAL_TYPE_RV770,
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THERMAL_TYPE_ADT7473_WITH_INTERNAL,
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THERMAL_TYPE_EVERGREEN,
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THERMAL_TYPE_SUMO,
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THERMAL_TYPE_NI,
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THERMAL_TYPE_SI,
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THERMAL_TYPE_EMC2103_WITH_INTERNAL,
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THERMAL_TYPE_CI,
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};
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@ -1161,6 +1179,60 @@ struct radeon_power_state {
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*/
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#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
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struct radeon_ps {
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u32 caps; /* vbios flags */
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u32 class; /* vbios flags */
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u32 class2; /* vbios flags */
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/* UVD clocks */
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u32 vclk;
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u32 dclk;
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/* asic priv */
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void *ps_priv;
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};
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struct radeon_dpm_thermal {
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/* thermal interrupt work */
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struct work_struct work;
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/* low temperature threshold */
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int min_temp;
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/* high temperature threshold */
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int max_temp;
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/* was interrupt low to high or high to low */
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bool high_to_low;
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};
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struct radeon_dpm {
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struct radeon_ps *ps;
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/* number of valid power states */
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int num_ps;
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/* current power state that is active */
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struct radeon_ps *current_ps;
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/* requested power state */
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struct radeon_ps *requested_ps;
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/* boot up power state */
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struct radeon_ps *boot_ps;
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/* default uvd power state */
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struct radeon_ps *uvd_ps;
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enum radeon_pm_state_type state;
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enum radeon_pm_state_type user_state;
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u32 platform_caps;
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u32 voltage_response_time;
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u32 backbias_response_time;
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void *priv;
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u32 new_active_crtcs;
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int new_active_crtc_count;
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u32 current_active_crtcs;
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int current_active_crtc_count;
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/* special states active */
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bool thermal_active;
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/* thermal handling */
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struct radeon_dpm_thermal thermal;
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};
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void radeon_dpm_enable_power_state(struct radeon_device *rdev,
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enum radeon_pm_state_type dpm_state);
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struct radeon_pm {
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struct mutex mutex;
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/* write locked while reprogramming mclk */
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@ -1214,6 +1286,9 @@ struct radeon_pm {
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/* internal thermal controller on rv6xx+ */
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enum radeon_int_thermal_type int_thermal_type;
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struct device *int_hwmon_dev;
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/* dpm */
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bool dpm_enabled;
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struct radeon_dpm dpm;
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};
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int radeon_pm_get_type_index(struct radeon_device *rdev,
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@ -1415,7 +1490,7 @@ struct radeon_asic {
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bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
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void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
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} hpd;
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/* power management */
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/* static power management */
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struct {
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void (*misc)(struct radeon_device *rdev);
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void (*prepare)(struct radeon_device *rdev);
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@ -1432,6 +1507,19 @@ struct radeon_asic {
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int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
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int (*get_temperature)(struct radeon_device *rdev);
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} pm;
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/* dynamic power management */
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struct {
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int (*init)(struct radeon_device *rdev);
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void (*setup_asic)(struct radeon_device *rdev);
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int (*enable)(struct radeon_device *rdev);
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void (*disable)(struct radeon_device *rdev);
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int (*set_power_state)(struct radeon_device *rdev);
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void (*display_configuration_changed)(struct radeon_device *rdev);
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void (*fini)(struct radeon_device *rdev);
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u32 (*get_sclk)(struct radeon_device *rdev, bool low);
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u32 (*get_mclk)(struct radeon_device *rdev, bool low);
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void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
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} dpm;
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/* pageflipping */
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struct {
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void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
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@ -2124,6 +2212,16 @@ void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
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#define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
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#define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
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#define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
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#define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
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#define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
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#define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
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#define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
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#define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
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#define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
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#define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
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#define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
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#define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
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#define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
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/* Common functions */
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/* AGP */
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@ -165,6 +165,7 @@ int radeon_pcie_gen2 = -1;
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int radeon_msi = -1;
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int radeon_lockup_timeout = 10000;
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int radeon_fastfb = 0;
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int radeon_dpm = -1;
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MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
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module_param_named(no_wb, radeon_no_wb, int, 0444);
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@ -220,6 +221,9 @@ module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444);
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MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)");
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module_param_named(fastfb, radeon_fastfb, int, 0444);
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MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
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module_param_named(dpm, radeon_dpm, int, 0444);
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static struct pci_device_id pciidlist[] = {
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radeon_PCI_IDS
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};
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@ -388,7 +388,8 @@ static ssize_t radeon_get_pm_method(struct device *dev,
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int pm = rdev->pm.pm_method;
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return snprintf(buf, PAGE_SIZE, "%s\n",
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(pm == PM_METHOD_DYNPM) ? "dynpm" : "profile");
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(pm == PM_METHOD_DYNPM) ? "dynpm" :
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(pm == PM_METHOD_PROFILE) ? "profile" : "dpm");
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}
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static ssize_t radeon_set_pm_method(struct device *dev,
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@ -399,6 +400,11 @@ static ssize_t radeon_set_pm_method(struct device *dev,
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struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
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struct radeon_device *rdev = ddev->dev_private;
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/* we don't support the legacy modes with dpm */
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if (rdev->pm.pm_method == PM_METHOD_DPM) {
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count = -EINVAL;
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goto fail;
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}
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if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
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mutex_lock(&rdev->pm.mutex);
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@ -423,8 +429,48 @@ fail:
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return count;
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}
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static ssize_t radeon_get_dpm_state(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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{
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struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
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struct radeon_device *rdev = ddev->dev_private;
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enum radeon_pm_state_type pm = rdev->pm.dpm.user_state;
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return snprintf(buf, PAGE_SIZE, "%s\n",
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(pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
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(pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
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}
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static ssize_t radeon_set_dpm_state(struct device *dev,
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struct device_attribute *attr,
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const char *buf,
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size_t count)
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{
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struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
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struct radeon_device *rdev = ddev->dev_private;
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mutex_lock(&rdev->pm.mutex);
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if (strncmp("battery", buf, strlen("battery")) == 0)
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rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY;
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else if (strncmp("balanced", buf, strlen("balanced")) == 0)
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rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
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else if (strncmp("performance", buf, strlen("performance")) == 0)
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rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE;
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else {
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mutex_unlock(&rdev->pm.mutex);
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count = -EINVAL;
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goto fail;
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}
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mutex_unlock(&rdev->pm.mutex);
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radeon_pm_compute_clocks(rdev);
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fail:
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return count;
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}
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static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
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static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
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static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, radeon_get_dpm_state, radeon_set_dpm_state);
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static ssize_t radeon_hwmon_show_temp(struct device *dev,
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struct device_attribute *attr,
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@ -508,7 +554,228 @@ static void radeon_hwmon_fini(struct radeon_device *rdev)
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}
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}
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void radeon_pm_suspend(struct radeon_device *rdev)
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static void radeon_dpm_thermal_work_handler(struct work_struct *work)
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{
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struct radeon_device *rdev =
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container_of(work, struct radeon_device,
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pm.dpm.thermal.work);
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/* switch to the thermal state */
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enum radeon_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
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if (!rdev->pm.dpm_enabled)
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return;
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if (rdev->asic->pm.get_temperature) {
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int temp = radeon_get_temperature(rdev);
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if (temp < rdev->pm.dpm.thermal.min_temp)
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/* switch back the user state */
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dpm_state = rdev->pm.dpm.user_state;
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} else {
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if (rdev->pm.dpm.thermal.high_to_low)
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/* switch back the user state */
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dpm_state = rdev->pm.dpm.user_state;
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}
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radeon_dpm_enable_power_state(rdev, dpm_state);
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}
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static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev,
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enum radeon_pm_state_type dpm_state)
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{
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int i;
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struct radeon_ps *ps;
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u32 ui_class;
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restart_search:
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/* balanced states don't exist at the moment */
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if (dpm_state == POWER_STATE_TYPE_BALANCED)
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dpm_state = POWER_STATE_TYPE_PERFORMANCE;
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/* Pick the best power state based on current conditions */
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for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
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ps = &rdev->pm.dpm.ps[i];
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ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
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switch (dpm_state) {
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/* user states */
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case POWER_STATE_TYPE_BATTERY:
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if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
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if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
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if (rdev->pm.dpm.new_active_crtc_count < 2)
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return ps;
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} else
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return ps;
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}
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break;
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case POWER_STATE_TYPE_BALANCED:
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if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
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if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
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if (rdev->pm.dpm.new_active_crtc_count < 2)
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return ps;
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} else
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return ps;
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}
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break;
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case POWER_STATE_TYPE_PERFORMANCE:
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if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
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if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
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if (rdev->pm.dpm.new_active_crtc_count < 2)
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return ps;
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} else
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return ps;
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}
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break;
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/* internal states */
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case POWER_STATE_TYPE_INTERNAL_UVD:
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return rdev->pm.dpm.uvd_ps;
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case POWER_STATE_TYPE_INTERNAL_UVD_SD:
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if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
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return ps;
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break;
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case POWER_STATE_TYPE_INTERNAL_UVD_HD:
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if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
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return ps;
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break;
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case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
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if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
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return ps;
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break;
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case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
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if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
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return ps;
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break;
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case POWER_STATE_TYPE_INTERNAL_BOOT:
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return rdev->pm.dpm.boot_ps;
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case POWER_STATE_TYPE_INTERNAL_THERMAL:
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if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
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return ps;
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break;
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case POWER_STATE_TYPE_INTERNAL_ACPI:
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if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
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return ps;
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break;
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case POWER_STATE_TYPE_INTERNAL_ULV:
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if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
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return ps;
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break;
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default:
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break;
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}
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}
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/* use a fallback state if we didn't match */
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switch (dpm_state) {
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case POWER_STATE_TYPE_INTERNAL_UVD_SD:
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case POWER_STATE_TYPE_INTERNAL_UVD_HD:
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case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
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case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
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return rdev->pm.dpm.uvd_ps;
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case POWER_STATE_TYPE_INTERNAL_THERMAL:
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dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
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goto restart_search;
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case POWER_STATE_TYPE_INTERNAL_ACPI:
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dpm_state = POWER_STATE_TYPE_BATTERY;
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goto restart_search;
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case POWER_STATE_TYPE_BATTERY:
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dpm_state = POWER_STATE_TYPE_PERFORMANCE;
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goto restart_search;
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default:
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break;
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}
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return NULL;
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}
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static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev)
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{
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int i;
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struct radeon_ps *ps;
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enum radeon_pm_state_type dpm_state;
|
||||
|
||||
/* if dpm init failed */
|
||||
if (!rdev->pm.dpm_enabled)
|
||||
return;
|
||||
|
||||
if (rdev->pm.dpm.user_state != rdev->pm.dpm.state) {
|
||||
/* add other state override checks here */
|
||||
if (!rdev->pm.dpm.thermal_active)
|
||||
rdev->pm.dpm.state = rdev->pm.dpm.user_state;
|
||||
}
|
||||
dpm_state = rdev->pm.dpm.state;
|
||||
|
||||
ps = radeon_dpm_pick_power_state(rdev, dpm_state);
|
||||
if (ps)
|
||||
rdev->pm.dpm.requested_ps = ps;
|
||||
else
|
||||
return;
|
||||
|
||||
/* no need to reprogram if nothing changed */
|
||||
if (rdev->pm.dpm.current_ps == rdev->pm.dpm.requested_ps) {
|
||||
/* update display watermarks based on new power state */
|
||||
if (rdev->pm.dpm.new_active_crtcs != rdev->pm.dpm.current_active_crtcs) {
|
||||
radeon_bandwidth_update(rdev);
|
||||
/* update displays */
|
||||
radeon_dpm_display_configuration_changed(rdev);
|
||||
rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
|
||||
rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
printk("switching from power state:\n");
|
||||
radeon_dpm_print_power_state(rdev, rdev->pm.dpm.current_ps);
|
||||
printk("switching to power state:\n");
|
||||
radeon_dpm_print_power_state(rdev, rdev->pm.dpm.requested_ps);
|
||||
|
||||
mutex_lock(&rdev->ddev->struct_mutex);
|
||||
down_write(&rdev->pm.mclk_lock);
|
||||
mutex_lock(&rdev->ring_lock);
|
||||
|
||||
/* update display watermarks based on new power state */
|
||||
radeon_bandwidth_update(rdev);
|
||||
/* update displays */
|
||||
radeon_dpm_display_configuration_changed(rdev);
|
||||
|
||||
rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
|
||||
rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
|
||||
|
||||
/* wait for the rings to drain */
|
||||
for (i = 0; i < RADEON_NUM_RINGS; i++) {
|
||||
struct radeon_ring *ring = &rdev->ring[i];
|
||||
if (ring->ready)
|
||||
radeon_fence_wait_empty_locked(rdev, i);
|
||||
}
|
||||
|
||||
/* program the new power state */
|
||||
radeon_dpm_set_power_state(rdev);
|
||||
|
||||
/* update current power state */
|
||||
rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps;
|
||||
|
||||
mutex_unlock(&rdev->ring_lock);
|
||||
up_write(&rdev->pm.mclk_lock);
|
||||
mutex_unlock(&rdev->ddev->struct_mutex);
|
||||
}
|
||||
|
||||
void radeon_dpm_enable_power_state(struct radeon_device *rdev,
|
||||
enum radeon_pm_state_type dpm_state)
|
||||
{
|
||||
if (!rdev->pm.dpm_enabled)
|
||||
return;
|
||||
|
||||
mutex_lock(&rdev->pm.mutex);
|
||||
switch (dpm_state) {
|
||||
case POWER_STATE_TYPE_INTERNAL_THERMAL:
|
||||
rdev->pm.dpm.thermal_active = true;
|
||||
break;
|
||||
default:
|
||||
rdev->pm.dpm.thermal_active = false;
|
||||
break;
|
||||
}
|
||||
rdev->pm.dpm.state = dpm_state;
|
||||
mutex_unlock(&rdev->pm.mutex);
|
||||
radeon_pm_compute_clocks(rdev);
|
||||
}
|
||||
|
||||
static void radeon_pm_suspend_old(struct radeon_device *rdev)
|
||||
{
|
||||
mutex_lock(&rdev->pm.mutex);
|
||||
if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
|
||||
|
|
@ -520,7 +787,26 @@ void radeon_pm_suspend(struct radeon_device *rdev)
|
|||
cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
|
||||
}
|
||||
|
||||
void radeon_pm_resume(struct radeon_device *rdev)
|
||||
static void radeon_pm_suspend_dpm(struct radeon_device *rdev)
|
||||
{
|
||||
mutex_lock(&rdev->pm.mutex);
|
||||
/* disable dpm */
|
||||
radeon_dpm_disable(rdev);
|
||||
/* reset the power state */
|
||||
rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
|
||||
rdev->pm.dpm_enabled = false;
|
||||
mutex_unlock(&rdev->pm.mutex);
|
||||
}
|
||||
|
||||
void radeon_pm_suspend(struct radeon_device *rdev)
|
||||
{
|
||||
if (rdev->pm.pm_method == PM_METHOD_DPM)
|
||||
radeon_pm_suspend_dpm(rdev);
|
||||
else
|
||||
radeon_pm_suspend_old(rdev);
|
||||
}
|
||||
|
||||
static void radeon_pm_resume_old(struct radeon_device *rdev)
|
||||
{
|
||||
/* set up the default clocks if the MC ucode is loaded */
|
||||
if ((rdev->family >= CHIP_BARTS) &&
|
||||
|
|
@ -555,12 +841,50 @@ void radeon_pm_resume(struct radeon_device *rdev)
|
|||
radeon_pm_compute_clocks(rdev);
|
||||
}
|
||||
|
||||
int radeon_pm_init(struct radeon_device *rdev)
|
||||
static void radeon_pm_resume_dpm(struct radeon_device *rdev)
|
||||
{
|
||||
int ret;
|
||||
|
||||
/* asic init will reset to the boot state */
|
||||
mutex_lock(&rdev->pm.mutex);
|
||||
rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
|
||||
radeon_dpm_setup_asic(rdev);
|
||||
ret = radeon_dpm_enable(rdev);
|
||||
mutex_unlock(&rdev->pm.mutex);
|
||||
if (ret) {
|
||||
DRM_ERROR("radeon: dpm resume failed\n");
|
||||
if ((rdev->family >= CHIP_BARTS) &&
|
||||
(rdev->family <= CHIP_CAYMAN) &&
|
||||
rdev->mc_fw) {
|
||||
if (rdev->pm.default_vddc)
|
||||
radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
|
||||
SET_VOLTAGE_TYPE_ASIC_VDDC);
|
||||
if (rdev->pm.default_vddci)
|
||||
radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
|
||||
SET_VOLTAGE_TYPE_ASIC_VDDCI);
|
||||
if (rdev->pm.default_sclk)
|
||||
radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
|
||||
if (rdev->pm.default_mclk)
|
||||
radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
|
||||
}
|
||||
} else {
|
||||
rdev->pm.dpm_enabled = true;
|
||||
radeon_pm_compute_clocks(rdev);
|
||||
}
|
||||
}
|
||||
|
||||
void radeon_pm_resume(struct radeon_device *rdev)
|
||||
{
|
||||
if (rdev->pm.pm_method == PM_METHOD_DPM)
|
||||
radeon_pm_resume_dpm(rdev);
|
||||
else
|
||||
radeon_pm_resume_old(rdev);
|
||||
}
|
||||
|
||||
static int radeon_pm_init_old(struct radeon_device *rdev)
|
||||
{
|
||||
int ret;
|
||||
|
||||
/* default to profile method */
|
||||
rdev->pm.pm_method = PM_METHOD_PROFILE;
|
||||
rdev->pm.profile = PM_PROFILE_DEFAULT;
|
||||
rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
|
||||
rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
|
||||
|
|
@ -622,7 +946,103 @@ int radeon_pm_init(struct radeon_device *rdev)
|
|||
return 0;
|
||||
}
|
||||
|
||||
void radeon_pm_fini(struct radeon_device *rdev)
|
||||
static void radeon_dpm_print_power_states(struct radeon_device *rdev)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
|
||||
printk("== power state %d ==\n", i);
|
||||
radeon_dpm_print_power_state(rdev, &rdev->pm.dpm.ps[i]);
|
||||
}
|
||||
}
|
||||
|
||||
static int radeon_pm_init_dpm(struct radeon_device *rdev)
|
||||
{
|
||||
int ret;
|
||||
|
||||
/* default to performance state */
|
||||
rdev->pm.dpm.state = POWER_STATE_TYPE_PERFORMANCE;
|
||||
rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE;
|
||||
rdev->pm.default_sclk = rdev->clock.default_sclk;
|
||||
rdev->pm.default_mclk = rdev->clock.default_mclk;
|
||||
rdev->pm.current_sclk = rdev->clock.default_sclk;
|
||||
rdev->pm.current_mclk = rdev->clock.default_mclk;
|
||||
rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
|
||||
|
||||
if (rdev->bios && rdev->is_atom_bios)
|
||||
radeon_atombios_get_power_modes(rdev);
|
||||
else
|
||||
return -EINVAL;
|
||||
|
||||
/* set up the internal thermal sensor if applicable */
|
||||
ret = radeon_hwmon_init(rdev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
INIT_WORK(&rdev->pm.dpm.thermal.work, radeon_dpm_thermal_work_handler);
|
||||
mutex_lock(&rdev->pm.mutex);
|
||||
radeon_dpm_init(rdev);
|
||||
rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
|
||||
radeon_dpm_print_power_states(rdev);
|
||||
radeon_dpm_setup_asic(rdev);
|
||||
ret = radeon_dpm_enable(rdev);
|
||||
mutex_unlock(&rdev->pm.mutex);
|
||||
if (ret) {
|
||||
rdev->pm.dpm_enabled = false;
|
||||
if ((rdev->family >= CHIP_BARTS) &&
|
||||
(rdev->family <= CHIP_CAYMAN) &&
|
||||
rdev->mc_fw) {
|
||||
if (rdev->pm.default_vddc)
|
||||
radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
|
||||
SET_VOLTAGE_TYPE_ASIC_VDDC);
|
||||
if (rdev->pm.default_vddci)
|
||||
radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
|
||||
SET_VOLTAGE_TYPE_ASIC_VDDCI);
|
||||
if (rdev->pm.default_sclk)
|
||||
radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
|
||||
if (rdev->pm.default_mclk)
|
||||
radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
|
||||
}
|
||||
DRM_ERROR("radeon: dpm initialization failed\n");
|
||||
return ret;
|
||||
}
|
||||
rdev->pm.dpm_enabled = true;
|
||||
radeon_pm_compute_clocks(rdev);
|
||||
|
||||
if (rdev->pm.num_power_states > 1) {
|
||||
ret = device_create_file(rdev->dev, &dev_attr_power_dpm_state);
|
||||
if (ret)
|
||||
DRM_ERROR("failed to create device file for dpm state\n");
|
||||
/* XXX: these are noops for dpm but are here for backwards compat */
|
||||
ret = device_create_file(rdev->dev, &dev_attr_power_profile);
|
||||
if (ret)
|
||||
DRM_ERROR("failed to create device file for power profile\n");
|
||||
ret = device_create_file(rdev->dev, &dev_attr_power_method);
|
||||
if (ret)
|
||||
DRM_ERROR("failed to create device file for power method\n");
|
||||
DRM_INFO("radeon: dpm initialized\n");
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int radeon_pm_init(struct radeon_device *rdev)
|
||||
{
|
||||
/* enable dpm on rv6xx+ */
|
||||
switch (rdev->family) {
|
||||
default:
|
||||
/* default to profile method */
|
||||
rdev->pm.pm_method = PM_METHOD_PROFILE;
|
||||
break;
|
||||
}
|
||||
|
||||
if (rdev->pm.pm_method == PM_METHOD_DPM)
|
||||
return radeon_pm_init_dpm(rdev);
|
||||
else
|
||||
return radeon_pm_init_old(rdev);
|
||||
}
|
||||
|
||||
static void radeon_pm_fini_old(struct radeon_device *rdev)
|
||||
{
|
||||
if (rdev->pm.num_power_states > 1) {
|
||||
mutex_lock(&rdev->pm.mutex);
|
||||
|
|
@ -650,7 +1070,35 @@ void radeon_pm_fini(struct radeon_device *rdev)
|
|||
radeon_hwmon_fini(rdev);
|
||||
}
|
||||
|
||||
void radeon_pm_compute_clocks(struct radeon_device *rdev)
|
||||
static void radeon_pm_fini_dpm(struct radeon_device *rdev)
|
||||
{
|
||||
if (rdev->pm.num_power_states > 1) {
|
||||
mutex_lock(&rdev->pm.mutex);
|
||||
radeon_dpm_disable(rdev);
|
||||
mutex_unlock(&rdev->pm.mutex);
|
||||
|
||||
device_remove_file(rdev->dev, &dev_attr_power_dpm_state);
|
||||
/* XXX backwards compat */
|
||||
device_remove_file(rdev->dev, &dev_attr_power_profile);
|
||||
device_remove_file(rdev->dev, &dev_attr_power_method);
|
||||
}
|
||||
radeon_dpm_fini(rdev);
|
||||
|
||||
if (rdev->pm.power_state)
|
||||
kfree(rdev->pm.power_state);
|
||||
|
||||
radeon_hwmon_fini(rdev);
|
||||
}
|
||||
|
||||
void radeon_pm_fini(struct radeon_device *rdev)
|
||||
{
|
||||
if (rdev->pm.pm_method == PM_METHOD_DPM)
|
||||
radeon_pm_fini_dpm(rdev);
|
||||
else
|
||||
radeon_pm_fini_old(rdev);
|
||||
}
|
||||
|
||||
static void radeon_pm_compute_clocks_old(struct radeon_device *rdev)
|
||||
{
|
||||
struct drm_device *ddev = rdev->ddev;
|
||||
struct drm_crtc *crtc;
|
||||
|
|
@ -721,6 +1169,38 @@ void radeon_pm_compute_clocks(struct radeon_device *rdev)
|
|||
mutex_unlock(&rdev->pm.mutex);
|
||||
}
|
||||
|
||||
static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev)
|
||||
{
|
||||
struct drm_device *ddev = rdev->ddev;
|
||||
struct drm_crtc *crtc;
|
||||
struct radeon_crtc *radeon_crtc;
|
||||
|
||||
mutex_lock(&rdev->pm.mutex);
|
||||
|
||||
rdev->pm.dpm.new_active_crtcs = 0;
|
||||
rdev->pm.dpm.new_active_crtc_count = 0;
|
||||
list_for_each_entry(crtc,
|
||||
&ddev->mode_config.crtc_list, head) {
|
||||
radeon_crtc = to_radeon_crtc(crtc);
|
||||
if (crtc->enabled) {
|
||||
rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id);
|
||||
rdev->pm.dpm.new_active_crtc_count++;
|
||||
}
|
||||
}
|
||||
|
||||
radeon_dpm_change_power_state_locked(rdev);
|
||||
|
||||
mutex_unlock(&rdev->pm.mutex);
|
||||
}
|
||||
|
||||
void radeon_pm_compute_clocks(struct radeon_device *rdev)
|
||||
{
|
||||
if (rdev->pm.pm_method == PM_METHOD_DPM)
|
||||
radeon_pm_compute_clocks_dpm(rdev);
|
||||
else
|
||||
radeon_pm_compute_clocks_old(rdev);
|
||||
}
|
||||
|
||||
static bool radeon_pm_in_vbl(struct radeon_device *rdev)
|
||||
{
|
||||
int crtc, vpos, hpos, vbl_status;
|
||||
|
|
|
|||
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