RISC-V: KVM: Document RISC-V specific parts of KVM API
Document RISC-V specific parts of the KVM API, such as:
- The interrupt numbers passed to the KVM_INTERRUPT ioctl.
- The states supported by the KVM_{GET,SET}_MP_STATE ioctls.
- The registers supported by the KVM_{GET,SET}_ONE_REG interface
and the encoding of those register ids.
- The exit reason KVM_EXIT_RISCV_SBI for SBI calls forwarded to
userspace tool.
CC: Jonathan Corbet <corbet@lwn.net>
CC: linux-doc@vger.kernel.org
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
This commit is contained in:
Anup Patel
Anup Patel
Родитель
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Коммит
da40d85805
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@ -532,7 +532,7 @@ translation mode.
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------------------
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:Capability: basic
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:Architectures: x86, ppc, mips
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:Architectures: x86, ppc, mips, riscv
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:Type: vcpu ioctl
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:Parameters: struct kvm_interrupt (in)
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:Returns: 0 on success, negative on failure.
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@ -601,6 +601,23 @@ interrupt number dequeues the interrupt.
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This is an asynchronous vcpu ioctl and can be invoked from any thread.
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RISC-V:
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^^^^^^^
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Queues an external interrupt to be injected into the virutal CPU. This ioctl
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is overloaded with 2 different irq values:
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a) KVM_INTERRUPT_SET
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This sets external interrupt for a virtual CPU and it will receive
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once it is ready.
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b) KVM_INTERRUPT_UNSET
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This clears pending external interrupt for a virtual CPU.
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This is an asynchronous vcpu ioctl and can be invoked from any thread.
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4.17 KVM_DEBUG_GUEST
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--------------------
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@ -1399,7 +1416,7 @@ for vm-wide capabilities.
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---------------------
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:Capability: KVM_CAP_MP_STATE
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:Architectures: x86, s390, arm, arm64
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:Architectures: x86, s390, arm, arm64, riscv
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:Type: vcpu ioctl
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:Parameters: struct kvm_mp_state (out)
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:Returns: 0 on success; -1 on error
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@ -1416,7 +1433,8 @@ uniprocessor guests).
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Possible values are:
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========================== ===============================================
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KVM_MP_STATE_RUNNABLE the vcpu is currently running [x86,arm/arm64]
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KVM_MP_STATE_RUNNABLE the vcpu is currently running
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[x86,arm/arm64,riscv]
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KVM_MP_STATE_UNINITIALIZED the vcpu is an application processor (AP)
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which has not yet received an INIT signal [x86]
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KVM_MP_STATE_INIT_RECEIVED the vcpu has received an INIT signal, and is
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@ -1425,7 +1443,7 @@ Possible values are:
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is waiting for an interrupt [x86]
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KVM_MP_STATE_SIPI_RECEIVED the vcpu has just received a SIPI (vector
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accessible via KVM_GET_VCPU_EVENTS) [x86]
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KVM_MP_STATE_STOPPED the vcpu is stopped [s390,arm/arm64]
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KVM_MP_STATE_STOPPED the vcpu is stopped [s390,arm/arm64,riscv]
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KVM_MP_STATE_CHECK_STOP the vcpu is in a special error state [s390]
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KVM_MP_STATE_OPERATING the vcpu is operating (running or halted)
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[s390]
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@ -1437,8 +1455,8 @@ On x86, this ioctl is only useful after KVM_CREATE_IRQCHIP. Without an
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in-kernel irqchip, the multiprocessing state must be maintained by userspace on
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these architectures.
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For arm/arm64:
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^^^^^^^^^^^^^^
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For arm/arm64/riscv:
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^^^^^^^^^^^^^^^^^^^^
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The only states that are valid are KVM_MP_STATE_STOPPED and
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KVM_MP_STATE_RUNNABLE which reflect if the vcpu is paused or not.
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@ -1447,7 +1465,7 @@ KVM_MP_STATE_RUNNABLE which reflect if the vcpu is paused or not.
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---------------------
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:Capability: KVM_CAP_MP_STATE
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:Architectures: x86, s390, arm, arm64
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:Architectures: x86, s390, arm, arm64, riscv
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:Type: vcpu ioctl
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:Parameters: struct kvm_mp_state (in)
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:Returns: 0 on success; -1 on error
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@ -1459,8 +1477,8 @@ On x86, this ioctl is only useful after KVM_CREATE_IRQCHIP. Without an
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in-kernel irqchip, the multiprocessing state must be maintained by userspace on
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these architectures.
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For arm/arm64:
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^^^^^^^^^^^^^^
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For arm/arm64/riscv:
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^^^^^^^^^^^^^^^^^^^^
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The only states that are valid are KVM_MP_STATE_STOPPED and
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KVM_MP_STATE_RUNNABLE which reflect if the vcpu should be paused or not.
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@ -2577,6 +2595,144 @@ following id bit patterns::
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0x7020 0000 0003 02 <0:3> <reg:5>
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RISC-V registers are mapped using the lower 32 bits. The upper 8 bits of
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that is the register group type.
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RISC-V config registers are meant for configuring a Guest VCPU and it has
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the following id bit patterns::
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0x8020 0000 01 <index into the kvm_riscv_config struct:24> (32bit Host)
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0x8030 0000 01 <index into the kvm_riscv_config struct:24> (64bit Host)
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Following are the RISC-V config registers:
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======================= ========= =============================================
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Encoding Register Description
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======================= ========= =============================================
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0x80x0 0000 0100 0000 isa ISA feature bitmap of Guest VCPU
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======================= ========= =============================================
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The isa config register can be read anytime but can only be written before
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a Guest VCPU runs. It will have ISA feature bits matching underlying host
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set by default.
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RISC-V core registers represent the general excution state of a Guest VCPU
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and it has the following id bit patterns::
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0x8020 0000 02 <index into the kvm_riscv_core struct:24> (32bit Host)
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0x8030 0000 02 <index into the kvm_riscv_core struct:24> (64bit Host)
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Following are the RISC-V core registers:
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======================= ========= =============================================
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Encoding Register Description
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======================= ========= =============================================
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0x80x0 0000 0200 0000 regs.pc Program counter
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0x80x0 0000 0200 0001 regs.ra Return address
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0x80x0 0000 0200 0002 regs.sp Stack pointer
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0x80x0 0000 0200 0003 regs.gp Global pointer
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0x80x0 0000 0200 0004 regs.tp Task pointer
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0x80x0 0000 0200 0005 regs.t0 Caller saved register 0
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0x80x0 0000 0200 0006 regs.t1 Caller saved register 1
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0x80x0 0000 0200 0007 regs.t2 Caller saved register 2
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0x80x0 0000 0200 0008 regs.s0 Callee saved register 0
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0x80x0 0000 0200 0009 regs.s1 Callee saved register 1
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0x80x0 0000 0200 000a regs.a0 Function argument (or return value) 0
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0x80x0 0000 0200 000b regs.a1 Function argument (or return value) 1
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0x80x0 0000 0200 000c regs.a2 Function argument 2
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0x80x0 0000 0200 000d regs.a3 Function argument 3
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0x80x0 0000 0200 000e regs.a4 Function argument 4
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0x80x0 0000 0200 000f regs.a5 Function argument 5
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0x80x0 0000 0200 0010 regs.a6 Function argument 6
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0x80x0 0000 0200 0011 regs.a7 Function argument 7
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0x80x0 0000 0200 0012 regs.s2 Callee saved register 2
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0x80x0 0000 0200 0013 regs.s3 Callee saved register 3
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0x80x0 0000 0200 0014 regs.s4 Callee saved register 4
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0x80x0 0000 0200 0015 regs.s5 Callee saved register 5
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0x80x0 0000 0200 0016 regs.s6 Callee saved register 6
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0x80x0 0000 0200 0017 regs.s7 Callee saved register 7
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0x80x0 0000 0200 0018 regs.s8 Callee saved register 8
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0x80x0 0000 0200 0019 regs.s9 Callee saved register 9
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0x80x0 0000 0200 001a regs.s10 Callee saved register 10
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0x80x0 0000 0200 001b regs.s11 Callee saved register 11
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0x80x0 0000 0200 001c regs.t3 Caller saved register 3
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0x80x0 0000 0200 001d regs.t4 Caller saved register 4
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0x80x0 0000 0200 001e regs.t5 Caller saved register 5
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0x80x0 0000 0200 001f regs.t6 Caller saved register 6
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0x80x0 0000 0200 0020 mode Privilege mode (1 = S-mode or 0 = U-mode)
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======================= ========= =============================================
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RISC-V csr registers represent the supervisor mode control/status registers
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of a Guest VCPU and it has the following id bit patterns::
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0x8020 0000 03 <index into the kvm_riscv_csr struct:24> (32bit Host)
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0x8030 0000 03 <index into the kvm_riscv_csr struct:24> (64bit Host)
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Following are the RISC-V csr registers:
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======================= ========= =============================================
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Encoding Register Description
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======================= ========= =============================================
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0x80x0 0000 0300 0000 sstatus Supervisor status
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0x80x0 0000 0300 0001 sie Supervisor interrupt enable
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0x80x0 0000 0300 0002 stvec Supervisor trap vector base
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0x80x0 0000 0300 0003 sscratch Supervisor scratch register
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0x80x0 0000 0300 0004 sepc Supervisor exception program counter
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0x80x0 0000 0300 0005 scause Supervisor trap cause
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0x80x0 0000 0300 0006 stval Supervisor bad address or instruction
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0x80x0 0000 0300 0007 sip Supervisor interrupt pending
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0x80x0 0000 0300 0008 satp Supervisor address translation and protection
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======================= ========= =============================================
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RISC-V timer registers represent the timer state of a Guest VCPU and it has
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the following id bit patterns::
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0x8030 0000 04 <index into the kvm_riscv_timer struct:24>
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Following are the RISC-V timer registers:
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======================= ========= =============================================
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Encoding Register Description
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======================= ========= =============================================
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0x8030 0000 0400 0000 frequency Time base frequency (read-only)
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0x8030 0000 0400 0001 time Time value visible to Guest
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0x8030 0000 0400 0002 compare Time compare programmed by Guest
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0x8030 0000 0400 0003 state Time compare state (1 = ON or 0 = OFF)
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======================= ========= =============================================
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RISC-V F-extension registers represent the single precision floating point
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state of a Guest VCPU and it has the following id bit patterns::
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0x8020 0000 05 <index into the __riscv_f_ext_state struct:24>
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Following are the RISC-V F-extension registers:
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======================= ========= =============================================
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Encoding Register Description
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======================= ========= =============================================
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0x8020 0000 0500 0000 f[0] Floating point register 0
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...
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0x8020 0000 0500 001f f[31] Floating point register 31
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0x8020 0000 0500 0020 fcsr Floating point control and status register
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======================= ========= =============================================
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RISC-V D-extension registers represent the double precision floating point
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state of a Guest VCPU and it has the following id bit patterns::
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0x8020 0000 06 <index into the __riscv_d_ext_state struct:24> (fcsr)
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0x8030 0000 06 <index into the __riscv_d_ext_state struct:24> (non-fcsr)
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Following are the RISC-V D-extension registers:
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======================= ========= =============================================
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Encoding Register Description
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======================= ========= =============================================
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0x8030 0000 0600 0000 f[0] Floating point register 0
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...
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0x8030 0000 0600 001f f[31] Floating point register 31
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0x8020 0000 0600 0020 fcsr Floating point control and status register
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======================= ========= =============================================
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4.69 KVM_GET_ONE_REG
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--------------------
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@ -5848,6 +6004,25 @@ Valid values for 'type' are:
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Userspace is expected to place the hypercall result into the appropriate
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field before invoking KVM_RUN again.
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::
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/* KVM_EXIT_RISCV_SBI */
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struct {
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unsigned long extension_id;
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unsigned long function_id;
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unsigned long args[6];
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unsigned long ret[2];
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} riscv_sbi;
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If exit reason is KVM_EXIT_RISCV_SBI then it indicates that the VCPU has
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done a SBI call which is not handled by KVM RISC-V kernel module. The details
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of the SBI call are available in 'riscv_sbi' member of kvm_run structure. The
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'extension_id' field of 'riscv_sbi' represents SBI extension ID whereas the
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'function_id' field represents function ID of given SBI extension. The 'args'
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array field of 'riscv_sbi' represents parameters for the SBI call and 'ret'
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array field represents return values. The userspace should update the return
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values of SBI call before resuming the VCPU. For more details on RISC-V SBI
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spec refer, https://github.com/riscv/riscv-sbi-doc.
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::
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/* Fix the size of the union. */
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