staging: comedi: me4000: tidy up ME4000_AI_CTRL_REG bit defines
Use the BIT() marco to define the bits of this register. For aesthetics, rename all the defines to remove the '_BIT' from the name. Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Reviewed-by: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
H Hartley Sweeten
Greg Kroah-Hartman
Родитель
a9b586a52a
Коммит
da772ad9a8
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@ -78,28 +78,28 @@ broken.
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#define ME4000_AO_TIMER_REG(x) (0x10 + ME4000_AO_CHAN(x))
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#define ME4000_AI_CTRL_REG 0x74
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#define ME4000_AI_STATUS_REG 0x74
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#define ME4000_AI_CTRL_BIT_MODE_0 (1 << 0)
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#define ME4000_AI_CTRL_BIT_MODE_1 (1 << 1)
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#define ME4000_AI_CTRL_BIT_MODE_2 (1 << 2)
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#define ME4000_AI_CTRL_BIT_SAMPLE_HOLD (1 << 3)
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#define ME4000_AI_CTRL_BIT_IMMEDIATE_STOP (1 << 4)
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#define ME4000_AI_CTRL_BIT_STOP (1 << 5)
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#define ME4000_AI_CTRL_BIT_CHANNEL_FIFO (1 << 6)
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#define ME4000_AI_CTRL_BIT_DATA_FIFO (1 << 7)
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#define ME4000_AI_CTRL_BIT_FULLSCALE (1 << 8)
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#define ME4000_AI_CTRL_BIT_OFFSET (1 << 9)
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#define ME4000_AI_CTRL_BIT_EX_TRIG_ANALOG (1 << 10)
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#define ME4000_AI_CTRL_BIT_EX_TRIG (1 << 11)
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#define ME4000_AI_CTRL_BIT_EX_TRIG_FALLING (1 << 12)
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#define ME4000_AI_CTRL_BIT_EX_IRQ (1 << 13)
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#define ME4000_AI_CTRL_BIT_EX_IRQ_RESET (1 << 14)
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#define ME4000_AI_CTRL_BIT_LE_IRQ (1 << 15)
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#define ME4000_AI_CTRL_BIT_LE_IRQ_RESET (1 << 16)
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#define ME4000_AI_CTRL_BIT_HF_IRQ (1 << 17)
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#define ME4000_AI_CTRL_BIT_HF_IRQ_RESET (1 << 18)
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#define ME4000_AI_CTRL_BIT_SC_IRQ (1 << 19)
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#define ME4000_AI_CTRL_BIT_SC_IRQ_RESET (1 << 20)
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#define ME4000_AI_CTRL_BIT_SC_RELOAD (1 << 21)
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#define ME4000_AI_CTRL_MODE_0 BIT(0)
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#define ME4000_AI_CTRL_MODE_1 BIT(1)
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#define ME4000_AI_CTRL_MODE_2 BIT(2)
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#define ME4000_AI_CTRL_SAMPLE_HOLD BIT(3)
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#define ME4000_AI_CTRL_IMMEDIATE_STOP BIT(4)
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#define ME4000_AI_CTRL_STOP BIT(5)
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#define ME4000_AI_CTRL_CHANNEL_FIFO BIT(6)
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#define ME4000_AI_CTRL_DATA_FIFO BIT(7)
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#define ME4000_AI_CTRL_FULLSCALE BIT(8)
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#define ME4000_AI_CTRL_OFFSET BIT(9)
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#define ME4000_AI_CTRL_EX_TRIG_ANALOG BIT(10)
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#define ME4000_AI_CTRL_EX_TRIG BIT(11)
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#define ME4000_AI_CTRL_EX_TRIG_FALLING BIT(12)
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#define ME4000_AI_CTRL_EX_IRQ BIT(13)
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#define ME4000_AI_CTRL_EX_IRQ_RESET BIT(14)
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#define ME4000_AI_CTRL_LE_IRQ BIT(15)
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#define ME4000_AI_CTRL_LE_IRQ_RESET BIT(16)
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#define ME4000_AI_CTRL_HF_IRQ BIT(17)
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#define ME4000_AI_CTRL_HF_IRQ_RESET BIT(18)
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#define ME4000_AI_CTRL_SC_IRQ BIT(19)
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#define ME4000_AI_CTRL_SC_IRQ_RESET BIT(20)
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#define ME4000_AI_CTRL_SC_RELOAD BIT(21)
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#define ME4000_AI_STATUS_EF_CHANNEL BIT(22)
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#define ME4000_AI_STATUS_HF_CHANNEL BIT(23)
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#define ME4000_AI_STATUS_FF_CHANNEL BIT(24)
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@ -108,7 +108,7 @@ broken.
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#define ME4000_AI_STATUS_FF_DATA BIT(27)
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#define ME4000_AI_STATUS_LE BIT(28)
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#define ME4000_AI_STATUS_FSM BIT(29)
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#define ME4000_AI_CTRL_BIT_EX_TRIG_BOTH (1 << 31)
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#define ME4000_AI_CTRL_EX_TRIG_BOTH BIT(31)
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#define ME4000_AI_CHANNEL_LIST_REG 0x78
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#define ME4000_AI_LIST_INPUT_DIFFERENTIAL BIT(5)
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#define ME4000_AI_LIST_RANGE(x) ((3 - ((x) & 3)) << 6)
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@ -408,7 +408,7 @@ static void me4000_reset(struct comedi_device *dev)
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outl(0x8000, dev->iobase + ME4000_AO_SINGLE_REG(chan));
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/* Set both stop bits in the analog input control register */
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outl(ME4000_AI_CTRL_BIT_IMMEDIATE_STOP | ME4000_AI_CTRL_BIT_STOP,
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outl(ME4000_AI_CTRL_IMMEDIATE_STOP | ME4000_AI_CTRL_STOP,
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dev->iobase + ME4000_AI_CTRL_REG);
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/* Set both stop bits in the analog output control register */
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@ -485,18 +485,17 @@ static int me4000_ai_insn_read(struct comedi_device *dev,
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/* Clear channel list, data fifo and both stop bits */
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tmp = inl(dev->iobase + ME4000_AI_CTRL_REG);
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tmp &= ~(ME4000_AI_CTRL_BIT_CHANNEL_FIFO |
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ME4000_AI_CTRL_BIT_DATA_FIFO |
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ME4000_AI_CTRL_BIT_STOP | ME4000_AI_CTRL_BIT_IMMEDIATE_STOP);
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tmp &= ~(ME4000_AI_CTRL_CHANNEL_FIFO | ME4000_AI_CTRL_DATA_FIFO |
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ME4000_AI_CTRL_STOP | ME4000_AI_CTRL_IMMEDIATE_STOP);
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outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
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/* Set the acquisition mode to single */
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tmp &= ~(ME4000_AI_CTRL_BIT_MODE_0 | ME4000_AI_CTRL_BIT_MODE_1 |
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ME4000_AI_CTRL_BIT_MODE_2);
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tmp &= ~(ME4000_AI_CTRL_MODE_0 | ME4000_AI_CTRL_MODE_1 |
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ME4000_AI_CTRL_MODE_2);
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outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
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/* Enable channel list and data fifo */
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tmp |= ME4000_AI_CTRL_BIT_CHANNEL_FIFO | ME4000_AI_CTRL_BIT_DATA_FIFO;
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tmp |= ME4000_AI_CTRL_CHANNEL_FIFO | ME4000_AI_CTRL_DATA_FIFO;
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outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
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/* Generate channel list entry */
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@ -531,7 +530,7 @@ static int me4000_ai_cancel(struct comedi_device *dev,
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/* Stop any running conversion */
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tmp = inl(dev->iobase + ME4000_AI_CTRL_REG);
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tmp &= ~(ME4000_AI_CTRL_BIT_STOP | ME4000_AI_CTRL_BIT_IMMEDIATE_STOP);
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tmp &= ~(ME4000_AI_CTRL_STOP | ME4000_AI_CTRL_IMMEDIATE_STOP);
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outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
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/* Clear the control register */
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@ -699,40 +698,40 @@ static int ai_prepare(struct comedi_device *dev,
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(cmd->start_src == TRIG_EXT &&
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cmd->scan_begin_src == TRIG_FOLLOW &&
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cmd->convert_src == TRIG_TIMER)) {
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tmp = ME4000_AI_CTRL_BIT_MODE_1 |
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ME4000_AI_CTRL_BIT_CHANNEL_FIFO |
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ME4000_AI_CTRL_BIT_DATA_FIFO;
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tmp = ME4000_AI_CTRL_MODE_1 |
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ME4000_AI_CTRL_CHANNEL_FIFO |
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ME4000_AI_CTRL_DATA_FIFO;
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} else if (cmd->start_src == TRIG_EXT &&
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cmd->scan_begin_src == TRIG_EXT &&
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cmd->convert_src == TRIG_TIMER) {
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tmp = ME4000_AI_CTRL_BIT_MODE_2 |
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ME4000_AI_CTRL_BIT_CHANNEL_FIFO |
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ME4000_AI_CTRL_BIT_DATA_FIFO;
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tmp = ME4000_AI_CTRL_MODE_2 |
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ME4000_AI_CTRL_CHANNEL_FIFO |
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ME4000_AI_CTRL_DATA_FIFO;
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} else if (cmd->start_src == TRIG_EXT &&
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cmd->scan_begin_src == TRIG_EXT &&
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cmd->convert_src == TRIG_EXT) {
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tmp = ME4000_AI_CTRL_BIT_MODE_0 |
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ME4000_AI_CTRL_BIT_MODE_1 |
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ME4000_AI_CTRL_BIT_CHANNEL_FIFO |
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ME4000_AI_CTRL_BIT_DATA_FIFO;
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tmp = ME4000_AI_CTRL_MODE_0 |
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ME4000_AI_CTRL_MODE_1 |
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ME4000_AI_CTRL_CHANNEL_FIFO |
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ME4000_AI_CTRL_DATA_FIFO;
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} else {
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tmp = ME4000_AI_CTRL_BIT_MODE_0 |
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ME4000_AI_CTRL_BIT_CHANNEL_FIFO |
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ME4000_AI_CTRL_BIT_DATA_FIFO;
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tmp = ME4000_AI_CTRL_MODE_0 |
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ME4000_AI_CTRL_CHANNEL_FIFO |
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ME4000_AI_CTRL_DATA_FIFO;
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}
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/* Stop triggers */
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if (cmd->stop_src == TRIG_COUNT) {
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outl(cmd->chanlist_len * cmd->stop_arg,
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dev->iobase + ME4000_AI_SAMPLE_COUNTER_REG);
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tmp |= ME4000_AI_CTRL_BIT_HF_IRQ | ME4000_AI_CTRL_BIT_SC_IRQ;
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tmp |= ME4000_AI_CTRL_HF_IRQ | ME4000_AI_CTRL_SC_IRQ;
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} else if (cmd->stop_src == TRIG_NONE &&
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cmd->scan_end_src == TRIG_COUNT) {
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outl(cmd->scan_end_arg,
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dev->iobase + ME4000_AI_SAMPLE_COUNTER_REG);
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tmp |= ME4000_AI_CTRL_BIT_HF_IRQ | ME4000_AI_CTRL_BIT_SC_IRQ;
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tmp |= ME4000_AI_CTRL_HF_IRQ | ME4000_AI_CTRL_SC_IRQ;
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} else {
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tmp |= ME4000_AI_CTRL_BIT_HF_IRQ;
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tmp |= ME4000_AI_CTRL_HF_IRQ;
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}
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/* Write the setup to the control register */
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@ -1009,9 +1008,9 @@ static irqreturn_t me4000_ai_isr(int irq, void *dev_id)
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* FIFO overflow, so stop conversion
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* and disable all interrupts
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*/
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tmp |= ME4000_AI_CTRL_BIT_IMMEDIATE_STOP;
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tmp &= ~(ME4000_AI_CTRL_BIT_HF_IRQ |
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ME4000_AI_CTRL_BIT_SC_IRQ);
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tmp |= ME4000_AI_CTRL_IMMEDIATE_STOP;
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tmp &= ~(ME4000_AI_CTRL_HF_IRQ |
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ME4000_AI_CTRL_SC_IRQ);
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outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
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s->async->events |= COMEDI_CB_ERROR;
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@ -1030,9 +1029,9 @@ static irqreturn_t me4000_ai_isr(int irq, void *dev_id)
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* Undefined state, so stop conversion
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* and disable all interrupts
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*/
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tmp |= ME4000_AI_CTRL_BIT_IMMEDIATE_STOP;
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tmp &= ~(ME4000_AI_CTRL_BIT_HF_IRQ |
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ME4000_AI_CTRL_BIT_SC_IRQ);
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tmp |= ME4000_AI_CTRL_IMMEDIATE_STOP;
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tmp &= ~(ME4000_AI_CTRL_HF_IRQ |
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ME4000_AI_CTRL_SC_IRQ);
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outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
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s->async->events |= COMEDI_CB_ERROR;
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@ -1050,18 +1049,18 @@ static irqreturn_t me4000_ai_isr(int irq, void *dev_id)
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* Buffer overflow, so stop conversion
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* and disable all interrupts
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*/
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tmp |= ME4000_AI_CTRL_BIT_IMMEDIATE_STOP;
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tmp &= ~(ME4000_AI_CTRL_BIT_HF_IRQ |
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ME4000_AI_CTRL_BIT_SC_IRQ);
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tmp |= ME4000_AI_CTRL_IMMEDIATE_STOP;
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tmp &= ~(ME4000_AI_CTRL_HF_IRQ |
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ME4000_AI_CTRL_SC_IRQ);
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outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
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break;
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}
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}
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/* Work is done, so reset the interrupt */
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tmp |= ME4000_AI_CTRL_BIT_HF_IRQ_RESET;
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tmp |= ME4000_AI_CTRL_HF_IRQ_RESET;
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outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
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tmp &= ~ME4000_AI_CTRL_BIT_HF_IRQ_RESET;
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tmp &= ~ME4000_AI_CTRL_HF_IRQ_RESET;
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outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
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}
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@ -1074,8 +1073,8 @@ static irqreturn_t me4000_ai_isr(int irq, void *dev_id)
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* conversion and disable all interrupts
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*/
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tmp = inl(dev->iobase + ME4000_AI_CTRL_REG);
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tmp |= ME4000_AI_CTRL_BIT_IMMEDIATE_STOP;
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tmp &= ~(ME4000_AI_CTRL_BIT_HF_IRQ | ME4000_AI_CTRL_BIT_SC_IRQ);
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tmp |= ME4000_AI_CTRL_IMMEDIATE_STOP;
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tmp &= ~(ME4000_AI_CTRL_HF_IRQ | ME4000_AI_CTRL_SC_IRQ);
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outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
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/* Poll data until fifo empty */
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@ -1090,9 +1089,9 @@ static irqreturn_t me4000_ai_isr(int irq, void *dev_id)
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}
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/* Work is done, so reset the interrupt */
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tmp |= ME4000_AI_CTRL_BIT_SC_IRQ_RESET;
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tmp |= ME4000_AI_CTRL_SC_IRQ_RESET;
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outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
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tmp &= ~ME4000_AI_CTRL_BIT_SC_IRQ_RESET;
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tmp &= ~ME4000_AI_CTRL_SC_IRQ_RESET;
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outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
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}
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