ARM: 7013/1: P2V: Remove ARM_PATCH_PHYS_VIRT_16BIT
This code can be removed now that MSM targets no longer need the 16-bit offsets for P2V. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Nicolas Pitre
Russell King
Родитель
9e775ad19f
Коммит
daece59689
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@ -205,20 +205,12 @@ config ARM_PATCH_PHYS_VIRT
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kernel in system memory.
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This can only be used with non-XIP MMU kernels where the base
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of physical memory is at a 16MB boundary, or theoretically 64K
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for the MSM machine class.
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of physical memory is at a 16MB boundary.
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Only disable this option if you know that you do not require
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this feature (eg, building a kernel for a single machine) and
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you need to shrink the kernel to the minimal size.
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config ARM_PATCH_PHYS_VIRT_16BIT
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def_bool y
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depends on ARM_PATCH_PHYS_VIRT && ARCH_MSM
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help
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This option extends the physical to virtual translation patching
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to allow physical memory down to a theoretical minimum of 64K
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boundaries.
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source "init/Kconfig"
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@ -160,7 +160,6 @@
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* so that all we need to do is modify the 8-bit constant field.
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*/
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#define __PV_BITS_31_24 0x81000000
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#define __PV_BITS_23_16 0x00810000
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extern unsigned long __pv_phys_offset;
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#define PHYS_OFFSET __pv_phys_offset
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@ -178,9 +177,6 @@ static inline unsigned long __virt_to_phys(unsigned long x)
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{
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unsigned long t;
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__pv_stub(x, t, "add", __PV_BITS_31_24);
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#ifdef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT
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__pv_stub(t, t, "add", __PV_BITS_23_16);
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#endif
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return t;
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}
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@ -188,9 +184,6 @@ static inline unsigned long __phys_to_virt(unsigned long x)
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{
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unsigned long t;
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__pv_stub(x, t, "sub", __PV_BITS_31_24);
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#ifdef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT
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__pv_stub(t, t, "sub", __PV_BITS_23_16);
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#endif
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return t;
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}
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#else
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@ -31,11 +31,7 @@ struct mod_arch_specific {
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/* Add __virt_to_phys patching state as well */
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#ifdef CONFIG_ARM_PATCH_PHYS_VIRT
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#ifdef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT
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#define MODULE_ARCH_VERMAGIC_P2V "p2v16 "
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#else
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#define MODULE_ARCH_VERMAGIC_P2V "p2v8 "
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#endif
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#else
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#define MODULE_ARCH_VERMAGIC_P2V ""
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#endif
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@ -488,13 +488,8 @@ __fixup_pv_table:
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add r5, r5, r3 @ adjust table end address
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add r7, r7, r3 @ adjust __pv_phys_offset address
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str r8, [r7] @ save computed PHYS_OFFSET to __pv_phys_offset
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#ifndef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT
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mov r6, r3, lsr #24 @ constant for add/sub instructions
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teq r3, r6, lsl #24 @ must be 16MiB aligned
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#else
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mov r6, r3, lsr #16 @ constant for add/sub instructions
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teq r3, r6, lsl #16 @ must be 64kiB aligned
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#endif
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THUMB( it ne @ cross section branch )
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bne __error
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str r6, [r7, #4] @ save to __pv_offset
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@ -510,20 +505,8 @@ ENDPROC(__fixup_pv_table)
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.text
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__fixup_a_pv_table:
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#ifdef CONFIG_THUMB2_KERNEL
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#ifdef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT
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lsls r0, r6, #24
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lsr r6, #8
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beq 1f
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clz r7, r0
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lsr r0, #24
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lsl r0, r7
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bic r0, 0x0080
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lsrs r7, #1
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orrcs r0, #0x0080
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orr r0, r0, r7, lsl #12
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#endif
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1: lsls r6, #24
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beq 4f
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lsls r6, #24
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beq 2f
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clz r7, r6
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lsr r6, #24
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lsl r6, r7
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@ -532,43 +515,25 @@ __fixup_a_pv_table:
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orrcs r6, #0x0080
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orr r6, r6, r7, lsl #12
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orr r6, #0x4000
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b 4f
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2: @ at this point the C flag is always clear
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add r7, r3
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#ifdef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT
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ldrh ip, [r7]
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tst ip, 0x0400 @ the i bit tells us LS or MS byte
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beq 3f
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cmp r0, #0 @ set C flag, and ...
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biceq ip, 0x0400 @ immediate zero value has a special encoding
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streqh ip, [r7] @ that requires the i bit cleared
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#endif
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3: ldrh ip, [r7, #2]
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b 2f
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1: add r7, r3
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ldrh ip, [r7, #2]
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and ip, 0x8f00
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orrcc ip, r6 @ mask in offset bits 31-24
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orrcs ip, r0 @ mask in offset bits 23-16
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orr ip, r6 @ mask in offset bits 31-24
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strh ip, [r7, #2]
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4: cmp r4, r5
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2: cmp r4, r5
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ldrcc r7, [r4], #4 @ use branch for delay slot
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bcc 2b
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bcc 1b
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bx lr
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#else
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#ifdef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT
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and r0, r6, #255 @ offset bits 23-16
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mov r6, r6, lsr #8 @ offset bits 31-24
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#else
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mov r0, #0 @ just in case...
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#endif
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b 3f
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2: ldr ip, [r7, r3]
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b 2f
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1: ldr ip, [r7, r3]
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bic ip, ip, #0x000000ff
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tst ip, #0x400 @ rotate shift tells us LS or MS byte
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orrne ip, ip, r6 @ mask in offset bits 31-24
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orreq ip, ip, r0 @ mask in offset bits 23-16
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orr ip, ip, r6 @ mask in offset bits 31-24
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str ip, [r7, r3]
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3: cmp r4, r5
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2: cmp r4, r5
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ldrcc r7, [r4], #4 @ use branch for delay slot
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bcc 2b
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bcc 1b
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mov pc, lr
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#endif
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ENDPROC(__fixup_a_pv_table)
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