netdev: driver: ethernet: add cpsw address lookup engine support
TI CPSW ethernet switch has a built-in address lookup engine. This patch adds the code necessary for programming this module. Signed-off-by: Cyril Chemparathy <cyril@ti.com> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Mugunthan V N
David S. Miller
Родитель
49099122a4
Коммит
db82173f23
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@ -0,0 +1,641 @@
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/*
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* Texas Instruments 3-Port Ethernet Switch Address Lookup Engine
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*
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* Copyright (C) 2012 Texas Instruments
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/platform_device.h>
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#include <linux/seq_file.h>
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#include <linux/slab.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/stat.h>
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#include <linux/sysfs.h>
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#include "cpsw_ale.h"
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#define BITMASK(bits) (BIT(bits) - 1)
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#define ALE_ENTRY_BITS 68
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#define ALE_ENTRY_WORDS DIV_ROUND_UP(ALE_ENTRY_BITS, 32)
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#define ALE_VERSION_MAJOR(rev) ((rev >> 8) & 0xff)
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#define ALE_VERSION_MINOR(rev) (rev & 0xff)
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/* ALE Registers */
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#define ALE_IDVER 0x00
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#define ALE_CONTROL 0x08
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#define ALE_PRESCALE 0x10
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#define ALE_UNKNOWNVLAN 0x18
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#define ALE_TABLE_CONTROL 0x20
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#define ALE_TABLE 0x34
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#define ALE_PORTCTL 0x40
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#define ALE_TABLE_WRITE BIT(31)
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#define ALE_TYPE_FREE 0
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#define ALE_TYPE_ADDR 1
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#define ALE_TYPE_VLAN 2
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#define ALE_TYPE_VLAN_ADDR 3
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#define ALE_UCAST_PERSISTANT 0
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#define ALE_UCAST_UNTOUCHED 1
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#define ALE_UCAST_OUI 2
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#define ALE_UCAST_TOUCHED 3
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static inline int cpsw_ale_get_field(u32 *ale_entry, u32 start, u32 bits)
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{
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int idx;
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idx = start / 32;
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start -= idx * 32;
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idx = 2 - idx; /* flip */
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return (ale_entry[idx] >> start) & BITMASK(bits);
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}
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static inline void cpsw_ale_set_field(u32 *ale_entry, u32 start, u32 bits,
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u32 value)
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{
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int idx;
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value &= BITMASK(bits);
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idx = start / 32;
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start -= idx * 32;
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idx = 2 - idx; /* flip */
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ale_entry[idx] &= ~(BITMASK(bits) << start);
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ale_entry[idx] |= (value << start);
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}
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#define DEFINE_ALE_FIELD(name, start, bits) \
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static inline int cpsw_ale_get_##name(u32 *ale_entry) \
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{ \
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return cpsw_ale_get_field(ale_entry, start, bits); \
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} \
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static inline void cpsw_ale_set_##name(u32 *ale_entry, u32 value) \
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{ \
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cpsw_ale_set_field(ale_entry, start, bits, value); \
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}
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DEFINE_ALE_FIELD(entry_type, 60, 2)
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DEFINE_ALE_FIELD(vlan_id, 48, 12)
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DEFINE_ALE_FIELD(mcast_state, 62, 2)
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DEFINE_ALE_FIELD(port_mask, 66, 3)
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DEFINE_ALE_FIELD(super, 65, 1)
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DEFINE_ALE_FIELD(ucast_type, 62, 2)
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DEFINE_ALE_FIELD(port_num, 66, 2)
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DEFINE_ALE_FIELD(blocked, 65, 1)
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DEFINE_ALE_FIELD(secure, 64, 1)
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DEFINE_ALE_FIELD(vlan_untag_force, 24, 3)
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DEFINE_ALE_FIELD(vlan_reg_mcast, 16, 3)
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DEFINE_ALE_FIELD(vlan_unreg_mcast, 8, 3)
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DEFINE_ALE_FIELD(vlan_member_list, 0, 3)
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DEFINE_ALE_FIELD(mcast, 40, 1)
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/* The MAC address field in the ALE entry cannot be macroized as above */
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static inline void cpsw_ale_get_addr(u32 *ale_entry, u8 *addr)
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{
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int i;
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for (i = 0; i < 6; i++)
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addr[i] = cpsw_ale_get_field(ale_entry, 40 - 8*i, 8);
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}
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static inline void cpsw_ale_set_addr(u32 *ale_entry, u8 *addr)
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{
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int i;
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for (i = 0; i < 6; i++)
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cpsw_ale_set_field(ale_entry, 40 - 8*i, 8, addr[i]);
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}
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static int cpsw_ale_read(struct cpsw_ale *ale, int idx, u32 *ale_entry)
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{
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int i;
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WARN_ON(idx > ale->params.ale_entries);
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__raw_writel(idx, ale->params.ale_regs + ALE_TABLE_CONTROL);
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for (i = 0; i < ALE_ENTRY_WORDS; i++)
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ale_entry[i] = __raw_readl(ale->params.ale_regs +
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ALE_TABLE + 4 * i);
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return idx;
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}
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static int cpsw_ale_write(struct cpsw_ale *ale, int idx, u32 *ale_entry)
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{
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int i;
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WARN_ON(idx > ale->params.ale_entries);
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for (i = 0; i < ALE_ENTRY_WORDS; i++)
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__raw_writel(ale_entry[i], ale->params.ale_regs +
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ALE_TABLE + 4 * i);
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__raw_writel(idx | ALE_TABLE_WRITE, ale->params.ale_regs +
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ALE_TABLE_CONTROL);
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return idx;
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}
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static int cpsw_ale_match_addr(struct cpsw_ale *ale, u8 *addr)
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{
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u32 ale_entry[ALE_ENTRY_WORDS];
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int type, idx;
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for (idx = 0; idx < ale->params.ale_entries; idx++) {
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u8 entry_addr[6];
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cpsw_ale_read(ale, idx, ale_entry);
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type = cpsw_ale_get_entry_type(ale_entry);
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if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
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continue;
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cpsw_ale_get_addr(ale_entry, entry_addr);
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if (memcmp(entry_addr, addr, 6) == 0)
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return idx;
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}
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return -ENOENT;
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}
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static int cpsw_ale_match_free(struct cpsw_ale *ale)
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{
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u32 ale_entry[ALE_ENTRY_WORDS];
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int type, idx;
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for (idx = 0; idx < ale->params.ale_entries; idx++) {
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cpsw_ale_read(ale, idx, ale_entry);
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type = cpsw_ale_get_entry_type(ale_entry);
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if (type == ALE_TYPE_FREE)
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return idx;
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}
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return -ENOENT;
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}
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static int cpsw_ale_find_ageable(struct cpsw_ale *ale)
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{
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u32 ale_entry[ALE_ENTRY_WORDS];
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int type, idx;
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for (idx = 0; idx < ale->params.ale_entries; idx++) {
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cpsw_ale_read(ale, idx, ale_entry);
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type = cpsw_ale_get_entry_type(ale_entry);
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if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
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continue;
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if (cpsw_ale_get_mcast(ale_entry))
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continue;
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type = cpsw_ale_get_ucast_type(ale_entry);
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if (type != ALE_UCAST_PERSISTANT &&
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type != ALE_UCAST_OUI)
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return idx;
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}
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return -ENOENT;
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}
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static void cpsw_ale_flush_mcast(struct cpsw_ale *ale, u32 *ale_entry,
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int port_mask)
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{
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int mask;
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mask = cpsw_ale_get_port_mask(ale_entry);
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if ((mask & port_mask) == 0)
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return; /* ports dont intersect, not interested */
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mask &= ~port_mask;
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/* free if only remaining port is host port */
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if (mask == BIT(ale->params.ale_ports))
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cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE);
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else
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cpsw_ale_set_port_mask(ale_entry, mask);
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}
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static void cpsw_ale_flush_ucast(struct cpsw_ale *ale, u32 *ale_entry,
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int port_mask)
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{
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int port;
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port = cpsw_ale_get_port_num(ale_entry);
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if ((BIT(port) & port_mask) == 0)
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return; /* ports dont intersect, not interested */
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cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE);
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}
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int cpsw_ale_flush(struct cpsw_ale *ale, int port_mask)
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{
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u32 ale_entry[ALE_ENTRY_WORDS];
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int ret, idx;
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for (idx = 0; idx < ale->params.ale_entries; idx++) {
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cpsw_ale_read(ale, idx, ale_entry);
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ret = cpsw_ale_get_entry_type(ale_entry);
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if (ret != ALE_TYPE_ADDR && ret != ALE_TYPE_VLAN_ADDR)
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continue;
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if (cpsw_ale_get_mcast(ale_entry))
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cpsw_ale_flush_mcast(ale, ale_entry, port_mask);
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else
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cpsw_ale_flush_ucast(ale, ale_entry, port_mask);
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cpsw_ale_write(ale, idx, ale_entry);
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}
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return 0;
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}
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int cpsw_ale_add_ucast(struct cpsw_ale *ale, u8 *addr, int port, int flags)
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{
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u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
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int idx;
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cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
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cpsw_ale_set_addr(ale_entry, addr);
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cpsw_ale_set_ucast_type(ale_entry, ALE_UCAST_PERSISTANT);
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cpsw_ale_set_secure(ale_entry, (flags & ALE_SECURE) ? 1 : 0);
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cpsw_ale_set_blocked(ale_entry, (flags & ALE_BLOCKED) ? 1 : 0);
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cpsw_ale_set_port_num(ale_entry, port);
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idx = cpsw_ale_match_addr(ale, addr);
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if (idx < 0)
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idx = cpsw_ale_match_free(ale);
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if (idx < 0)
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idx = cpsw_ale_find_ageable(ale);
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if (idx < 0)
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return -ENOMEM;
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cpsw_ale_write(ale, idx, ale_entry);
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return 0;
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}
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int cpsw_ale_del_ucast(struct cpsw_ale *ale, u8 *addr, int port)
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{
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u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
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int idx;
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idx = cpsw_ale_match_addr(ale, addr);
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if (idx < 0)
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return -ENOENT;
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cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE);
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cpsw_ale_write(ale, idx, ale_entry);
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return 0;
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}
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int cpsw_ale_add_mcast(struct cpsw_ale *ale, u8 *addr, int port_mask,
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int super, int mcast_state)
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{
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u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
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int idx, mask;
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idx = cpsw_ale_match_addr(ale, addr);
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if (idx >= 0)
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cpsw_ale_read(ale, idx, ale_entry);
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cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
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cpsw_ale_set_addr(ale_entry, addr);
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cpsw_ale_set_super(ale_entry, super);
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cpsw_ale_set_mcast_state(ale_entry, mcast_state);
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mask = cpsw_ale_get_port_mask(ale_entry);
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port_mask |= mask;
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cpsw_ale_set_port_mask(ale_entry, port_mask);
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if (idx < 0)
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idx = cpsw_ale_match_free(ale);
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if (idx < 0)
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idx = cpsw_ale_find_ageable(ale);
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if (idx < 0)
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return -ENOMEM;
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cpsw_ale_write(ale, idx, ale_entry);
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return 0;
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}
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int cpsw_ale_del_mcast(struct cpsw_ale *ale, u8 *addr, int port_mask)
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{
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u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
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int idx;
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idx = cpsw_ale_match_addr(ale, addr);
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if (idx < 0)
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return -EINVAL;
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cpsw_ale_read(ale, idx, ale_entry);
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if (port_mask)
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cpsw_ale_set_port_mask(ale_entry, port_mask);
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else
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cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE);
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cpsw_ale_write(ale, idx, ale_entry);
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return 0;
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}
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struct ale_control_info {
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const char *name;
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int offset, port_offset;
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int shift, port_shift;
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int bits;
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};
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static const struct ale_control_info ale_controls[ALE_NUM_CONTROLS] = {
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[ALE_ENABLE] = {
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.name = "enable",
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.offset = ALE_CONTROL,
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.port_offset = 0,
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.shift = 31,
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.port_shift = 0,
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.bits = 1,
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},
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[ALE_CLEAR] = {
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.name = "clear",
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.offset = ALE_CONTROL,
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.port_offset = 0,
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.shift = 30,
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.port_shift = 0,
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.bits = 1,
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},
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[ALE_AGEOUT] = {
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.name = "ageout",
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.offset = ALE_CONTROL,
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.port_offset = 0,
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.shift = 29,
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.port_shift = 0,
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.bits = 1,
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},
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[ALE_VLAN_NOLEARN] = {
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.name = "vlan_nolearn",
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.offset = ALE_CONTROL,
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.port_offset = 0,
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.shift = 7,
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.port_shift = 0,
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.bits = 1,
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},
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[ALE_NO_PORT_VLAN] = {
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.name = "no_port_vlan",
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.offset = ALE_CONTROL,
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.port_offset = 0,
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.shift = 6,
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.port_shift = 0,
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.bits = 1,
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},
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[ALE_OUI_DENY] = {
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.name = "oui_deny",
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.offset = ALE_CONTROL,
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.port_offset = 0,
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.shift = 5,
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.port_shift = 0,
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.bits = 1,
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},
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[ALE_BYPASS] = {
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.name = "bypass",
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.offset = ALE_CONTROL,
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.port_offset = 0,
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.shift = 4,
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.port_shift = 0,
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.bits = 1,
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},
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[ALE_RATE_LIMIT_TX] = {
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.name = "rate_limit_tx",
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.offset = ALE_CONTROL,
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.port_offset = 0,
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.shift = 3,
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.port_shift = 0,
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.bits = 1,
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},
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[ALE_VLAN_AWARE] = {
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.name = "vlan_aware",
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.offset = ALE_CONTROL,
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.port_offset = 0,
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.shift = 2,
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.port_shift = 0,
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.bits = 1,
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},
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[ALE_AUTH_ENABLE] = {
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.name = "auth_enable",
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.offset = ALE_CONTROL,
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.port_offset = 0,
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.shift = 1,
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.port_shift = 0,
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.bits = 1,
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},
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[ALE_RATE_LIMIT] = {
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.name = "rate_limit",
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.offset = ALE_CONTROL,
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.port_offset = 0,
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.shift = 0,
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.port_shift = 0,
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.bits = 1,
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},
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[ALE_PORT_STATE] = {
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.name = "port_state",
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.offset = ALE_PORTCTL,
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.port_offset = 4,
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.shift = 0,
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.port_shift = 0,
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.bits = 2,
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},
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[ALE_PORT_DROP_UNTAGGED] = {
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.name = "drop_untagged",
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.offset = ALE_PORTCTL,
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.port_offset = 4,
|
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.shift = 2,
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.port_shift = 0,
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.bits = 1,
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},
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[ALE_PORT_DROP_UNKNOWN_VLAN] = {
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.name = "drop_unknown",
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.offset = ALE_PORTCTL,
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.port_offset = 4,
|
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.shift = 3,
|
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.port_shift = 0,
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.bits = 1,
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},
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[ALE_PORT_NOLEARN] = {
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.name = "nolearn",
|
||||
.offset = ALE_PORTCTL,
|
||||
.port_offset = 4,
|
||||
.shift = 4,
|
||||
.port_shift = 0,
|
||||
.bits = 1,
|
||||
},
|
||||
[ALE_PORT_MCAST_LIMIT] = {
|
||||
.name = "mcast_limit",
|
||||
.offset = ALE_PORTCTL,
|
||||
.port_offset = 4,
|
||||
.shift = 16,
|
||||
.port_shift = 0,
|
||||
.bits = 8,
|
||||
},
|
||||
[ALE_PORT_BCAST_LIMIT] = {
|
||||
.name = "bcast_limit",
|
||||
.offset = ALE_PORTCTL,
|
||||
.port_offset = 4,
|
||||
.shift = 24,
|
||||
.port_shift = 0,
|
||||
.bits = 8,
|
||||
},
|
||||
[ALE_PORT_UNKNOWN_VLAN_MEMBER] = {
|
||||
.name = "unknown_vlan_member",
|
||||
.offset = ALE_UNKNOWNVLAN,
|
||||
.port_offset = 0,
|
||||
.shift = 0,
|
||||
.port_shift = 0,
|
||||
.bits = 6,
|
||||
},
|
||||
[ALE_PORT_UNKNOWN_MCAST_FLOOD] = {
|
||||
.name = "unknown_mcast_flood",
|
||||
.offset = ALE_UNKNOWNVLAN,
|
||||
.port_offset = 0,
|
||||
.shift = 8,
|
||||
.port_shift = 0,
|
||||
.bits = 6,
|
||||
},
|
||||
[ALE_PORT_UNKNOWN_REG_MCAST_FLOOD] = {
|
||||
.name = "unknown_reg_flood",
|
||||
.offset = ALE_UNKNOWNVLAN,
|
||||
.port_offset = 0,
|
||||
.shift = 16,
|
||||
.port_shift = 0,
|
||||
.bits = 6,
|
||||
},
|
||||
[ALE_PORT_UNTAGGED_EGRESS] = {
|
||||
.name = "untagged_egress",
|
||||
.offset = ALE_UNKNOWNVLAN,
|
||||
.port_offset = 0,
|
||||
.shift = 24,
|
||||
.port_shift = 0,
|
||||
.bits = 6,
|
||||
},
|
||||
};
|
||||
|
||||
int cpsw_ale_control_set(struct cpsw_ale *ale, int port, int control,
|
||||
int value)
|
||||
{
|
||||
const struct ale_control_info *info;
|
||||
int offset, shift;
|
||||
u32 tmp, mask;
|
||||
|
||||
if (control < 0 || control >= ARRAY_SIZE(ale_controls))
|
||||
return -EINVAL;
|
||||
|
||||
info = &ale_controls[control];
|
||||
if (info->port_offset == 0 && info->port_shift == 0)
|
||||
port = 0; /* global, port is a dont care */
|
||||
|
||||
if (port < 0 || port > ale->params.ale_ports)
|
||||
return -EINVAL;
|
||||
|
||||
mask = BITMASK(info->bits);
|
||||
if (value & ~mask)
|
||||
return -EINVAL;
|
||||
|
||||
offset = info->offset + (port * info->port_offset);
|
||||
shift = info->shift + (port * info->port_shift);
|
||||
|
||||
tmp = __raw_readl(ale->params.ale_regs + offset);
|
||||
tmp = (tmp & ~(mask << shift)) | (value << shift);
|
||||
__raw_writel(tmp, ale->params.ale_regs + offset);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int cpsw_ale_control_get(struct cpsw_ale *ale, int port, int control)
|
||||
{
|
||||
const struct ale_control_info *info;
|
||||
int offset, shift;
|
||||
u32 tmp;
|
||||
|
||||
if (control < 0 || control >= ARRAY_SIZE(ale_controls))
|
||||
return -EINVAL;
|
||||
|
||||
info = &ale_controls[control];
|
||||
if (info->port_offset == 0 && info->port_shift == 0)
|
||||
port = 0; /* global, port is a dont care */
|
||||
|
||||
if (port < 0 || port > ale->params.ale_ports)
|
||||
return -EINVAL;
|
||||
|
||||
offset = info->offset + (port * info->port_offset);
|
||||
shift = info->shift + (port * info->port_shift);
|
||||
|
||||
tmp = __raw_readl(ale->params.ale_regs + offset) >> shift;
|
||||
return tmp & BITMASK(info->bits);
|
||||
}
|
||||
|
||||
static void cpsw_ale_timer(unsigned long arg)
|
||||
{
|
||||
struct cpsw_ale *ale = (struct cpsw_ale *)arg;
|
||||
|
||||
cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
|
||||
|
||||
if (ale->ageout) {
|
||||
ale->timer.expires = jiffies + ale->ageout;
|
||||
add_timer(&ale->timer);
|
||||
}
|
||||
}
|
||||
|
||||
int cpsw_ale_set_ageout(struct cpsw_ale *ale, int ageout)
|
||||
{
|
||||
del_timer_sync(&ale->timer);
|
||||
ale->ageout = ageout * HZ;
|
||||
if (ale->ageout) {
|
||||
ale->timer.expires = jiffies + ale->ageout;
|
||||
add_timer(&ale->timer);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
void cpsw_ale_start(struct cpsw_ale *ale)
|
||||
{
|
||||
u32 rev;
|
||||
|
||||
rev = __raw_readl(ale->params.ale_regs + ALE_IDVER);
|
||||
dev_dbg(ale->params.dev, "initialized cpsw ale revision %d.%d\n",
|
||||
ALE_VERSION_MAJOR(rev), ALE_VERSION_MINOR(rev));
|
||||
cpsw_ale_control_set(ale, 0, ALE_ENABLE, 1);
|
||||
cpsw_ale_control_set(ale, 0, ALE_CLEAR, 1);
|
||||
|
||||
init_timer(&ale->timer);
|
||||
ale->timer.data = (unsigned long)ale;
|
||||
ale->timer.function = cpsw_ale_timer;
|
||||
if (ale->ageout) {
|
||||
ale->timer.expires = jiffies + ale->ageout;
|
||||
add_timer(&ale->timer);
|
||||
}
|
||||
}
|
||||
|
||||
void cpsw_ale_stop(struct cpsw_ale *ale)
|
||||
{
|
||||
del_timer_sync(&ale->timer);
|
||||
}
|
||||
|
||||
struct cpsw_ale *cpsw_ale_create(struct cpsw_ale_params *params)
|
||||
{
|
||||
struct cpsw_ale *ale;
|
||||
|
||||
ale = kzalloc(sizeof(*ale), GFP_KERNEL);
|
||||
if (!ale)
|
||||
return NULL;
|
||||
|
||||
ale->params = *params;
|
||||
ale->ageout = ale->params.ale_ageout * HZ;
|
||||
|
||||
return ale;
|
||||
}
|
||||
|
||||
int cpsw_ale_destroy(struct cpsw_ale *ale)
|
||||
{
|
||||
if (!ale)
|
||||
return -EINVAL;
|
||||
cpsw_ale_stop(ale);
|
||||
cpsw_ale_control_set(ale, 0, ALE_ENABLE, 0);
|
||||
kfree(ale);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,93 @@
|
|||
/*
|
||||
* Texas Instruments 3-Port Ethernet Switch Address Lookup Engine APIs
|
||||
*
|
||||
* Copyright (C) 2012 Texas Instruments
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
#ifndef __TI_CPSW_ALE_H__
|
||||
#define __TI_CPSW_ALE_H__
|
||||
|
||||
struct cpsw_ale_params {
|
||||
struct device *dev;
|
||||
void __iomem *ale_regs;
|
||||
unsigned long ale_ageout; /* in secs */
|
||||
unsigned long ale_entries;
|
||||
unsigned long ale_ports;
|
||||
};
|
||||
|
||||
struct cpsw_ale {
|
||||
struct cpsw_ale_params params;
|
||||
struct timer_list timer;
|
||||
unsigned long ageout;
|
||||
};
|
||||
|
||||
enum cpsw_ale_control {
|
||||
/* global */
|
||||
ALE_ENABLE,
|
||||
ALE_CLEAR,
|
||||
ALE_AGEOUT,
|
||||
ALE_VLAN_NOLEARN,
|
||||
ALE_NO_PORT_VLAN,
|
||||
ALE_OUI_DENY,
|
||||
ALE_BYPASS,
|
||||
ALE_RATE_LIMIT_TX,
|
||||
ALE_VLAN_AWARE,
|
||||
ALE_AUTH_ENABLE,
|
||||
ALE_RATE_LIMIT,
|
||||
/* port controls */
|
||||
ALE_PORT_STATE,
|
||||
ALE_PORT_DROP_UNTAGGED,
|
||||
ALE_PORT_DROP_UNKNOWN_VLAN,
|
||||
ALE_PORT_NOLEARN,
|
||||
ALE_PORT_UNKNOWN_VLAN_MEMBER,
|
||||
ALE_PORT_UNKNOWN_MCAST_FLOOD,
|
||||
ALE_PORT_UNKNOWN_REG_MCAST_FLOOD,
|
||||
ALE_PORT_UNTAGGED_EGRESS,
|
||||
ALE_PORT_BCAST_LIMIT,
|
||||
ALE_PORT_MCAST_LIMIT,
|
||||
ALE_NUM_CONTROLS,
|
||||
};
|
||||
|
||||
enum cpsw_ale_port_state {
|
||||
ALE_PORT_STATE_DISABLE = 0x00,
|
||||
ALE_PORT_STATE_BLOCK = 0x01,
|
||||
ALE_PORT_STATE_LEARN = 0x02,
|
||||
ALE_PORT_STATE_FORWARD = 0x03,
|
||||
};
|
||||
|
||||
/* ALE unicast entry flags - passed into cpsw_ale_add_ucast() */
|
||||
#define ALE_SECURE 1
|
||||
#define ALE_BLOCKED 2
|
||||
|
||||
#define ALE_MCAST_FWD 0
|
||||
#define ALE_MCAST_BLOCK_LEARN_FWD 1
|
||||
#define ALE_MCAST_FWD_LEARN 2
|
||||
#define ALE_MCAST_FWD_2 3
|
||||
|
||||
struct cpsw_ale *cpsw_ale_create(struct cpsw_ale_params *params);
|
||||
int cpsw_ale_destroy(struct cpsw_ale *ale);
|
||||
|
||||
void cpsw_ale_start(struct cpsw_ale *ale);
|
||||
void cpsw_ale_stop(struct cpsw_ale *ale);
|
||||
|
||||
int cpsw_ale_set_ageout(struct cpsw_ale *ale, int ageout);
|
||||
int cpsw_ale_flush(struct cpsw_ale *ale, int port_mask);
|
||||
int cpsw_ale_add_ucast(struct cpsw_ale *ale, u8 *addr, int port, int flags);
|
||||
int cpsw_ale_del_ucast(struct cpsw_ale *ale, u8 *addr, int port);
|
||||
int cpsw_ale_add_mcast(struct cpsw_ale *ale, u8 *addr, int port_mask,
|
||||
int super, int mcast_state);
|
||||
int cpsw_ale_del_mcast(struct cpsw_ale *ale, u8 *addr, int port_mask);
|
||||
|
||||
int cpsw_ale_control_get(struct cpsw_ale *ale, int port, int control);
|
||||
int cpsw_ale_control_set(struct cpsw_ale *ale, int port,
|
||||
int control, int value);
|
||||
|
||||
#endif
|
||||
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