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@ -139,6 +139,10 @@
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* Selects interface with clock source for mISDN and applications.
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* Set to card number starting with 1. Set to -1 to disable.
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* By default, the first card is used as clock source.
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*
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* hwid:
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* NOTE: only one hwid value must be given once
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* Enable special embedded devices with XHFC controllers.
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*/
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/*
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@ -206,6 +210,11 @@ static int clock;
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static uint timer;
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static uint clockdelay_te = CLKDEL_TE;
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static uint clockdelay_nt = CLKDEL_NT;
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#define HWID_NONE 0
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#define HWID_MINIP4 1
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#define HWID_MINIP8 2
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#define HWID_MINIP16 3
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static uint hwid = HWID_NONE;
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static int HFC_cnt, Port_cnt, PCM_cnt = 99;
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@ -223,6 +232,7 @@ module_param_array(pcm, int, NULL, S_IRUGO | S_IWUSR);
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module_param_array(dslot, int, NULL, S_IRUGO | S_IWUSR);
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module_param_array(iomode, uint, NULL, S_IRUGO | S_IWUSR);
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module_param_array(port, uint, NULL, S_IRUGO | S_IWUSR);
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module_param(hwid, uint, S_IRUGO | S_IWUSR); /* The hardware ID */
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#ifdef HFC_REGISTER_DEBUG
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#define HFC_outb(hc, reg, val) \
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@ -252,6 +262,10 @@ module_param_array(port, uint, NULL, S_IRUGO | S_IWUSR);
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#define HFC_wait_nodebug(hc) (hc->HFC_wait_nodebug(hc))
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#endif
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#ifdef CONFIG_MISDN_HFCMULTI_8xx
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#include "hfc_multi_8xx.h"
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#endif
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/* HFC_IO_MODE_PCIMEM */
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static void
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#ifdef HFC_REGISTER_DEBUG
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@ -928,7 +942,7 @@ hfcmulti_resync(struct hfc_multi *locked, struct hfc_multi *newmaster, int rm)
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writel(pv, plx_acc_32);
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if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) {
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pcmmaster = hc;
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if (hc->type == 1) {
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if (hc->ctype == HFC_TYPE_E1) {
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if (debug & DEBUG_HFCMULTI_PLXSD)
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printk(KERN_DEBUG
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"Schedule SYNC_I\n");
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@ -949,7 +963,8 @@ hfcmulti_resync(struct hfc_multi *locked, struct hfc_multi *newmaster, int rm)
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pv |= PLX_SYNC_O_EN;
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writel(pv, plx_acc_32);
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/* switch to jatt PLL, if not disabled by RX_SYNC */
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if (hc->type == 1 && !test_bit(HFC_CHIP_RX_SYNC, &hc->chip)) {
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if (hc->ctype == HFC_TYPE_E1
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&& !test_bit(HFC_CHIP_RX_SYNC, &hc->chip)) {
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if (debug & DEBUG_HFCMULTI_PLXSD)
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printk(KERN_DEBUG "Schedule jatt PLL\n");
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hc->e1_resync |= 2; /* switch to jatt */
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@ -961,7 +976,7 @@ hfcmulti_resync(struct hfc_multi *locked, struct hfc_multi *newmaster, int rm)
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printk(KERN_DEBUG
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"id=%d (0x%p) = PCM master syncronized "
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"with QUARTZ\n", hc->id, hc);
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if (hc->type == 1) {
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if (hc->ctype == HFC_TYPE_E1) {
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/* Use the crystal clock for the PCM
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master card */
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if (debug & DEBUG_HFCMULTI_PLXSD)
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@ -972,7 +987,7 @@ hfcmulti_resync(struct hfc_multi *locked, struct hfc_multi *newmaster, int rm)
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if (debug & DEBUG_HFCMULTI_PLXSD)
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printk(KERN_DEBUG
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"QUARTZ is automatically "
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"enabled by HFC-%dS\n", hc->type);
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"enabled by HFC-%dS\n", hc->ctype);
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}
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plx_acc_32 = hc->plx_membase + PLX_GPIOC;
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pv = readl(plx_acc_32);
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@ -1060,13 +1075,16 @@ release_io_hfcmulti(struct hfc_multi *hc)
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/* disable memory mapped ports / io ports */
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test_and_clear_bit(HFC_CHIP_PLXSD, &hc->chip); /* prevent resync */
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pci_write_config_word(hc->pci_dev, PCI_COMMAND, 0);
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if (hc->pci_dev)
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pci_write_config_word(hc->pci_dev, PCI_COMMAND, 0);
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if (hc->pci_membase)
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iounmap(hc->pci_membase);
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if (hc->plx_membase)
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iounmap(hc->plx_membase);
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if (hc->pci_iobase)
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release_region(hc->pci_iobase, 8);
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if (hc->xhfc_membase)
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iounmap((void *)hc->xhfc_membase);
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if (hc->pci_dev) {
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pci_disable_device(hc->pci_dev);
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@ -1100,8 +1118,9 @@ init_chip(struct hfc_multi *hc)
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/* revision check */
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if (debug & DEBUG_HFCMULTI_INIT)
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printk(KERN_DEBUG "%s: entered\n", __func__);
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val = HFC_inb(hc, R_CHIP_ID)>>4;
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if (val != 0x8 && val != 0xc && val != 0xe) {
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val = HFC_inb(hc, R_CHIP_ID);
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if ((val>>4) != 0x8 && (val>>4) != 0xc && (val>>4) != 0xe
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&& (val>>1) != 0x31) {
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printk(KERN_INFO "HFC_multi: unknown CHIP_ID:%x\n", (u_int)val);
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err = -EIO;
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goto out;
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@ -1109,8 +1128,9 @@ init_chip(struct hfc_multi *hc)
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rev = HFC_inb(hc, R_CHIP_RV);
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printk(KERN_INFO
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"HFC_multi: detected HFC with chip ID=0x%lx revision=%ld%s\n",
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val, rev, (rev == 0) ? " (old FIFO handling)" : "");
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if (rev == 0) {
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val, rev, (rev == 0 && (hc->ctype != HFC_TYPE_XHFC)) ?
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" (old FIFO handling)" : "");
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if (hc->ctype != HFC_TYPE_XHFC && rev == 0) {
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test_and_set_bit(HFC_CHIP_REVISION0, &hc->chip);
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printk(KERN_WARNING
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"HFC_multi: NOTE: Your chip is revision 0, "
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@ -1152,6 +1172,12 @@ init_chip(struct hfc_multi *hc)
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hc->Zlen = 8000;
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hc->DTMFbase = 0x2000;
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}
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if (hc->ctype == HFC_TYPE_XHFC) {
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hc->Flen = 0x8;
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hc->Zmin = 0x0;
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hc->Zlen = 64;
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hc->DTMFbase = 0x0;
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}
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hc->max_trans = poll << 1;
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if (hc->max_trans > hc->Zlen)
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hc->max_trans = hc->Zlen;
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@ -1211,6 +1237,9 @@ init_chip(struct hfc_multi *hc)
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hc->hw.r_pcm_md0 = V_F0_LEN; /* shift clock for DSP */
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}
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if (test_bit(HFC_CHIP_EMBSD, &hc->chip))
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hc->hw.r_pcm_md0 = V_F0_LEN; /* shift clock for DSP */
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/* we only want the real Z2 read-pointer for revision > 0 */
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if (!test_bit(HFC_CHIP_REVISION0, &hc->chip))
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hc->hw.r_ram_sz |= V_FZ_MD;
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@ -1234,15 +1263,24 @@ init_chip(struct hfc_multi *hc)
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/* soft reset */
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HFC_outb(hc, R_CTRL, hc->hw.r_ctrl);
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HFC_outb(hc, R_RAM_SZ, hc->hw.r_ram_sz);
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if (hc->ctype == HFC_TYPE_XHFC)
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HFC_outb(hc, 0x0C /* R_FIFO_THRES */,
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0x11 /* 16 Bytes TX/RX */);
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else
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HFC_outb(hc, R_RAM_SZ, hc->hw.r_ram_sz);
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HFC_outb(hc, R_FIFO_MD, 0);
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hc->hw.r_cirm = V_SRES | V_HFCRES | V_PCMRES | V_STRES | V_RLD_EPR;
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if (hc->ctype == HFC_TYPE_XHFC)
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hc->hw.r_cirm = V_SRES | V_HFCRES | V_PCMRES | V_STRES;
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else
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hc->hw.r_cirm = V_SRES | V_HFCRES | V_PCMRES | V_STRES
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| V_RLD_EPR;
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HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
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udelay(100);
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hc->hw.r_cirm = 0;
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HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
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udelay(100);
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HFC_outb(hc, R_RAM_SZ, hc->hw.r_ram_sz);
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if (hc->ctype != HFC_TYPE_XHFC)
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HFC_outb(hc, R_RAM_SZ, hc->hw.r_ram_sz);
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/* Speech Design PLX bridge pcm and sync mode */
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if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
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@ -1278,13 +1316,16 @@ init_chip(struct hfc_multi *hc)
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HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0xa0);
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if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
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HFC_outb(hc, R_PCM_MD2, V_SYNC_SRC); /* sync via SYNC_I / O */
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else if (test_bit(HFC_CHIP_EMBSD, &hc->chip))
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HFC_outb(hc, R_PCM_MD2, 0x10); /* V_C2O_EN */
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else
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HFC_outb(hc, R_PCM_MD2, 0x00); /* sync from interface */
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HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x00);
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for (i = 0; i < 256; i++) {
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HFC_outb_nodebug(hc, R_SLOT, i);
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HFC_outb_nodebug(hc, A_SL_CFG, 0);
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HFC_outb_nodebug(hc, A_CONF, 0);
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if (hc->ctype != HFC_TYPE_XHFC)
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HFC_outb_nodebug(hc, A_CONF, 0);
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hc->slot_owner[i] = -1;
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}
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@ -1296,6 +1337,9 @@ init_chip(struct hfc_multi *hc)
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HFC_outb(hc, R_BRG_PCM_CFG, V_PCM_CLK);
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}
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if (test_bit(HFC_CHIP_EMBSD, &hc->chip))
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HFC_outb(hc, 0x02 /* R_CLK_CFG */, 0x40 /* V_CLKO_OFF */);
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/* B410P GPIO */
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if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
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printk(KERN_NOTICE "Setting GPIOs\n");
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@ -1424,7 +1468,7 @@ controller_fail:
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hc->hw.r_irqmsk_misc |= V_TI_IRQMSK;
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/* set E1 state machine IRQ */
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if (hc->type == 1)
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if (hc->ctype == HFC_TYPE_E1)
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hc->hw.r_irqmsk_misc |= V_STA_IRQMSK;
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/* set DTMF detection */
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@ -1444,7 +1488,8 @@ controller_fail:
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r_conf_en = V_CONF_EN | V_ULAW;
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else
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r_conf_en = V_CONF_EN;
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HFC_outb(hc, R_CONF_EN, r_conf_en);
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if (hc->ctype != HFC_TYPE_XHFC)
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HFC_outb(hc, R_CONF_EN, r_conf_en);
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/* setting leds */
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switch (hc->leds) {
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@ -1468,16 +1513,23 @@ controller_fail:
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break;
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}
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if (test_bit(HFC_CHIP_EMBSD, &hc->chip)) {
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hc->hw.r_st_sync = 0x10; /* V_AUTO_SYNCI */
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HFC_outb(hc, R_ST_SYNC, hc->hw.r_st_sync);
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}
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/* set master clock */
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if (hc->masterclk >= 0) {
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if (debug & DEBUG_HFCMULTI_INIT)
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printk(KERN_DEBUG "%s: setting ST master clock "
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"to port %d (0..%d)\n",
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__func__, hc->masterclk, hc->ports-1);
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hc->hw.r_st_sync = hc->masterclk | V_AUTO_SYNC;
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hc->hw.r_st_sync |= (hc->masterclk | V_AUTO_SYNC);
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HFC_outb(hc, R_ST_SYNC, hc->hw.r_st_sync);
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}
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/* setting misc irq */
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HFC_outb(hc, R_IRQMSK_MISC, hc->hw.r_irqmsk_misc);
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|
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if (debug & DEBUG_HFCMULTI_INIT)
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@ -1929,7 +1981,7 @@ next_frame:
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Fspace = 1;
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}
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|
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/* one frame only for ST D-channels, to allow resending */
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|
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if (hc->type != 1 && dch) {
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if (hc->ctype != HFC_TYPE_E1 && dch) {
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if (f1 != f2)
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Fspace = 0;
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}
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@ -1971,12 +2023,22 @@ next_frame:
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"slot_tx %d\n",
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__func__, ch, slot_tx);
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|
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/* connect slot */
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|
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HFC_outb(hc, A_CON_HDLC, 0xc0 | 0x00 |
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|
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V_HDLC_TRP | V_IFF);
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|
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if (hc->ctype == HFC_TYPE_XHFC)
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|
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HFC_outb(hc, A_CON_HDLC, 0xc0
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| 0x07 << 2 | V_HDLC_TRP | V_IFF);
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|
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/* Enable FIFO, no interrupt */
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else
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|
|
HFC_outb(hc, A_CON_HDLC, 0xc0 | 0x00 |
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|
|
V_HDLC_TRP | V_IFF);
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|
|
HFC_outb_nodebug(hc, R_FIFO, ch<<1 | 1);
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|
|
HFC_wait_nodebug(hc);
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|
|
HFC_outb(hc, A_CON_HDLC, 0xc0 | 0x00 |
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|
|
V_HDLC_TRP | V_IFF);
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|
|
if (hc->ctype == HFC_TYPE_XHFC)
|
|
|
|
|
HFC_outb(hc, A_CON_HDLC, 0xc0
|
|
|
|
|
| 0x07 << 2 | V_HDLC_TRP | V_IFF);
|
|
|
|
|
/* Enable FIFO, no interrupt */
|
|
|
|
|
else
|
|
|
|
|
HFC_outb(hc, A_CON_HDLC, 0xc0 | 0x00 |
|
|
|
|
|
V_HDLC_TRP | V_IFF);
|
|
|
|
|
HFC_outb_nodebug(hc, R_FIFO, ch<<1);
|
|
|
|
|
HFC_wait_nodebug(hc);
|
|
|
|
|
}
|
|
|
|
@ -2004,10 +2066,22 @@ next_frame:
|
|
|
|
|
"FIFO data: channel %d slot_tx %d\n",
|
|
|
|
|
__func__, ch, slot_tx);
|
|
|
|
|
/* disconnect slot */
|
|
|
|
|
HFC_outb(hc, A_CON_HDLC, 0x80 | 0x00 | V_HDLC_TRP | V_IFF);
|
|
|
|
|
if (hc->ctype == HFC_TYPE_XHFC)
|
|
|
|
|
HFC_outb(hc, A_CON_HDLC, 0x80
|
|
|
|
|
| 0x07 << 2 | V_HDLC_TRP | V_IFF);
|
|
|
|
|
/* Enable FIFO, no interrupt */
|
|
|
|
|
else
|
|
|
|
|
HFC_outb(hc, A_CON_HDLC, 0x80 | 0x00 |
|
|
|
|
|
V_HDLC_TRP | V_IFF);
|
|
|
|
|
HFC_outb_nodebug(hc, R_FIFO, ch<<1 | 1);
|
|
|
|
|
HFC_wait_nodebug(hc);
|
|
|
|
|
HFC_outb(hc, A_CON_HDLC, 0x80 | 0x00 | V_HDLC_TRP | V_IFF);
|
|
|
|
|
if (hc->ctype == HFC_TYPE_XHFC)
|
|
|
|
|
HFC_outb(hc, A_CON_HDLC, 0x80
|
|
|
|
|
| 0x07 << 2 | V_HDLC_TRP | V_IFF);
|
|
|
|
|
/* Enable FIFO, no interrupt */
|
|
|
|
|
else
|
|
|
|
|
HFC_outb(hc, A_CON_HDLC, 0x80 | 0x00 |
|
|
|
|
|
V_HDLC_TRP | V_IFF);
|
|
|
|
|
HFC_outb_nodebug(hc, R_FIFO, ch<<1);
|
|
|
|
|
HFC_wait_nodebug(hc);
|
|
|
|
|
}
|
|
|
|
@ -2327,7 +2401,7 @@ handle_timer_irq(struct hfc_multi *hc)
|
|
|
|
|
spin_unlock_irqrestore(&HFClock, flags);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (hc->type != 1 || hc->e1_state == 1)
|
|
|
|
|
if (hc->ctype != HFC_TYPE_E1 || hc->e1_state == 1)
|
|
|
|
|
for (ch = 0; ch <= 31; ch++) {
|
|
|
|
|
if (hc->created[hc->chan[ch].port]) {
|
|
|
|
|
hfcmulti_tx(hc, ch);
|
|
|
|
@ -2350,7 +2424,7 @@ handle_timer_irq(struct hfc_multi *hc)
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
if (hc->type == 1 && hc->created[0]) {
|
|
|
|
|
if (hc->ctype == HFC_TYPE_E1 && hc->created[0]) {
|
|
|
|
|
dch = hc->chan[hc->dslot].dch;
|
|
|
|
|
if (test_bit(HFC_CFG_REPORT_LOS, &hc->chan[hc->dslot].cfg)) {
|
|
|
|
|
/* LOS */
|
|
|
|
@ -2610,7 +2684,10 @@ hfcmulti_interrupt(int intno, void *dev_id)
|
|
|
|
|
"card %d, this is no bug.\n", hc->id + 1, irqsem);
|
|
|
|
|
irqsem = hc->id + 1;
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_MISDN_HFCMULTI_8xx
|
|
|
|
|
if (hc->immap->im_cpm.cp_pbdat & hc->pb_irqmsk)
|
|
|
|
|
goto irq_notforus;
|
|
|
|
|
#endif
|
|
|
|
|
if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
|
|
|
|
|
spin_lock_irqsave(&plx_lock, flags);
|
|
|
|
|
plx_acc = hc->plx_membase + PLX_INTCSR;
|
|
|
|
@ -2650,7 +2727,7 @@ hfcmulti_interrupt(int intno, void *dev_id)
|
|
|
|
|
}
|
|
|
|
|
hc->irqcnt++;
|
|
|
|
|
if (r_irq_statech) {
|
|
|
|
|
if (hc->type != 1)
|
|
|
|
|
if (hc->ctype != HFC_TYPE_E1)
|
|
|
|
|
ph_state_irq(hc, r_irq_statech);
|
|
|
|
|
}
|
|
|
|
|
if (status & V_EXT_IRQSTA)
|
|
|
|
@ -2664,7 +2741,7 @@ hfcmulti_interrupt(int intno, void *dev_id)
|
|
|
|
|
r_irq_misc = HFC_inb_nodebug(hc, R_IRQ_MISC);
|
|
|
|
|
r_irq_misc &= hc->hw.r_irqmsk_misc; /* ignore disabled irqs */
|
|
|
|
|
if (r_irq_misc & V_STA_IRQ) {
|
|
|
|
|
if (hc->type == 1) {
|
|
|
|
|
if (hc->ctype == HFC_TYPE_E1) {
|
|
|
|
|
/* state machine */
|
|
|
|
|
dch = hc->chan[hc->dslot].dch;
|
|
|
|
|
e1_syncsta = HFC_inb_nodebug(hc, R_SYNC_STA);
|
|
|
|
@ -2786,7 +2863,8 @@ mode_hfcmulti(struct hfc_multi *hc, int ch, int protocol, int slot_tx,
|
|
|
|
|
if (hc->slot_owner[oslot_tx<<1] == ch) {
|
|
|
|
|
HFC_outb(hc, R_SLOT, oslot_tx << 1);
|
|
|
|
|
HFC_outb(hc, A_SL_CFG, 0);
|
|
|
|
|
HFC_outb(hc, A_CONF, 0);
|
|
|
|
|
if (hc->ctype != HFC_TYPE_XHFC)
|
|
|
|
|
HFC_outb(hc, A_CONF, 0);
|
|
|
|
|
hc->slot_owner[oslot_tx<<1] = -1;
|
|
|
|
|
} else {
|
|
|
|
|
if (debug & DEBUG_HFCMULTI_MODE)
|
|
|
|
@ -2839,7 +2917,9 @@ mode_hfcmulti(struct hfc_multi *hc, int ch, int protocol, int slot_tx,
|
|
|
|
|
flow_tx, routing, conf);
|
|
|
|
|
HFC_outb(hc, R_SLOT, slot_tx << 1);
|
|
|
|
|
HFC_outb(hc, A_SL_CFG, (ch<<1) | routing);
|
|
|
|
|
HFC_outb(hc, A_CONF, (conf < 0) ? 0 : (conf | V_CONF_SL));
|
|
|
|
|
if (hc->ctype != HFC_TYPE_XHFC)
|
|
|
|
|
HFC_outb(hc, A_CONF,
|
|
|
|
|
(conf < 0) ? 0 : (conf | V_CONF_SL));
|
|
|
|
|
hc->slot_owner[slot_tx << 1] = ch;
|
|
|
|
|
hc->chan[ch].slot_tx = slot_tx;
|
|
|
|
|
hc->chan[ch].bank_tx = bank_tx;
|
|
|
|
@ -2889,7 +2969,7 @@ mode_hfcmulti(struct hfc_multi *hc, int ch, int protocol, int slot_tx,
|
|
|
|
|
HFC_outb(hc, A_IRQ_MSK, 0);
|
|
|
|
|
HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
|
|
|
|
|
HFC_wait(hc);
|
|
|
|
|
if (hc->chan[ch].bch && hc->type != 1) {
|
|
|
|
|
if (hc->chan[ch].bch && hc->ctype != HFC_TYPE_E1) {
|
|
|
|
|
hc->hw.a_st_ctrl0[hc->chan[ch].port] &=
|
|
|
|
|
((ch & 0x3) == 0)? ~V_B1_EN: ~V_B2_EN;
|
|
|
|
|
HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
|
|
|
|
@ -2965,8 +3045,13 @@ mode_hfcmulti(struct hfc_multi *hc, int ch, int protocol, int slot_tx,
|
|
|
|
|
/* enable TX fifo */
|
|
|
|
|
HFC_outb(hc, R_FIFO, ch << 1);
|
|
|
|
|
HFC_wait(hc);
|
|
|
|
|
HFC_outb(hc, A_CON_HDLC, flow_tx | 0x00 |
|
|
|
|
|
V_HDLC_TRP | V_IFF);
|
|
|
|
|
if (hc->ctype == HFC_TYPE_XHFC)
|
|
|
|
|
HFC_outb(hc, A_CON_HDLC, flow_tx | 0x07 << 2 |
|
|
|
|
|
V_HDLC_TRP | V_IFF);
|
|
|
|
|
/* Enable FIFO, no interrupt */
|
|
|
|
|
else
|
|
|
|
|
HFC_outb(hc, A_CON_HDLC, flow_tx | 0x00 |
|
|
|
|
|
V_HDLC_TRP | V_IFF);
|
|
|
|
|
HFC_outb(hc, A_SUBCH_CFG, 0);
|
|
|
|
|
HFC_outb(hc, A_IRQ_MSK, 0);
|
|
|
|
|
HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
|
|
|
|
@ -2976,13 +3061,19 @@ mode_hfcmulti(struct hfc_multi *hc, int ch, int protocol, int slot_tx,
|
|
|
|
|
/* enable RX fifo */
|
|
|
|
|
HFC_outb(hc, R_FIFO, (ch<<1)|1);
|
|
|
|
|
HFC_wait(hc);
|
|
|
|
|
HFC_outb(hc, A_CON_HDLC, flow_rx | 0x00 | V_HDLC_TRP);
|
|
|
|
|
if (hc->ctype == HFC_TYPE_XHFC)
|
|
|
|
|
HFC_outb(hc, A_CON_HDLC, flow_rx | 0x07 << 2 |
|
|
|
|
|
V_HDLC_TRP);
|
|
|
|
|
/* Enable FIFO, no interrupt*/
|
|
|
|
|
else
|
|
|
|
|
HFC_outb(hc, A_CON_HDLC, flow_rx | 0x00 |
|
|
|
|
|
V_HDLC_TRP);
|
|
|
|
|
HFC_outb(hc, A_SUBCH_CFG, 0);
|
|
|
|
|
HFC_outb(hc, A_IRQ_MSK, 0);
|
|
|
|
|
HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
|
|
|
|
|
HFC_wait(hc);
|
|
|
|
|
}
|
|
|
|
|
if (hc->type != 1) {
|
|
|
|
|
if (hc->ctype != HFC_TYPE_E1) {
|
|
|
|
|
hc->hw.a_st_ctrl0[hc->chan[ch].port] |=
|
|
|
|
|
((ch & 0x3) == 0) ? V_B1_EN : V_B2_EN;
|
|
|
|
|
HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
|
|
|
|
@ -3003,7 +3094,7 @@ mode_hfcmulti(struct hfc_multi *hc, int ch, int protocol, int slot_tx,
|
|
|
|
|
/* enable TX fifo */
|
|
|
|
|
HFC_outb(hc, R_FIFO, ch<<1);
|
|
|
|
|
HFC_wait(hc);
|
|
|
|
|
if (hc->type == 1 || hc->chan[ch].bch) {
|
|
|
|
|
if (hc->ctype == HFC_TYPE_E1 || hc->chan[ch].bch) {
|
|
|
|
|
/* E1 or B-channel */
|
|
|
|
|
HFC_outb(hc, A_CON_HDLC, flow_tx | 0x04);
|
|
|
|
|
HFC_outb(hc, A_SUBCH_CFG, 0);
|
|
|
|
@ -3019,7 +3110,7 @@ mode_hfcmulti(struct hfc_multi *hc, int ch, int protocol, int slot_tx,
|
|
|
|
|
HFC_outb(hc, R_FIFO, (ch<<1)|1);
|
|
|
|
|
HFC_wait(hc);
|
|
|
|
|
HFC_outb(hc, A_CON_HDLC, flow_rx | 0x04);
|
|
|
|
|
if (hc->type == 1 || hc->chan[ch].bch)
|
|
|
|
|
if (hc->ctype == HFC_TYPE_E1 || hc->chan[ch].bch)
|
|
|
|
|
HFC_outb(hc, A_SUBCH_CFG, 0); /* full 8 bits */
|
|
|
|
|
else
|
|
|
|
|
HFC_outb(hc, A_SUBCH_CFG, 2); /* 2 bits dchannel */
|
|
|
|
@ -3028,7 +3119,7 @@ mode_hfcmulti(struct hfc_multi *hc, int ch, int protocol, int slot_tx,
|
|
|
|
|
HFC_wait(hc);
|
|
|
|
|
if (hc->chan[ch].bch) {
|
|
|
|
|
test_and_set_bit(FLG_HDLC, &hc->chan[ch].bch->Flags);
|
|
|
|
|
if (hc->type != 1) {
|
|
|
|
|
if (hc->ctype != HFC_TYPE_E1) {
|
|
|
|
|
hc->hw.a_st_ctrl0[hc->chan[ch].port] |=
|
|
|
|
|
((ch&0x3) == 0) ? V_B1_EN : V_B2_EN;
|
|
|
|
|
HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
|
|
|
|
@ -3108,7 +3199,7 @@ hfcm_l1callback(struct dchannel *dch, u_int cmd)
|
|
|
|
|
case HW_RESET_REQ:
|
|
|
|
|
/* start activation */
|
|
|
|
|
spin_lock_irqsave(&hc->lock, flags);
|
|
|
|
|
if (hc->type == 1) {
|
|
|
|
|
if (hc->ctype == HFC_TYPE_E1) {
|
|
|
|
|
if (debug & DEBUG_HFCMULTI_MSG)
|
|
|
|
|
printk(KERN_DEBUG
|
|
|
|
|
"%s: HW_RESET_REQ no BRI\n",
|
|
|
|
@ -3129,7 +3220,7 @@ hfcm_l1callback(struct dchannel *dch, u_int cmd)
|
|
|
|
|
case HW_DEACT_REQ:
|
|
|
|
|
/* start deactivation */
|
|
|
|
|
spin_lock_irqsave(&hc->lock, flags);
|
|
|
|
|
if (hc->type == 1) {
|
|
|
|
|
if (hc->ctype == HFC_TYPE_E1) {
|
|
|
|
|
if (debug & DEBUG_HFCMULTI_MSG)
|
|
|
|
|
printk(KERN_DEBUG
|
|
|
|
|
"%s: HW_DEACT_REQ no BRI\n",
|
|
|
|
@ -3163,7 +3254,7 @@ hfcm_l1callback(struct dchannel *dch, u_int cmd)
|
|
|
|
|
break;
|
|
|
|
|
case HW_POWERUP_REQ:
|
|
|
|
|
spin_lock_irqsave(&hc->lock, flags);
|
|
|
|
|
if (hc->type == 1) {
|
|
|
|
|
if (hc->ctype == HFC_TYPE_E1) {
|
|
|
|
|
if (debug & DEBUG_HFCMULTI_MSG)
|
|
|
|
|
printk(KERN_DEBUG
|
|
|
|
|
"%s: HW_POWERUP_REQ no BRI\n",
|
|
|
|
@ -3240,7 +3331,7 @@ handle_dmsg(struct mISDNchannel *ch, struct sk_buff *skb)
|
|
|
|
|
__func__, hc->chan[dch->slot].port,
|
|
|
|
|
hc->ports-1);
|
|
|
|
|
/* start activation */
|
|
|
|
|
if (hc->type == 1) {
|
|
|
|
|
if (hc->ctype == HFC_TYPE_E1) {
|
|
|
|
|
ph_state_change(dch);
|
|
|
|
|
if (debug & DEBUG_HFCMULTI_STATE)
|
|
|
|
|
printk(KERN_DEBUG
|
|
|
|
@ -3273,7 +3364,7 @@ handle_dmsg(struct mISDNchannel *ch, struct sk_buff *skb)
|
|
|
|
|
__func__, hc->chan[dch->slot].port,
|
|
|
|
|
hc->ports-1);
|
|
|
|
|
/* start deactivation */
|
|
|
|
|
if (hc->type == 1) {
|
|
|
|
|
if (hc->ctype == HFC_TYPE_E1) {
|
|
|
|
|
if (debug & DEBUG_HFCMULTI_MSG)
|
|
|
|
|
printk(KERN_DEBUG
|
|
|
|
|
"%s: PH_DEACTIVATE no BRI\n",
|
|
|
|
@ -3493,6 +3584,8 @@ channel_bctrl(struct bchannel *bch, struct mISDN_ctrl_req *cq)
|
|
|
|
|
features->hfc_id = hc->id;
|
|
|
|
|
if (test_bit(HFC_CHIP_DTMF, &hc->chip))
|
|
|
|
|
features->hfc_dtmf = 1;
|
|
|
|
|
if (test_bit(HFC_CHIP_CONF, &hc->chip))
|
|
|
|
|
features->hfc_conf = 1;
|
|
|
|
|
features->hfc_loops = 0;
|
|
|
|
|
if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
|
|
|
|
|
features->hfc_echocanhw = 1;
|
|
|
|
@ -3630,7 +3723,7 @@ ph_state_change(struct dchannel *dch)
|
|
|
|
|
hc = dch->hw;
|
|
|
|
|
ch = dch->slot;
|
|
|
|
|
|
|
|
|
|
if (hc->type == 1) {
|
|
|
|
|
if (hc->ctype == HFC_TYPE_E1) {
|
|
|
|
|
if (dch->dev.D.protocol == ISDN_P_TE_E1) {
|
|
|
|
|
if (debug & DEBUG_HFCMULTI_STATE)
|
|
|
|
|
printk(KERN_DEBUG
|
|
|
|
@ -3755,7 +3848,7 @@ hfcmulti_initmode(struct dchannel *dch)
|
|
|
|
|
if (debug & DEBUG_HFCMULTI_INIT)
|
|
|
|
|
printk(KERN_DEBUG "%s: entered\n", __func__);
|
|
|
|
|
|
|
|
|
|
if (hc->type == 1) {
|
|
|
|
|
if (hc->ctype == HFC_TYPE_E1) {
|
|
|
|
|
hc->chan[hc->dslot].slot_tx = -1;
|
|
|
|
|
hc->chan[hc->dslot].slot_rx = -1;
|
|
|
|
|
hc->chan[hc->dslot].conf = -1;
|
|
|
|
@ -3904,6 +3997,11 @@ hfcmulti_initmode(struct dchannel *dch)
|
|
|
|
|
}
|
|
|
|
|
if (!test_bit(HFC_CFG_NONCAP_TX, &hc->chan[i].cfg))
|
|
|
|
|
hc->hw.a_st_ctrl0[pt] |= V_TX_LI;
|
|
|
|
|
if (hc->ctype == HFC_TYPE_XHFC) {
|
|
|
|
|
hc->hw.a_st_ctrl0[pt] |= 0x40 /* V_ST_PU_CTRL */;
|
|
|
|
|
HFC_outb(hc, 0x35 /* A_ST_CTRL3 */,
|
|
|
|
|
0x7c << 1 /* V_ST_PULSE */);
|
|
|
|
|
}
|
|
|
|
|
/* line setup */
|
|
|
|
|
HFC_outb(hc, A_ST_CTRL0, hc->hw.a_st_ctrl0[pt]);
|
|
|
|
|
/* disable E-channel */
|
|
|
|
@ -3990,7 +4088,7 @@ open_bchannel(struct hfc_multi *hc, struct dchannel *dch,
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
if (rq->protocol == ISDN_P_NONE)
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
if (hc->type == 1)
|
|
|
|
|
if (hc->ctype == HFC_TYPE_E1)
|
|
|
|
|
ch = rq->adr.channel;
|
|
|
|
|
else
|
|
|
|
|
ch = (rq->adr.channel - 1) + (dch->slot - 2);
|
|
|
|
@ -4081,7 +4179,7 @@ hfcm_dctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
|
|
|
|
|
switch (rq->protocol) {
|
|
|
|
|
case ISDN_P_TE_S0:
|
|
|
|
|
case ISDN_P_NT_S0:
|
|
|
|
|
if (hc->type == 1) {
|
|
|
|
|
if (hc->ctype == HFC_TYPE_E1) {
|
|
|
|
|
err = -EINVAL;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
@ -4089,7 +4187,7 @@ hfcm_dctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
|
|
|
|
|
break;
|
|
|
|
|
case ISDN_P_TE_E1:
|
|
|
|
|
case ISDN_P_NT_E1:
|
|
|
|
|
if (hc->type != 1) {
|
|
|
|
|
if (hc->ctype != HFC_TYPE_E1) {
|
|
|
|
|
err = -EINVAL;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
@ -4156,13 +4254,13 @@ init_card(struct hfc_multi *hc)
|
|
|
|
|
disable_hwirq(hc);
|
|
|
|
|
spin_unlock_irqrestore(&hc->lock, flags);
|
|
|
|
|
|
|
|
|
|
if (request_irq(hc->pci_dev->irq, hfcmulti_interrupt, IRQF_SHARED,
|
|
|
|
|
if (request_irq(hc->irq, hfcmulti_interrupt, IRQF_SHARED,
|
|
|
|
|
"HFC-multi", hc)) {
|
|
|
|
|
printk(KERN_WARNING "mISDN: Could not get interrupt %d.\n",
|
|
|
|
|
hc->pci_dev->irq);
|
|
|
|
|
hc->irq);
|
|
|
|
|
hc->irq = 0;
|
|
|
|
|
return -EIO;
|
|
|
|
|
}
|
|
|
|
|
hc->irq = hc->pci_dev->irq;
|
|
|
|
|
|
|
|
|
|
if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
|
|
|
|
|
spin_lock_irqsave(&plx_lock, plx_flags);
|
|
|
|
@ -4269,6 +4367,10 @@ setup_pci(struct hfc_multi *hc, struct pci_dev *pdev,
|
|
|
|
|
hc->ledstate = 0xAFFEAFFE;
|
|
|
|
|
hc->opticalsupport = m->opticalsupport;
|
|
|
|
|
|
|
|
|
|
hc->pci_iobase = 0;
|
|
|
|
|
hc->pci_membase = NULL;
|
|
|
|
|
hc->plx_membase = NULL;
|
|
|
|
|
|
|
|
|
|
/* set memory access methods */
|
|
|
|
|
if (m->io_mode) /* use mode from card config */
|
|
|
|
|
hc->io_mode = m->io_mode;
|
|
|
|
@ -4276,44 +4378,12 @@ setup_pci(struct hfc_multi *hc, struct pci_dev *pdev,
|
|
|
|
|
case HFC_IO_MODE_PLXSD:
|
|
|
|
|
test_and_set_bit(HFC_CHIP_PLXSD, &hc->chip);
|
|
|
|
|
hc->slots = 128; /* required */
|
|
|
|
|
/* fall through */
|
|
|
|
|
case HFC_IO_MODE_PCIMEM:
|
|
|
|
|
hc->HFC_outb = HFC_outb_pcimem;
|
|
|
|
|
hc->HFC_inb = HFC_inb_pcimem;
|
|
|
|
|
hc->HFC_inw = HFC_inw_pcimem;
|
|
|
|
|
hc->HFC_wait = HFC_wait_pcimem;
|
|
|
|
|
hc->read_fifo = read_fifo_pcimem;
|
|
|
|
|
hc->write_fifo = write_fifo_pcimem;
|
|
|
|
|
break;
|
|
|
|
|
case HFC_IO_MODE_REGIO:
|
|
|
|
|
hc->HFC_outb = HFC_outb_regio;
|
|
|
|
|
hc->HFC_inb = HFC_inb_regio;
|
|
|
|
|
hc->HFC_inw = HFC_inw_regio;
|
|
|
|
|
hc->HFC_wait = HFC_wait_regio;
|
|
|
|
|
hc->read_fifo = read_fifo_regio;
|
|
|
|
|
hc->write_fifo = write_fifo_regio;
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
printk(KERN_WARNING "HFC-multi: Invalid IO mode.\n");
|
|
|
|
|
pci_disable_device(hc->pci_dev);
|
|
|
|
|
return -EIO;
|
|
|
|
|
}
|
|
|
|
|
hc->HFC_outb_nodebug = hc->HFC_outb;
|
|
|
|
|
hc->HFC_inb_nodebug = hc->HFC_inb;
|
|
|
|
|
hc->HFC_inw_nodebug = hc->HFC_inw;
|
|
|
|
|
hc->HFC_wait_nodebug = hc->HFC_wait;
|
|
|
|
|
#ifdef HFC_REGISTER_DEBUG
|
|
|
|
|
hc->HFC_outb = HFC_outb_debug;
|
|
|
|
|
hc->HFC_inb = HFC_inb_debug;
|
|
|
|
|
hc->HFC_inw = HFC_inw_debug;
|
|
|
|
|
hc->HFC_wait = HFC_wait_debug;
|
|
|
|
|
#endif
|
|
|
|
|
hc->pci_iobase = 0;
|
|
|
|
|
hc->pci_membase = NULL;
|
|
|
|
|
hc->plx_membase = NULL;
|
|
|
|
|
|
|
|
|
|
switch (hc->io_mode) {
|
|
|
|
|
case HFC_IO_MODE_PLXSD:
|
|
|
|
|
hc->plx_origmembase = hc->pci_dev->resource[0].start;
|
|
|
|
|
/* MEMBASE 1 is PLX PCI Bridge */
|
|
|
|
|
|
|
|
|
@ -4361,6 +4431,12 @@ setup_pci(struct hfc_multi *hc, struct pci_dev *pdev,
|
|
|
|
|
pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_MEMIO);
|
|
|
|
|
break;
|
|
|
|
|
case HFC_IO_MODE_PCIMEM:
|
|
|
|
|
hc->HFC_outb = HFC_outb_pcimem;
|
|
|
|
|
hc->HFC_inb = HFC_inb_pcimem;
|
|
|
|
|
hc->HFC_inw = HFC_inw_pcimem;
|
|
|
|
|
hc->HFC_wait = HFC_wait_pcimem;
|
|
|
|
|
hc->read_fifo = read_fifo_pcimem;
|
|
|
|
|
hc->write_fifo = write_fifo_pcimem;
|
|
|
|
|
hc->pci_origmembase = hc->pci_dev->resource[1].start;
|
|
|
|
|
if (!hc->pci_origmembase) {
|
|
|
|
|
printk(KERN_WARNING
|
|
|
|
@ -4377,12 +4453,18 @@ setup_pci(struct hfc_multi *hc, struct pci_dev *pdev,
|
|
|
|
|
pci_disable_device(hc->pci_dev);
|
|
|
|
|
return -EIO;
|
|
|
|
|
}
|
|
|
|
|
printk(KERN_INFO "card %d: defined at MEMBASE %#lx (%#lx) IRQ %d "
|
|
|
|
|
"HZ %d leds-type %d\n", hc->id, (u_long)hc->pci_membase,
|
|
|
|
|
printk(KERN_INFO "card %d: defined at MEMBASE %#lx (%#lx) IRQ "
|
|
|
|
|
"%d HZ %d leds-type %d\n", hc->id, (u_long)hc->pci_membase,
|
|
|
|
|
hc->pci_origmembase, hc->pci_dev->irq, HZ, hc->leds);
|
|
|
|
|
pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_MEMIO);
|
|
|
|
|
break;
|
|
|
|
|
case HFC_IO_MODE_REGIO:
|
|
|
|
|
hc->HFC_outb = HFC_outb_regio;
|
|
|
|
|
hc->HFC_inb = HFC_inb_regio;
|
|
|
|
|
hc->HFC_inw = HFC_inw_regio;
|
|
|
|
|
hc->HFC_wait = HFC_wait_regio;
|
|
|
|
|
hc->read_fifo = read_fifo_regio;
|
|
|
|
|
hc->write_fifo = write_fifo_regio;
|
|
|
|
|
hc->pci_iobase = (u_int) hc->pci_dev->resource[0].start;
|
|
|
|
|
if (!hc->pci_iobase) {
|
|
|
|
|
printk(KERN_WARNING
|
|
|
|
@ -4464,7 +4546,7 @@ release_port(struct hfc_multi *hc, struct dchannel *dch)
|
|
|
|
|
dch->timer.function = NULL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (hc->type == 1) { /* E1 */
|
|
|
|
|
if (hc->ctype == HFC_TYPE_E1) { /* E1 */
|
|
|
|
|
/* remove sync */
|
|
|
|
|
if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
|
|
|
|
|
hc->syncronized = 0;
|
|
|
|
@ -4863,9 +4945,15 @@ init_multi_port(struct hfc_multi *hc, int pt)
|
|
|
|
|
test_and_set_bit(HFC_CFG_DIS_ECHANNEL,
|
|
|
|
|
&hc->chan[i + 2].cfg);
|
|
|
|
|
}
|
|
|
|
|
snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-%ds.%d-%d",
|
|
|
|
|
hc->type, HFC_cnt + 1, pt + 1);
|
|
|
|
|
ret = mISDN_register_device(&dch->dev, &hc->pci_dev->dev, name);
|
|
|
|
|
if (hc->ctype == HFC_TYPE_XHFC) {
|
|
|
|
|
snprintf(name, MISDN_MAX_IDLEN - 1, "xhfc.%d-%d",
|
|
|
|
|
HFC_cnt + 1, pt + 1);
|
|
|
|
|
ret = mISDN_register_device(&dch->dev, NULL, name);
|
|
|
|
|
} else {
|
|
|
|
|
snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-%ds.%d-%d",
|
|
|
|
|
hc->ctype, HFC_cnt + 1, pt + 1);
|
|
|
|
|
ret = mISDN_register_device(&dch->dev, &hc->pci_dev->dev, name);
|
|
|
|
|
}
|
|
|
|
|
if (ret)
|
|
|
|
|
goto free_chan;
|
|
|
|
|
hc->created[pt] = 1;
|
|
|
|
@ -4876,9 +4964,9 @@ free_chan:
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int
|
|
|
|
|
hfcmulti_init(struct pci_dev *pdev, const struct pci_device_id *ent)
|
|
|
|
|
hfcmulti_init(struct hm_map *m, struct pci_dev *pdev,
|
|
|
|
|
const struct pci_device_id *ent)
|
|
|
|
|
{
|
|
|
|
|
struct hm_map *m = (struct hm_map *)ent->driver_data;
|
|
|
|
|
int ret_err = 0;
|
|
|
|
|
int pt;
|
|
|
|
|
struct hfc_multi *hc;
|
|
|
|
@ -4913,16 +5001,18 @@ hfcmulti_init(struct pci_dev *pdev, const struct pci_device_id *ent)
|
|
|
|
|
}
|
|
|
|
|
spin_lock_init(&hc->lock);
|
|
|
|
|
hc->mtyp = m;
|
|
|
|
|
hc->type = m->type;
|
|
|
|
|
hc->ctype = m->type;
|
|
|
|
|
hc->ports = m->ports;
|
|
|
|
|
hc->id = HFC_cnt;
|
|
|
|
|
hc->pcm = pcm[HFC_cnt];
|
|
|
|
|
hc->io_mode = iomode[HFC_cnt];
|
|
|
|
|
if (dslot[HFC_cnt] < 0 && hc->type == 1) {
|
|
|
|
|
if (dslot[HFC_cnt] < 0 && hc->ctype == HFC_TYPE_E1) {
|
|
|
|
|
hc->dslot = 0;
|
|
|
|
|
printk(KERN_INFO "HFC-E1 card has disabled D-channel, but "
|
|
|
|
|
"31 B-channels\n");
|
|
|
|
|
} if (dslot[HFC_cnt] > 0 && dslot[HFC_cnt] < 32 && hc->type == 1) {
|
|
|
|
|
}
|
|
|
|
|
if (dslot[HFC_cnt] > 0 && dslot[HFC_cnt] < 32
|
|
|
|
|
&& hc->ctype == HFC_TYPE_E1) {
|
|
|
|
|
hc->dslot = dslot[HFC_cnt];
|
|
|
|
|
printk(KERN_INFO "HFC-E1 card has alternating D-channel on "
|
|
|
|
|
"time slot %d\n", dslot[HFC_cnt]);
|
|
|
|
@ -4944,8 +5034,11 @@ hfcmulti_init(struct pci_dev *pdev, const struct pci_device_id *ent)
|
|
|
|
|
for (i = 0; i < (poll >> 1); i++)
|
|
|
|
|
hc->silence_data[i] = hc->silence;
|
|
|
|
|
|
|
|
|
|
if (!(type[HFC_cnt] & 0x200))
|
|
|
|
|
test_and_set_bit(HFC_CHIP_DTMF, &hc->chip);
|
|
|
|
|
if (hc->ctype != HFC_TYPE_XHFC) {
|
|
|
|
|
if (!(type[HFC_cnt] & 0x200))
|
|
|
|
|
test_and_set_bit(HFC_CHIP_DTMF, &hc->chip);
|
|
|
|
|
test_and_set_bit(HFC_CHIP_CONF, &hc->chip);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (type[HFC_cnt] & 0x800)
|
|
|
|
|
test_and_set_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
|
|
|
|
@ -4969,8 +5062,18 @@ hfcmulti_init(struct pci_dev *pdev, const struct pci_device_id *ent)
|
|
|
|
|
printk(KERN_NOTICE "Watchdog enabled\n");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* setup pci, hc->slots may change due to PLXSD */
|
|
|
|
|
ret_err = setup_pci(hc, pdev, ent);
|
|
|
|
|
if (pdev && ent)
|
|
|
|
|
/* setup pci, hc->slots may change due to PLXSD */
|
|
|
|
|
ret_err = setup_pci(hc, pdev, ent);
|
|
|
|
|
else
|
|
|
|
|
#ifdef CONFIG_MISDN_HFCMULTI_8xx
|
|
|
|
|
ret_err = setup_embedded(hc, m);
|
|
|
|
|
#else
|
|
|
|
|
{
|
|
|
|
|
printk(KERN_WARNING "Embedded IO Mode not selected\n");
|
|
|
|
|
ret_err = -EIO;
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
if (ret_err) {
|
|
|
|
|
if (hc == syncmaster)
|
|
|
|
|
syncmaster = NULL;
|
|
|
|
@ -4978,7 +5081,17 @@ hfcmulti_init(struct pci_dev *pdev, const struct pci_device_id *ent)
|
|
|
|
|
return ret_err;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* crate channels */
|
|
|
|
|
hc->HFC_outb_nodebug = hc->HFC_outb;
|
|
|
|
|
hc->HFC_inb_nodebug = hc->HFC_inb;
|
|
|
|
|
hc->HFC_inw_nodebug = hc->HFC_inw;
|
|
|
|
|
hc->HFC_wait_nodebug = hc->HFC_wait;
|
|
|
|
|
#ifdef HFC_REGISTER_DEBUG
|
|
|
|
|
hc->HFC_outb = HFC_outb_debug;
|
|
|
|
|
hc->HFC_inb = HFC_inb_debug;
|
|
|
|
|
hc->HFC_inw = HFC_inw_debug;
|
|
|
|
|
hc->HFC_wait = HFC_wait_debug;
|
|
|
|
|
#endif
|
|
|
|
|
/* create channels */
|
|
|
|
|
for (pt = 0; pt < hc->ports; pt++) {
|
|
|
|
|
if (Port_cnt >= MAX_PORTS) {
|
|
|
|
|
printk(KERN_ERR "too many ports (max=%d).\n",
|
|
|
|
@ -4986,7 +5099,7 @@ hfcmulti_init(struct pci_dev *pdev, const struct pci_device_id *ent)
|
|
|
|
|
ret_err = -EINVAL;
|
|
|
|
|
goto free_card;
|
|
|
|
|
}
|
|
|
|
|
if (hc->type == 1)
|
|
|
|
|
if (hc->ctype == HFC_TYPE_E1)
|
|
|
|
|
ret_err = init_e1_port(hc, m);
|
|
|
|
|
else
|
|
|
|
|
ret_err = init_multi_port(hc, pt);
|
|
|
|
@ -5070,6 +5183,7 @@ hfcmulti_init(struct pci_dev *pdev, const struct pci_device_id *ent)
|
|
|
|
|
hc->iclock = mISDN_register_clock("HFCMulti", 0, clockctl, hc);
|
|
|
|
|
|
|
|
|
|
/* initialize hardware */
|
|
|
|
|
hc->irq = (m->irq) ? : hc->pci_dev->irq;
|
|
|
|
|
ret_err = init_card(hc);
|
|
|
|
|
if (ret_err) {
|
|
|
|
|
printk(KERN_ERR "init card returns %d\n", ret_err);
|
|
|
|
@ -5120,45 +5234,47 @@ static void __devexit hfc_remove_pci(struct pci_dev *pdev)
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#define VENDOR_PRIM "PrimuX"
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static const struct hm_map hfcm_map[] = {
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/*0*/ {VENDOR_BN, "HFC-1S Card (mini PCI)", 4, 1, 1, 3, 0, DIP_4S, 0},
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/*1*/ {VENDOR_BN, "HFC-2S Card", 4, 2, 1, 3, 0, DIP_4S, 0},
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/*2*/ {VENDOR_BN, "HFC-2S Card (mini PCI)", 4, 2, 1, 3, 0, DIP_4S, 0},
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/*3*/ {VENDOR_BN, "HFC-4S Card", 4, 4, 1, 2, 0, DIP_4S, 0},
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/*4*/ {VENDOR_BN, "HFC-4S Card (mini PCI)", 4, 4, 1, 2, 0, 0, 0},
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/*5*/ {VENDOR_CCD, "HFC-4S Eval (old)", 4, 4, 0, 0, 0, 0, 0},
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/*6*/ {VENDOR_CCD, "HFC-4S IOB4ST", 4, 4, 1, 2, 0, DIP_4S, 0},
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/*7*/ {VENDOR_CCD, "HFC-4S", 4, 4, 1, 2, 0, 0, 0},
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/*8*/ {VENDOR_DIG, "HFC-4S Card", 4, 4, 0, 2, 0, 0, HFC_IO_MODE_REGIO},
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/*9*/ {VENDOR_CCD, "HFC-4S Swyx 4xS0 SX2 QuadBri", 4, 4, 1, 2, 0, 0, 0},
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/*10*/ {VENDOR_JH, "HFC-4S (junghanns 2.0)", 4, 4, 1, 2, 0, 0, 0},
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/*11*/ {VENDOR_PRIM, "HFC-2S Primux Card", 4, 2, 0, 0, 0, 0, 0},
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/*0*/ {VENDOR_BN, "HFC-1S Card (mini PCI)", 4, 1, 1, 3, 0, DIP_4S, 0, 0},
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/*1*/ {VENDOR_BN, "HFC-2S Card", 4, 2, 1, 3, 0, DIP_4S, 0, 0},
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/*2*/ {VENDOR_BN, "HFC-2S Card (mini PCI)", 4, 2, 1, 3, 0, DIP_4S, 0, 0},
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/*3*/ {VENDOR_BN, "HFC-4S Card", 4, 4, 1, 2, 0, DIP_4S, 0, 0},
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/*4*/ {VENDOR_BN, "HFC-4S Card (mini PCI)", 4, 4, 1, 2, 0, 0, 0, 0},
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/*5*/ {VENDOR_CCD, "HFC-4S Eval (old)", 4, 4, 0, 0, 0, 0, 0, 0},
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/*6*/ {VENDOR_CCD, "HFC-4S IOB4ST", 4, 4, 1, 2, 0, DIP_4S, 0, 0},
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/*7*/ {VENDOR_CCD, "HFC-4S", 4, 4, 1, 2, 0, 0, 0, 0},
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/*8*/ {VENDOR_DIG, "HFC-4S Card", 4, 4, 0, 2, 0, 0, HFC_IO_MODE_REGIO, 0},
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/*9*/ {VENDOR_CCD, "HFC-4S Swyx 4xS0 SX2 QuadBri", 4, 4, 1, 2, 0, 0, 0, 0},
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/*10*/ {VENDOR_JH, "HFC-4S (junghanns 2.0)", 4, 4, 1, 2, 0, 0, 0, 0},
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/*11*/ {VENDOR_PRIM, "HFC-2S Primux Card", 4, 2, 0, 0, 0, 0, 0, 0},
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/*12*/ {VENDOR_BN, "HFC-8S Card", 8, 8, 1, 0, 0, 0, 0},
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/*12*/ {VENDOR_BN, "HFC-8S Card", 8, 8, 1, 0, 0, 0, 0, 0},
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/*13*/ {VENDOR_BN, "HFC-8S Card (+)", 8, 8, 1, 8, 0, DIP_8S,
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HFC_IO_MODE_REGIO},
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/*14*/ {VENDOR_CCD, "HFC-8S Eval (old)", 8, 8, 0, 0, 0, 0, 0},
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/*15*/ {VENDOR_CCD, "HFC-8S IOB4ST Recording", 8, 8, 1, 0, 0, 0, 0},
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HFC_IO_MODE_REGIO, 0},
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/*14*/ {VENDOR_CCD, "HFC-8S Eval (old)", 8, 8, 0, 0, 0, 0, 0, 0},
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/*15*/ {VENDOR_CCD, "HFC-8S IOB4ST Recording", 8, 8, 1, 0, 0, 0, 0, 0},
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/*16*/ {VENDOR_CCD, "HFC-8S IOB8ST", 8, 8, 1, 0, 0, 0, 0},
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/*17*/ {VENDOR_CCD, "HFC-8S", 8, 8, 1, 0, 0, 0, 0},
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/*18*/ {VENDOR_CCD, "HFC-8S", 8, 8, 1, 0, 0, 0, 0},
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/*16*/ {VENDOR_CCD, "HFC-8S IOB8ST", 8, 8, 1, 0, 0, 0, 0, 0},
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/*17*/ {VENDOR_CCD, "HFC-8S", 8, 8, 1, 0, 0, 0, 0, 0},
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/*18*/ {VENDOR_CCD, "HFC-8S", 8, 8, 1, 0, 0, 0, 0, 0},
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/*19*/ {VENDOR_BN, "HFC-E1 Card", 1, 1, 0, 1, 0, DIP_E1, 0},
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/*20*/ {VENDOR_BN, "HFC-E1 Card (mini PCI)", 1, 1, 0, 1, 0, 0, 0},
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/*21*/ {VENDOR_BN, "HFC-E1+ Card (Dual)", 1, 1, 0, 1, 0, DIP_E1, 0},
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/*22*/ {VENDOR_BN, "HFC-E1 Card (Dual)", 1, 1, 0, 1, 0, DIP_E1, 0},
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/*19*/ {VENDOR_BN, "HFC-E1 Card", 1, 1, 0, 1, 0, DIP_E1, 0, 0},
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/*20*/ {VENDOR_BN, "HFC-E1 Card (mini PCI)", 1, 1, 0, 1, 0, 0, 0, 0},
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/*21*/ {VENDOR_BN, "HFC-E1+ Card (Dual)", 1, 1, 0, 1, 0, DIP_E1, 0, 0},
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/*22*/ {VENDOR_BN, "HFC-E1 Card (Dual)", 1, 1, 0, 1, 0, DIP_E1, 0, 0},
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/*23*/ {VENDOR_CCD, "HFC-E1 Eval (old)", 1, 1, 0, 0, 0, 0, 0},
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/*24*/ {VENDOR_CCD, "HFC-E1 IOB1E1", 1, 1, 0, 1, 0, 0, 0},
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/*25*/ {VENDOR_CCD, "HFC-E1", 1, 1, 0, 1, 0, 0, 0},
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/*23*/ {VENDOR_CCD, "HFC-E1 Eval (old)", 1, 1, 0, 0, 0, 0, 0, 0},
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/*24*/ {VENDOR_CCD, "HFC-E1 IOB1E1", 1, 1, 0, 1, 0, 0, 0, 0},
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/*25*/ {VENDOR_CCD, "HFC-E1", 1, 1, 0, 1, 0, 0, 0, 0},
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/*26*/ {VENDOR_CCD, "HFC-4S Speech Design", 4, 4, 0, 0, 0, 0,
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HFC_IO_MODE_PLXSD},
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HFC_IO_MODE_PLXSD, 0},
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/*27*/ {VENDOR_CCD, "HFC-E1 Speech Design", 1, 1, 0, 0, 0, 0,
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HFC_IO_MODE_PLXSD},
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/*28*/ {VENDOR_CCD, "HFC-4S OpenVox", 4, 4, 1, 0, 0, 0, 0},
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/*29*/ {VENDOR_CCD, "HFC-2S OpenVox", 4, 2, 1, 0, 0, 0, 0},
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/*30*/ {VENDOR_CCD, "HFC-8S OpenVox", 8, 8, 1, 0, 0, 0, 0},
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HFC_IO_MODE_PLXSD, 0},
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/*28*/ {VENDOR_CCD, "HFC-4S OpenVox", 4, 4, 1, 0, 0, 0, 0, 0},
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/*29*/ {VENDOR_CCD, "HFC-2S OpenVox", 4, 2, 1, 0, 0, 0, 0, 0},
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/*30*/ {VENDOR_CCD, "HFC-8S OpenVox", 8, 8, 1, 0, 0, 0, 0, 0},
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/*31*/ {VENDOR_CCD, "XHFC-4S Speech Design", 5, 4, 0, 0, 0, 0,
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HFC_IO_MODE_EMBSD, XHFC_IRQ},
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};
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#undef H
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@ -5265,7 +5381,7 @@ hfcmulti_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
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"Please contact the driver maintainer for support.\n");
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return -ENODEV;
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}
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ret = hfcmulti_init(pdev, ent);
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ret = hfcmulti_init(m, pdev, ent);
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if (ret)
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return ret;
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HFC_cnt++;
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@ -5295,6 +5411,8 @@ static int __init
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HFCmulti_init(void)
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{
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int err;
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int i, xhfc = 0;
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struct hm_map m;
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printk(KERN_INFO "mISDN: HFC-multi driver %s\n", HFC_MULTI_VERSION);
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@ -5342,11 +5460,43 @@ HFCmulti_init(void)
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if (!clock)
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clock = 1;
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/* Register the embedded devices.
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* This should be done before the PCI cards registration */
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switch (hwid) {
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case HWID_MINIP4:
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xhfc = 1;
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m = hfcm_map[31];
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break;
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case HWID_MINIP8:
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xhfc = 2;
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m = hfcm_map[31];
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break;
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case HWID_MINIP16:
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xhfc = 4;
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m = hfcm_map[31];
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break;
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default:
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xhfc = 0;
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}
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for (i = 0; i < xhfc; ++i) {
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err = hfcmulti_init(&m, NULL, NULL);
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if (err) {
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printk(KERN_ERR "error registering embedded driver: "
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"%x\n", err);
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return -err;
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}
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HFC_cnt++;
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printk(KERN_INFO "%d devices registered\n", HFC_cnt);
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}
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/* Register the PCI cards */
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err = pci_register_driver(&hfcmultipci_driver);
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if (err < 0) {
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printk(KERN_ERR "error registering pci driver: %x\n", err);
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return err;
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}
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return 0;
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}
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