Merge branch 'linus' into timers/core
Pick up the latest fixes and refresh the branch. Signed-off-by: Ingo Molnar <mingo@kernel.org>
This commit is contained in:
Ingo Molnar
Коммит
dba861461f
5
CREDITS
5
CREDITS
|
|
@ -655,6 +655,11 @@ S: Stanford University
|
|||
S: Stanford, California 94305
|
||||
S: USA
|
||||
|
||||
N: Carlos Chinea
|
||||
E: carlos.chinea@nokia.com
|
||||
E: cch.devel@gmail.com
|
||||
D: Author of HSI Subsystem
|
||||
|
||||
N: Randolph Chung
|
||||
E: tausq@debian.org
|
||||
D: Linux/PA-RISC hacker
|
||||
|
|
|
|||
|
|
@ -73,7 +73,8 @@ range from zero to the maximal number of valid planes for the currently active
|
|||
format. For the single-planar API, applications must set <structfield> plane
|
||||
</structfield> to zero. Additional flags may be posted in the <structfield>
|
||||
flags </structfield> field. Refer to a manual for open() for details.
|
||||
Currently only O_CLOEXEC is supported. All other fields must be set to zero.
|
||||
Currently only O_CLOEXEC, O_RDONLY, O_WRONLY, and O_RDWR are supported. All
|
||||
other fields must be set to zero.
|
||||
In the case of multi-planar API, every plane is exported separately using
|
||||
multiple <constant> VIDIOC_EXPBUF </constant> calls. </para>
|
||||
|
||||
|
|
@ -170,8 +171,9 @@ multi-planar API. Otherwise this value must be set to zero. </entry>
|
|||
<entry>__u32</entry>
|
||||
<entry><structfield>flags</structfield></entry>
|
||||
<entry>Flags for the newly created file, currently only <constant>
|
||||
O_CLOEXEC </constant> is supported, refer to the manual of open() for more
|
||||
details.</entry>
|
||||
O_CLOEXEC </constant>, <constant>O_RDONLY</constant>, <constant>O_WRONLY
|
||||
</constant>, and <constant>O_RDWR</constant> are supported, refer to the manual
|
||||
of open() for more details.</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry>__s32</entry>
|
||||
|
|
|
|||
|
|
@ -164,10 +164,10 @@ This points to a number of methods, all of which need to be provided:
|
|||
|
||||
(4) Diff the index keys of two objects.
|
||||
|
||||
int (*diff_objects)(const void *a, const void *b);
|
||||
int (*diff_objects)(const void *object, const void *index_key);
|
||||
|
||||
Return the bit position at which the index keys of two objects differ or
|
||||
-1 if they are the same.
|
||||
Return the bit position at which the index key of the specified object
|
||||
differs from the given index key or -1 if they are the same.
|
||||
|
||||
|
||||
(5) Free an object.
|
||||
|
|
|
|||
|
|
@ -0,0 +1,72 @@
|
|||
Null block device driver
|
||||
================================================================================
|
||||
|
||||
I. Overview
|
||||
|
||||
The null block device (/dev/nullb*) is used for benchmarking the various
|
||||
block-layer implementations. It emulates a block device of X gigabytes in size.
|
||||
The following instances are possible:
|
||||
|
||||
Single-queue block-layer
|
||||
- Request-based.
|
||||
- Single submission queue per device.
|
||||
- Implements IO scheduling algorithms (CFQ, Deadline, noop).
|
||||
Multi-queue block-layer
|
||||
- Request-based.
|
||||
- Configurable submission queues per device.
|
||||
No block-layer (Known as bio-based)
|
||||
- Bio-based. IO requests are submitted directly to the device driver.
|
||||
- Directly accepts bio data structure and returns them.
|
||||
|
||||
All of them have a completion queue for each core in the system.
|
||||
|
||||
II. Module parameters applicable for all instances:
|
||||
|
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queue_mode=[0-2]: Default: 2-Multi-queue
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||||
Selects which block-layer the module should instantiate with.
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||||
|
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0: Bio-based.
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||||
1: Single-queue.
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2: Multi-queue.
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|
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home_node=[0--nr_nodes]: Default: NUMA_NO_NODE
|
||||
Selects what CPU node the data structures are allocated from.
|
||||
|
||||
gb=[Size in GB]: Default: 250GB
|
||||
The size of the device reported to the system.
|
||||
|
||||
bs=[Block size (in bytes)]: Default: 512 bytes
|
||||
The block size reported to the system.
|
||||
|
||||
nr_devices=[Number of devices]: Default: 2
|
||||
Number of block devices instantiated. They are instantiated as /dev/nullb0,
|
||||
etc.
|
||||
|
||||
irq_mode=[0-2]: Default: 1-Soft-irq
|
||||
The completion mode used for completing IOs to the block-layer.
|
||||
|
||||
0: None.
|
||||
1: Soft-irq. Uses IPI to complete IOs across CPU nodes. Simulates the overhead
|
||||
when IOs are issued from another CPU node than the home the device is
|
||||
connected to.
|
||||
2: Timer: Waits a specific period (completion_nsec) for each IO before
|
||||
completion.
|
||||
|
||||
completion_nsec=[ns]: Default: 10.000ns
|
||||
Combined with irq_mode=2 (timer). The time each completion event must wait.
|
||||
|
||||
submit_queues=[0..nr_cpus]:
|
||||
The number of submission queues attached to the device driver. If unset, it
|
||||
defaults to 1 on single-queue and bio-based instances. For multi-queue,
|
||||
it is ignored when use_per_node_hctx module parameter is 1.
|
||||
|
||||
hw_queue_depth=[0..qdepth]: Default: 64
|
||||
The hardware queue depth of the device.
|
||||
|
||||
III: Multi-queue specific parameters
|
||||
|
||||
use_per_node_hctx=[0/1]: Default: 0
|
||||
0: The number of submit queues are set to the value of the submit_queues
|
||||
parameter.
|
||||
1: The multi-queue block layer is instantiated with a hardware dispatch
|
||||
queue for each CPU node in the system.
|
||||
|
|
@ -266,10 +266,12 @@ E.g.
|
|||
Invalidation is removing an entry from the cache without writing it
|
||||
back. Cache blocks can be invalidated via the invalidate_cblocks
|
||||
message, which takes an arbitrary number of cblock ranges. Each cblock
|
||||
must be expressed as a decimal value, in the future a variant message
|
||||
that takes cblock ranges expressed in hexidecimal may be needed to
|
||||
better support efficient invalidation of larger caches. The cache must
|
||||
be in passthrough mode when invalidate_cblocks is used.
|
||||
range's end value is "one past the end", meaning 5-10 expresses a range
|
||||
of values from 5 to 9. Each cblock must be expressed as a decimal
|
||||
value, in the future a variant message that takes cblock ranges
|
||||
expressed in hexidecimal may be needed to better support efficient
|
||||
invalidation of larger caches. The cache must be in passthrough mode
|
||||
when invalidate_cblocks is used.
|
||||
|
||||
invalidate_cblocks [<cblock>|<cblock begin>-<cblock end>]*
|
||||
|
||||
|
|
|
|||
|
|
@ -7,10 +7,18 @@ The MPU contain CPUs, GIC, L2 cache and a local PRCM.
|
|||
Required properties:
|
||||
- compatible : Should be "ti,omap3-mpu" for OMAP3
|
||||
Should be "ti,omap4-mpu" for OMAP4
|
||||
Should be "ti,omap5-mpu" for OMAP5
|
||||
- ti,hwmods: "mpu"
|
||||
|
||||
Examples:
|
||||
|
||||
- For an OMAP5 SMP system:
|
||||
|
||||
mpu {
|
||||
compatible = "ti,omap5-mpu";
|
||||
ti,hwmods = "mpu"
|
||||
};
|
||||
|
||||
- For an OMAP4 SMP system:
|
||||
|
||||
mpu {
|
||||
|
|
|
|||
|
|
@ -7,6 +7,7 @@ representation in the device tree should be done as under:-
|
|||
Required properties:
|
||||
|
||||
- compatible : should be one of
|
||||
"arm,armv8-pmuv3"
|
||||
"arm,cortex-a15-pmu"
|
||||
"arm,cortex-a9-pmu"
|
||||
"arm,cortex-a8-pmu"
|
||||
|
|
|
|||
|
|
@ -49,7 +49,7 @@ adc@12D10000 {
|
|||
/* NTC thermistor is a hwmon device */
|
||||
ncp15wb473@0 {
|
||||
compatible = "ntc,ncp15wb473";
|
||||
pullup-uV = <1800000>;
|
||||
pullup-uv = <1800000>;
|
||||
pullup-ohm = <47000>;
|
||||
pulldown-ohm = <0>;
|
||||
io-channels = <&adc 4>;
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@ SoC's in the Exynos4 family.
|
|||
|
||||
Required Properties:
|
||||
|
||||
- comptible: should be one of the following.
|
||||
- compatible: should be one of the following.
|
||||
- "samsung,exynos4210-clock" - controller compatible with Exynos4210 SoC.
|
||||
- "samsung,exynos4412-clock" - controller compatible with Exynos4412 SoC.
|
||||
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@ controllers within the Exynos5250 SoC.
|
|||
|
||||
Required Properties:
|
||||
|
||||
- comptible: should be one of the following.
|
||||
- compatible: should be one of the following.
|
||||
- "samsung,exynos5250-clock" - controller compatible with Exynos5250 SoC.
|
||||
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
|
|
@ -159,6 +159,8 @@ clock which they consume.
|
|||
mixer 343
|
||||
hdmi 344
|
||||
g2d 345
|
||||
mdma0 346
|
||||
smmu_mdma0 347
|
||||
|
||||
|
||||
[Clock Muxes]
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@ controllers within the Exynos5420 SoC.
|
|||
|
||||
Required Properties:
|
||||
|
||||
- comptible: should be one of the following.
|
||||
- compatible: should be one of the following.
|
||||
- "samsung,exynos5420-clock" - controller compatible with Exynos5420 SoC.
|
||||
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@ controllers within the Exynos5440 SoC.
|
|||
|
||||
Required Properties:
|
||||
|
||||
- comptible: should be "samsung,exynos5440-clock".
|
||||
- compatible: should be "samsung,exynos5440-clock".
|
||||
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
|
|
|
|||
|
|
@ -5,16 +5,42 @@ This is for the non-QE/CPM/GUTs GPIO controllers as found on
|
|||
|
||||
Every GPIO controller node must have #gpio-cells property defined,
|
||||
this information will be used to translate gpio-specifiers.
|
||||
See bindings/gpio/gpio.txt for details of how to specify GPIO
|
||||
information for devices.
|
||||
|
||||
The GPIO module usually is connected to the SoC's internal interrupt
|
||||
controller, see bindings/interrupt-controller/interrupts.txt (the
|
||||
interrupt client nodes section) for details how to specify this GPIO
|
||||
module's interrupt.
|
||||
|
||||
The GPIO module may serve as another interrupt controller (cascaded to
|
||||
the SoC's internal interrupt controller). See the interrupt controller
|
||||
nodes section in bindings/interrupt-controller/interrupts.txt for
|
||||
details.
|
||||
|
||||
Required properties:
|
||||
- compatible : "fsl,<CHIP>-gpio" followed by "fsl,mpc8349-gpio" for
|
||||
83xx, "fsl,mpc8572-gpio" for 85xx and "fsl,mpc8610-gpio" for 86xx.
|
||||
- #gpio-cells : Should be two. The first cell is the pin number and the
|
||||
second cell is used to specify optional parameters (currently unused).
|
||||
- interrupts : Interrupt mapping for GPIO IRQ.
|
||||
- interrupt-parent : Phandle for the interrupt controller that
|
||||
- compatible: "fsl,<chip>-gpio" followed by "fsl,mpc8349-gpio"
|
||||
for 83xx, "fsl,mpc8572-gpio" for 85xx, or
|
||||
"fsl,mpc8610-gpio" for 86xx.
|
||||
- #gpio-cells: Should be two. The first cell is the pin number
|
||||
and the second cell is used to specify optional
|
||||
parameters (currently unused).
|
||||
- interrupt-parent: Phandle for the interrupt controller that
|
||||
services interrupts for this device.
|
||||
- gpio-controller : Marks the port as GPIO controller.
|
||||
- interrupts: Interrupt mapping for GPIO IRQ.
|
||||
- gpio-controller: Marks the port as GPIO controller.
|
||||
|
||||
Optional properties:
|
||||
- interrupt-controller: Empty boolean property which marks the GPIO
|
||||
module as an IRQ controller.
|
||||
- #interrupt-cells: Should be two. Defines the number of integer
|
||||
cells required to specify an interrupt within
|
||||
this interrupt controller. The first cell
|
||||
defines the pin number, the second cell
|
||||
defines additional flags (trigger type,
|
||||
trigger polarity). Note that the available
|
||||
set of trigger conditions supported by the
|
||||
GPIO module depends on the actual SoC.
|
||||
|
||||
Example of gpio-controller nodes for a MPC8347 SoC:
|
||||
|
||||
|
|
@ -22,39 +48,27 @@ Example of gpio-controller nodes for a MPC8347 SoC:
|
|||
#gpio-cells = <2>;
|
||||
compatible = "fsl,mpc8347-gpio", "fsl,mpc8349-gpio";
|
||||
reg = <0xc00 0x100>;
|
||||
interrupts = <74 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <74 0x8>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio2: gpio-controller@d00 {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "fsl,mpc8347-gpio", "fsl,mpc8349-gpio";
|
||||
reg = <0xd00 0x100>;
|
||||
interrupts = <75 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <75 0x8>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
See booting-without-of.txt for details of how to specify GPIO
|
||||
information for devices.
|
||||
|
||||
To use GPIO pins as interrupt sources for peripherals, specify the
|
||||
GPIO controller as the interrupt parent and define GPIO number +
|
||||
trigger mode using the interrupts property, which is defined like
|
||||
this:
|
||||
|
||||
interrupts = <number trigger>, where:
|
||||
- number: GPIO pin (0..31)
|
||||
- trigger: trigger mode:
|
||||
2 = trigger on falling edge
|
||||
3 = trigger on both edges
|
||||
|
||||
Example of device using this is:
|
||||
Example of a peripheral using the GPIO module as an IRQ controller:
|
||||
|
||||
funkyfpga@0 {
|
||||
compatible = "funky-fpga";
|
||||
...
|
||||
interrupts = <4 3>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <4 3>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,54 @@
|
|||
* TI MMC host controller for OMAP1 and 2420
|
||||
|
||||
The MMC Host Controller on TI OMAP1 and 2420 family provides
|
||||
an interface for MMC, SD, and SDIO types of memory cards.
|
||||
|
||||
This file documents differences between the core properties described
|
||||
by mmc.txt and the properties used by the omap mmc driver.
|
||||
|
||||
Note that this driver will not work with omap2430 or later omaps,
|
||||
please see the omap hsmmc driver for the current omaps.
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be "ti,omap2420-mmc", for OMAP2420 controllers
|
||||
- ti,hwmods: For 2420, must be "msdi<n>", where n is controller
|
||||
instance starting 1
|
||||
|
||||
Examples:
|
||||
|
||||
msdi1: mmc@4809c000 {
|
||||
compatible = "ti,omap2420-mmc";
|
||||
ti,hwmods = "msdi1";
|
||||
reg = <0x4809c000 0x80>;
|
||||
interrupts = <83>;
|
||||
dmas = <&sdma 61 &sdma 62>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
* TI MMC host controller for OMAP1 and 2420
|
||||
|
||||
The MMC Host Controller on TI OMAP1 and 2420 family provides
|
||||
an interface for MMC, SD, and SDIO types of memory cards.
|
||||
|
||||
This file documents differences between the core properties described
|
||||
by mmc.txt and the properties used by the omap mmc driver.
|
||||
|
||||
Note that this driver will not work with omap2430 or later omaps,
|
||||
please see the omap hsmmc driver for the current omaps.
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be "ti,omap2420-mmc", for OMAP2420 controllers
|
||||
- ti,hwmods: For 2420, must be "msdi<n>", where n is controller
|
||||
instance starting 1
|
||||
|
||||
Examples:
|
||||
|
||||
msdi1: mmc@4809c000 {
|
||||
compatible = "ti,omap2420-mmc";
|
||||
ti,hwmods = "msdi1";
|
||||
reg = <0x4809c000 0x80>;
|
||||
interrupts = <83>;
|
||||
dmas = <&sdma 61 &sdma 62>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
|
|
@ -4,7 +4,7 @@ This file provides information, what the device node
|
|||
for the davinci_emac interface contains.
|
||||
|
||||
Required properties:
|
||||
- compatible: "ti,davinci-dm6467-emac";
|
||||
- compatible: "ti,davinci-dm6467-emac" or "ti,am3517-emac"
|
||||
- reg: Offset and length of the register set for the device
|
||||
- ti,davinci-ctrl-reg-offset: offset to control register
|
||||
- ti,davinci-ctrl-mod-reg-offset: offset to control module register
|
||||
|
|
|
|||
|
|
@ -15,6 +15,7 @@ Optional properties:
|
|||
only if property "phy-reset-gpios" is available. Missing the property
|
||||
will have the duration be 1 millisecond. Numbers greater than 1000 are
|
||||
invalid and 1 millisecond will be used instead.
|
||||
- phy-supply: regulator that powers the Ethernet PHY.
|
||||
|
||||
Example:
|
||||
|
||||
|
|
@ -25,4 +26,5 @@ ethernet@83fec000 {
|
|||
phy-mode = "mii";
|
||||
phy-reset-gpios = <&gpio2 14 0>; /* GPIO2_14 */
|
||||
local-mac-address = [00 04 9F 01 1B B9];
|
||||
phy-supply = <®_fec_supply>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -8,3 +8,7 @@ Required properties:
|
|||
Optional properties:
|
||||
- phy-device : phandle to Ethernet phy
|
||||
- local-mac-address : Ethernet mac address to use
|
||||
- reg-io-width : Mask of sizes (in bytes) of the IO accesses that
|
||||
are supported on the device. Valid value for SMSC LAN91c111 are
|
||||
1, 2 or 4. If it's omitted or invalid, the size would be 2 meaning
|
||||
16-bit access only.
|
||||
|
|
|
|||
|
|
@ -1,5 +0,0 @@
|
|||
NVIDIA Tegra 2 SPI device
|
||||
|
||||
Required properties:
|
||||
- compatible : should be "nvidia,tegra20-spi".
|
||||
- gpios : should specify GPIOs used for chipselect.
|
||||
|
|
@ -32,12 +32,14 @@ est ESTeem Wireless Modems
|
|||
fsl Freescale Semiconductor
|
||||
GEFanuc GE Fanuc Intelligent Platforms Embedded Systems, Inc.
|
||||
gef GE Fanuc Intelligent Platforms Embedded Systems, Inc.
|
||||
gmt Global Mixed-mode Technology, Inc.
|
||||
hisilicon Hisilicon Limited.
|
||||
hp Hewlett Packard
|
||||
ibm International Business Machines (IBM)
|
||||
idt Integrated Device Technologies, Inc.
|
||||
img Imagination Technologies Ltd.
|
||||
intercontrol Inter Control Group
|
||||
lg LG Corporation
|
||||
linux Linux-specific binding
|
||||
lsi LSI Corp. (LSI Logic)
|
||||
marvell Marvell Technology Group Ltd.
|
||||
|
|
|
|||
|
|
@ -0,0 +1,14 @@
|
|||
00-INDEX
|
||||
- This file
|
||||
gpio.txt
|
||||
- Introduction to GPIOs and their kernel interfaces
|
||||
consumer.txt
|
||||
- How to obtain and use GPIOs in a driver
|
||||
driver.txt
|
||||
- How to write a GPIO driver
|
||||
board.txt
|
||||
- How to assign GPIOs to a consumer device and a function
|
||||
sysfs.txt
|
||||
- Information about the GPIO sysfs interface
|
||||
gpio-legacy.txt
|
||||
- Historical documentation of the deprecated GPIO integer interface
|
||||
|
|
@ -1529,6 +1529,8 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
|
|||
|
||||
* atapi_dmadir: Enable ATAPI DMADIR bridge support
|
||||
|
||||
* disable: Disable this device.
|
||||
|
||||
If there are multiple matching configurations changing
|
||||
the same attribute, the last one is used.
|
||||
|
||||
|
|
|
|||
|
|
@ -313,7 +313,7 @@ static struct mic_device_desc *get_device_desc(struct mic_info *mic, int type)
|
|||
int i;
|
||||
void *dp = get_dp(mic, type);
|
||||
|
||||
for (i = mic_aligned_size(struct mic_bootparam); i < PAGE_SIZE;
|
||||
for (i = sizeof(struct mic_bootparam); i < PAGE_SIZE;
|
||||
i += mic_total_desc_size(d)) {
|
||||
d = dp + i;
|
||||
|
||||
|
|
@ -445,8 +445,8 @@ init_vr(struct mic_info *mic, int fd, int type,
|
|||
__func__, mic->name, vr0->va, vr0->info, vr_size,
|
||||
vring_size(MIC_VRING_ENTRIES, MIC_VIRTIO_RING_ALIGN));
|
||||
mpsslog("magic 0x%x expected 0x%x\n",
|
||||
vr0->info->magic, MIC_MAGIC + type);
|
||||
assert(vr0->info->magic == MIC_MAGIC + type);
|
||||
le32toh(vr0->info->magic), MIC_MAGIC + type);
|
||||
assert(le32toh(vr0->info->magic) == MIC_MAGIC + type);
|
||||
if (vr1) {
|
||||
vr1->va = (struct mic_vring *)
|
||||
&va[MIC_DEVICE_PAGE_END + vr_size];
|
||||
|
|
@ -458,8 +458,8 @@ init_vr(struct mic_info *mic, int fd, int type,
|
|||
__func__, mic->name, vr1->va, vr1->info, vr_size,
|
||||
vring_size(MIC_VRING_ENTRIES, MIC_VIRTIO_RING_ALIGN));
|
||||
mpsslog("magic 0x%x expected 0x%x\n",
|
||||
vr1->info->magic, MIC_MAGIC + type + 1);
|
||||
assert(vr1->info->magic == MIC_MAGIC + type + 1);
|
||||
le32toh(vr1->info->magic), MIC_MAGIC + type + 1);
|
||||
assert(le32toh(vr1->info->magic) == MIC_MAGIC + type + 1);
|
||||
}
|
||||
done:
|
||||
return va;
|
||||
|
|
@ -520,7 +520,7 @@ static void *
|
|||
virtio_net(void *arg)
|
||||
{
|
||||
static __u8 vnet_hdr[2][sizeof(struct virtio_net_hdr)];
|
||||
static __u8 vnet_buf[2][MAX_NET_PKT_SIZE] __aligned(64);
|
||||
static __u8 vnet_buf[2][MAX_NET_PKT_SIZE] __attribute__ ((aligned(64)));
|
||||
struct iovec vnet_iov[2][2] = {
|
||||
{ { .iov_base = vnet_hdr[0], .iov_len = sizeof(vnet_hdr[0]) },
|
||||
{ .iov_base = vnet_buf[0], .iov_len = sizeof(vnet_buf[0]) } },
|
||||
|
|
@ -1412,6 +1412,12 @@ mic_config(void *arg)
|
|||
}
|
||||
|
||||
do {
|
||||
ret = lseek(fd, 0, SEEK_SET);
|
||||
if (ret < 0) {
|
||||
mpsslog("%s: Failed to seek to file start '%s': %s\n",
|
||||
mic->name, pathname, strerror(errno));
|
||||
goto close_error1;
|
||||
}
|
||||
ret = read(fd, value, sizeof(value));
|
||||
if (ret < 0) {
|
||||
mpsslog("%s: Failed to read sysfs entry '%s': %s\n",
|
||||
|
|
|
|||
|
|
@ -0,0 +1,240 @@
|
|||
==============================
|
||||
KERNEL MODULE SIGNING FACILITY
|
||||
==============================
|
||||
|
||||
CONTENTS
|
||||
|
||||
- Overview.
|
||||
- Configuring module signing.
|
||||
- Generating signing keys.
|
||||
- Public keys in the kernel.
|
||||
- Manually signing modules.
|
||||
- Signed modules and stripping.
|
||||
- Loading signed modules.
|
||||
- Non-valid signatures and unsigned modules.
|
||||
- Administering/protecting the private key.
|
||||
|
||||
|
||||
========
|
||||
OVERVIEW
|
||||
========
|
||||
|
||||
The kernel module signing facility cryptographically signs modules during
|
||||
installation and then checks the signature upon loading the module. This
|
||||
allows increased kernel security by disallowing the loading of unsigned modules
|
||||
or modules signed with an invalid key. Module signing increases security by
|
||||
making it harder to load a malicious module into the kernel. The module
|
||||
signature checking is done by the kernel so that it is not necessary to have
|
||||
trusted userspace bits.
|
||||
|
||||
This facility uses X.509 ITU-T standard certificates to encode the public keys
|
||||
involved. The signatures are not themselves encoded in any industrial standard
|
||||
type. The facility currently only supports the RSA public key encryption
|
||||
standard (though it is pluggable and permits others to be used). The possible
|
||||
hash algorithms that can be used are SHA-1, SHA-224, SHA-256, SHA-384, and
|
||||
SHA-512 (the algorithm is selected by data in the signature).
|
||||
|
||||
|
||||
==========================
|
||||
CONFIGURING MODULE SIGNING
|
||||
==========================
|
||||
|
||||
The module signing facility is enabled by going to the "Enable Loadable Module
|
||||
Support" section of the kernel configuration and turning on
|
||||
|
||||
CONFIG_MODULE_SIG "Module signature verification"
|
||||
|
||||
This has a number of options available:
|
||||
|
||||
(1) "Require modules to be validly signed" (CONFIG_MODULE_SIG_FORCE)
|
||||
|
||||
This specifies how the kernel should deal with a module that has a
|
||||
signature for which the key is not known or a module that is unsigned.
|
||||
|
||||
If this is off (ie. "permissive"), then modules for which the key is not
|
||||
available and modules that are unsigned are permitted, but the kernel will
|
||||
be marked as being tainted.
|
||||
|
||||
If this is on (ie. "restrictive"), only modules that have a valid
|
||||
signature that can be verified by a public key in the kernel's possession
|
||||
will be loaded. All other modules will generate an error.
|
||||
|
||||
Irrespective of the setting here, if the module has a signature block that
|
||||
cannot be parsed, it will be rejected out of hand.
|
||||
|
||||
|
||||
(2) "Automatically sign all modules" (CONFIG_MODULE_SIG_ALL)
|
||||
|
||||
If this is on then modules will be automatically signed during the
|
||||
modules_install phase of a build. If this is off, then the modules must
|
||||
be signed manually using:
|
||||
|
||||
scripts/sign-file
|
||||
|
||||
|
||||
(3) "Which hash algorithm should modules be signed with?"
|
||||
|
||||
This presents a choice of which hash algorithm the installation phase will
|
||||
sign the modules with:
|
||||
|
||||
CONFIG_SIG_SHA1 "Sign modules with SHA-1"
|
||||
CONFIG_SIG_SHA224 "Sign modules with SHA-224"
|
||||
CONFIG_SIG_SHA256 "Sign modules with SHA-256"
|
||||
CONFIG_SIG_SHA384 "Sign modules with SHA-384"
|
||||
CONFIG_SIG_SHA512 "Sign modules with SHA-512"
|
||||
|
||||
The algorithm selected here will also be built into the kernel (rather
|
||||
than being a module) so that modules signed with that algorithm can have
|
||||
their signatures checked without causing a dependency loop.
|
||||
|
||||
|
||||
=======================
|
||||
GENERATING SIGNING KEYS
|
||||
=======================
|
||||
|
||||
Cryptographic keypairs are required to generate and check signatures. A
|
||||
private key is used to generate a signature and the corresponding public key is
|
||||
used to check it. The private key is only needed during the build, after which
|
||||
it can be deleted or stored securely. The public key gets built into the
|
||||
kernel so that it can be used to check the signatures as the modules are
|
||||
loaded.
|
||||
|
||||
Under normal conditions, the kernel build will automatically generate a new
|
||||
keypair using openssl if one does not exist in the files:
|
||||
|
||||
signing_key.priv
|
||||
signing_key.x509
|
||||
|
||||
during the building of vmlinux (the public part of the key needs to be built
|
||||
into vmlinux) using parameters in the:
|
||||
|
||||
x509.genkey
|
||||
|
||||
file (which is also generated if it does not already exist).
|
||||
|
||||
It is strongly recommended that you provide your own x509.genkey file.
|
||||
|
||||
Most notably, in the x509.genkey file, the req_distinguished_name section
|
||||
should be altered from the default:
|
||||
|
||||
[ req_distinguished_name ]
|
||||
O = Magrathea
|
||||
CN = Glacier signing key
|
||||
emailAddress = slartibartfast@magrathea.h2g2
|
||||
|
||||
The generated RSA key size can also be set with:
|
||||
|
||||
[ req ]
|
||||
default_bits = 4096
|
||||
|
||||
|
||||
It is also possible to manually generate the key private/public files using the
|
||||
x509.genkey key generation configuration file in the root node of the Linux
|
||||
kernel sources tree and the openssl command. The following is an example to
|
||||
generate the public/private key files:
|
||||
|
||||
openssl req -new -nodes -utf8 -sha256 -days 36500 -batch -x509 \
|
||||
-config x509.genkey -outform DER -out signing_key.x509 \
|
||||
-keyout signing_key.priv
|
||||
|
||||
|
||||
=========================
|
||||
PUBLIC KEYS IN THE KERNEL
|
||||
=========================
|
||||
|
||||
The kernel contains a ring of public keys that can be viewed by root. They're
|
||||
in a keyring called ".system_keyring" that can be seen by:
|
||||
|
||||
[root@deneb ~]# cat /proc/keys
|
||||
...
|
||||
223c7853 I------ 1 perm 1f030000 0 0 keyring .system_keyring: 1
|
||||
302d2d52 I------ 1 perm 1f010000 0 0 asymmetri Fedora kernel signing key: d69a84e6bce3d216b979e9505b3e3ef9a7118079: X509.RSA a7118079 []
|
||||
...
|
||||
|
||||
Beyond the public key generated specifically for module signing, any file
|
||||
placed in the kernel source root directory or the kernel build root directory
|
||||
whose name is suffixed with ".x509" will be assumed to be an X.509 public key
|
||||
and will be added to the keyring.
|
||||
|
||||
Further, the architecture code may take public keys from a hardware store and
|
||||
add those in also (e.g. from the UEFI key database).
|
||||
|
||||
Finally, it is possible to add additional public keys by doing:
|
||||
|
||||
keyctl padd asymmetric "" [.system_keyring-ID] <[key-file]
|
||||
|
||||
e.g.:
|
||||
|
||||
keyctl padd asymmetric "" 0x223c7853 <my_public_key.x509
|
||||
|
||||
Note, however, that the kernel will only permit keys to be added to
|
||||
.system_keyring _if_ the new key's X.509 wrapper is validly signed by a key
|
||||
that is already resident in the .system_keyring at the time the key was added.
|
||||
|
||||
|
||||
=========================
|
||||
MANUALLY SIGNING MODULES
|
||||
=========================
|
||||
|
||||
To manually sign a module, use the scripts/sign-file tool available in
|
||||
the Linux kernel source tree. The script requires 4 arguments:
|
||||
|
||||
1. The hash algorithm (e.g., sha256)
|
||||
2. The private key filename
|
||||
3. The public key filename
|
||||
4. The kernel module to be signed
|
||||
|
||||
The following is an example to sign a kernel module:
|
||||
|
||||
scripts/sign-file sha512 kernel-signkey.priv \
|
||||
kernel-signkey.x509 module.ko
|
||||
|
||||
The hash algorithm used does not have to match the one configured, but if it
|
||||
doesn't, you should make sure that hash algorithm is either built into the
|
||||
kernel or can be loaded without requiring itself.
|
||||
|
||||
|
||||
============================
|
||||
SIGNED MODULES AND STRIPPING
|
||||
============================
|
||||
|
||||
A signed module has a digital signature simply appended at the end. The string
|
||||
"~Module signature appended~." at the end of the module's file confirms that a
|
||||
signature is present but it does not confirm that the signature is valid!
|
||||
|
||||
Signed modules are BRITTLE as the signature is outside of the defined ELF
|
||||
container. Thus they MAY NOT be stripped once the signature is computed and
|
||||
attached. Note the entire module is the signed payload, including any and all
|
||||
debug information present at the time of signing.
|
||||
|
||||
|
||||
======================
|
||||
LOADING SIGNED MODULES
|
||||
======================
|
||||
|
||||
Modules are loaded with insmod, modprobe, init_module() or finit_module(),
|
||||
exactly as for unsigned modules as no processing is done in userspace. The
|
||||
signature checking is all done within the kernel.
|
||||
|
||||
|
||||
=========================================
|
||||
NON-VALID SIGNATURES AND UNSIGNED MODULES
|
||||
=========================================
|
||||
|
||||
If CONFIG_MODULE_SIG_FORCE is enabled or enforcemodulesig=1 is supplied on
|
||||
the kernel command line, the kernel will only load validly signed modules
|
||||
for which it has a public key. Otherwise, it will also load modules that are
|
||||
unsigned. Any module for which the kernel has a key, but which proves to have
|
||||
a signature mismatch will not be permitted to load.
|
||||
|
||||
Any module that has an unparseable signature will be rejected.
|
||||
|
||||
|
||||
=========================================
|
||||
ADMINISTERING/PROTECTING THE PRIVATE KEY
|
||||
=========================================
|
||||
|
||||
Since the private key is used to sign modules, viruses and malware could use
|
||||
the private key to sign modules and compromise the operating system. The
|
||||
private key must be either destroyed or moved to a secure location and not kept
|
||||
in the root node of the kernel source tree.
|
||||
|
|
@ -16,8 +16,12 @@ ip_default_ttl - INTEGER
|
|||
Default: 64 (as recommended by RFC1700)
|
||||
|
||||
ip_no_pmtu_disc - BOOLEAN
|
||||
Disable Path MTU Discovery.
|
||||
default FALSE
|
||||
Disable Path MTU Discovery. If enabled and a
|
||||
fragmentation-required ICMP is received, the PMTU to this
|
||||
destination will be set to min_pmtu (see below). You will need
|
||||
to raise min_pmtu to the smallest interface MTU on your system
|
||||
manually if you want to avoid locally generated fragments.
|
||||
Default: FALSE
|
||||
|
||||
min_pmtu - INTEGER
|
||||
default 552 - minimum discovered Path MTU
|
||||
|
|
|
|||
|
|
@ -123,6 +123,16 @@ Transmission process is similar to capture as shown below.
|
|||
[shutdown] close() --------> destruction of the transmission socket and
|
||||
deallocation of all associated resources.
|
||||
|
||||
Socket creation and destruction is also straight forward, and is done
|
||||
the same way as in capturing described in the previous paragraph:
|
||||
|
||||
int fd = socket(PF_PACKET, mode, 0);
|
||||
|
||||
The protocol can optionally be 0 in case we only want to transmit
|
||||
via this socket, which avoids an expensive call to packet_rcv().
|
||||
In this case, you also need to bind(2) the TX_RING with sll_protocol = 0
|
||||
set. Otherwise, htons(ETH_P_ALL) or any other protocol, for example.
|
||||
|
||||
Binding the socket to your network interface is mandatory (with zero copy) to
|
||||
know the header size of frames used in the circular buffer.
|
||||
|
||||
|
|
|
|||
106
MAINTAINERS
106
MAINTAINERS
|
|
@ -783,7 +783,7 @@ F: arch/arm/boot/dts/sama*.dts
|
|||
F: arch/arm/boot/dts/sama*.dtsi
|
||||
|
||||
ARM/CALXEDA HIGHBANK ARCHITECTURE
|
||||
M: Rob Herring <rob.herring@calxeda.com>
|
||||
M: Rob Herring <robh@kernel.org>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
F: arch/arm/mach-highbank/
|
||||
|
|
@ -893,19 +893,14 @@ F: arch/arm/include/asm/hardware/dec21285.h
|
|||
F: arch/arm/mach-footbridge/
|
||||
|
||||
ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
|
||||
M: Shawn Guo <shawn.guo@linaro.org>
|
||||
M: Sascha Hauer <kernel@pengutronix.de>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
T: git git://git.pengutronix.de/git/imx/linux-2.6.git
|
||||
F: arch/arm/mach-imx/
|
||||
F: arch/arm/configs/imx*_defconfig
|
||||
|
||||
ARM/FREESCALE IMX6
|
||||
M: Shawn Guo <shawn.guo@linaro.org>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
T: git git://git.linaro.org/people/shawnguo/linux-2.6.git
|
||||
F: arch/arm/mach-imx/*imx6*
|
||||
F: arch/arm/mach-imx/
|
||||
F: arch/arm/boot/dts/imx*
|
||||
F: arch/arm/configs/imx*_defconfig
|
||||
|
||||
ARM/FREESCALE MXS ARM ARCHITECTURE
|
||||
M: Shawn Guo <shawn.guo@linaro.org>
|
||||
|
|
@ -1013,6 +1008,8 @@ M: Santosh Shilimkar <santosh.shilimkar@ti.com>
|
|||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
F: arch/arm/mach-keystone/
|
||||
F: drivers/clk/keystone/
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone.git
|
||||
|
||||
ARM/LOGICPD PXA270 MACHINE SUPPORT
|
||||
M: Lennert Buytenhek <kernel@wantstofly.org>
|
||||
|
|
@ -1371,6 +1368,9 @@ T: git git://git.xilinx.com/linux-xlnx.git
|
|||
S: Supported
|
||||
F: arch/arm/mach-zynq/
|
||||
F: drivers/cpuidle/cpuidle-zynq.c
|
||||
N: zynq
|
||||
N: xilinx
|
||||
F: drivers/clocksource/cadence_ttc_timer.c
|
||||
|
||||
ARM SMMU DRIVER
|
||||
M: Will Deacon <will.deacon@arm.com>
|
||||
|
|
@ -1934,7 +1934,8 @@ S: Maintained
|
|||
F: drivers/gpio/gpio-bt8xx.c
|
||||
|
||||
BTRFS FILE SYSTEM
|
||||
M: Chris Mason <chris.mason@fusionio.com>
|
||||
M: Chris Mason <clm@fb.com>
|
||||
M: Josef Bacik <jbacik@fb.com>
|
||||
L: linux-btrfs@vger.kernel.org
|
||||
W: http://btrfs.wiki.kernel.org/
|
||||
Q: http://patchwork.kernel.org/project/linux-btrfs/list/
|
||||
|
|
@ -2137,7 +2138,8 @@ S: Maintained
|
|||
F: Documentation/zh_CN/
|
||||
|
||||
CHIPIDEA USB HIGH SPEED DUAL ROLE CONTROLLER
|
||||
M: Alexander Shishkin <alexander.shishkin@linux.intel.com>
|
||||
M: Peter Chen <Peter.Chen@freescale.com>
|
||||
T: git://github.com/hzpeterchen/linux-usb.git
|
||||
L: linux-usb@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/usb/chipidea/
|
||||
|
|
@ -2826,8 +2828,10 @@ F: include/uapi/drm/
|
|||
|
||||
INTEL DRM DRIVERS (excluding Poulsbo, Moorestown and derivative chipsets)
|
||||
M: Daniel Vetter <daniel.vetter@ffwll.ch>
|
||||
M: Jani Nikula <jani.nikula@linux.intel.com>
|
||||
L: intel-gfx@lists.freedesktop.org
|
||||
L: dri-devel@lists.freedesktop.org
|
||||
Q: http://patchwork.freedesktop.org/project/intel-gfx/
|
||||
T: git git://people.freedesktop.org/~danvet/drm-intel
|
||||
S: Supported
|
||||
F: drivers/gpu/drm/i915/
|
||||
|
|
@ -3764,9 +3768,11 @@ F: include/uapi/linux/gigaset_dev.h
|
|||
|
||||
GPIO SUBSYSTEM
|
||||
M: Linus Walleij <linus.walleij@linaro.org>
|
||||
S: Maintained
|
||||
M: Alexandre Courbot <gnurou@gmail.com>
|
||||
L: linux-gpio@vger.kernel.org
|
||||
F: Documentation/gpio.txt
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio.git
|
||||
S: Maintained
|
||||
F: Documentation/gpio/
|
||||
F: drivers/gpio/
|
||||
F: include/linux/gpio*
|
||||
F: include/asm-generic/gpio.h
|
||||
|
|
@ -3834,6 +3840,12 @@ T: git git://linuxtv.org/media_tree.git
|
|||
S: Maintained
|
||||
F: drivers/media/usb/gspca/
|
||||
|
||||
GUID PARTITION TABLE (GPT)
|
||||
M: Davidlohr Bueso <davidlohr@hp.com>
|
||||
L: linux-efi@vger.kernel.org
|
||||
S: Maintained
|
||||
F: block/partitions/efi.*
|
||||
|
||||
STK1160 USB VIDEO CAPTURE DRIVER
|
||||
M: Ezequiel Garcia <elezegarcia@gmail.com>
|
||||
L: linux-media@vger.kernel.org
|
||||
|
|
@ -4043,6 +4055,14 @@ W: http://artax.karlin.mff.cuni.cz/~mikulas/vyplody/hpfs/index-e.cgi
|
|||
S: Maintained
|
||||
F: fs/hpfs/
|
||||
|
||||
HSI SUBSYSTEM
|
||||
M: Sebastian Reichel <sre@debian.org>
|
||||
S: Maintained
|
||||
F: Documentation/ABI/testing/sysfs-bus-hsi
|
||||
F: drivers/hsi/
|
||||
F: include/linux/hsi/
|
||||
F: include/uapi/linux/hsi/
|
||||
|
||||
HSO 3G MODEM DRIVER
|
||||
M: Jan Dumon <j.dumon@option.com>
|
||||
W: http://www.pharscape.org
|
||||
|
|
@ -4461,10 +4481,8 @@ M: Bruce Allan <bruce.w.allan@intel.com>
|
|||
M: Carolyn Wyborny <carolyn.wyborny@intel.com>
|
||||
M: Don Skidmore <donald.c.skidmore@intel.com>
|
||||
M: Greg Rose <gregory.v.rose@intel.com>
|
||||
M: Peter P Waskiewicz Jr <peter.p.waskiewicz.jr@intel.com>
|
||||
M: Alex Duyck <alexander.h.duyck@intel.com>
|
||||
M: John Ronciak <john.ronciak@intel.com>
|
||||
M: Tushar Dave <tushar.n.dave@intel.com>
|
||||
L: e1000-devel@lists.sourceforge.net
|
||||
W: http://www.intel.com/support/feedback.htm
|
||||
W: http://e1000.sourceforge.net/
|
||||
|
|
@ -5908,12 +5926,21 @@ M: Steffen Klassert <steffen.klassert@secunet.com>
|
|||
M: Herbert Xu <herbert@gondor.apana.org.au>
|
||||
M: "David S. Miller" <davem@davemloft.net>
|
||||
L: netdev@vger.kernel.org
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/davem/net.git
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/klassert/ipsec.git
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/klassert/ipsec-next.git
|
||||
S: Maintained
|
||||
F: net/xfrm/
|
||||
F: net/key/
|
||||
F: net/ipv4/xfrm*
|
||||
F: net/ipv4/esp4.c
|
||||
F: net/ipv4/ah4.c
|
||||
F: net/ipv4/ipcomp.c
|
||||
F: net/ipv4/ip_vti.c
|
||||
F: net/ipv6/xfrm*
|
||||
F: net/ipv6/esp6.c
|
||||
F: net/ipv6/ah6.c
|
||||
F: net/ipv6/ipcomp6.c
|
||||
F: net/ipv6/ip6_vti.c
|
||||
F: include/uapi/linux/xfrm.h
|
||||
F: include/net/xfrm.h
|
||||
|
||||
|
|
@ -5979,10 +6006,10 @@ F: drivers/nfc/
|
|||
F: include/linux/platform_data/pn544.h
|
||||
|
||||
NFS, SUNRPC, AND LOCKD CLIENTS
|
||||
M: Trond Myklebust <Trond.Myklebust@netapp.com>
|
||||
M: Trond Myklebust <trond.myklebust@primarydata.com>
|
||||
L: linux-nfs@vger.kernel.org
|
||||
W: http://client.linux-nfs.org
|
||||
T: git git://git.linux-nfs.org/pub/linux/nfs-2.6.git
|
||||
T: git git://git.linux-nfs.org/projects/trondmy/linux-nfs.git
|
||||
S: Maintained
|
||||
F: fs/lockd/
|
||||
F: fs/nfs/
|
||||
|
|
@ -6234,7 +6261,7 @@ F: drivers/i2c/busses/i2c-ocores.c
|
|||
|
||||
OPEN FIRMWARE AND FLATTENED DEVICE TREE
|
||||
M: Grant Likely <grant.likely@linaro.org>
|
||||
M: Rob Herring <rob.herring@calxeda.com>
|
||||
M: Rob Herring <robh+dt@kernel.org>
|
||||
L: devicetree@vger.kernel.org
|
||||
W: http://fdt.secretlab.ca
|
||||
T: git git://git.secretlab.ca/git/linux-2.6.git
|
||||
|
|
@ -6246,11 +6273,11 @@ K: of_get_property
|
|||
K: of_match_table
|
||||
|
||||
OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
|
||||
M: Rob Herring <rob.herring@calxeda.com>
|
||||
M: Rob Herring <robh+dt@kernel.org>
|
||||
M: Pawel Moll <pawel.moll@arm.com>
|
||||
M: Mark Rutland <mark.rutland@arm.com>
|
||||
M: Stephen Warren <swarren@wwwdotorg.org>
|
||||
M: Ian Campbell <ijc+devicetree@hellion.org.uk>
|
||||
M: Kumar Gala <galak@codeaurora.org>
|
||||
L: devicetree@vger.kernel.org
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/
|
||||
|
|
@ -6460,19 +6487,52 @@ F: drivers/pci/
|
|||
F: include/linux/pci*
|
||||
F: arch/x86/pci/
|
||||
|
||||
PCI DRIVER FOR IMX6
|
||||
M: Richard Zhu <r65037@freescale.com>
|
||||
M: Shawn Guo <shawn.guo@linaro.org>
|
||||
L: linux-pci@vger.kernel.org
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
F: drivers/pci/host/*imx6*
|
||||
|
||||
PCI DRIVER FOR MVEBU (Marvell Armada 370 and Armada XP SOC support)
|
||||
M: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
M: Jason Cooper <jason@lakedaemon.net>
|
||||
L: linux-pci@vger.kernel.org
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
F: drivers/pci/host/*mvebu*
|
||||
|
||||
PCI DRIVER FOR NVIDIA TEGRA
|
||||
M: Thierry Reding <thierry.reding@gmail.com>
|
||||
L: linux-tegra@vger.kernel.org
|
||||
L: linux-pci@vger.kernel.org
|
||||
S: Supported
|
||||
F: Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
|
||||
F: drivers/pci/host/pci-tegra.c
|
||||
|
||||
PCI DRIVER FOR RENESAS R-CAR
|
||||
M: Simon Horman <horms@verge.net.au>
|
||||
L: linux-pci@vger.kernel.org
|
||||
L: linux-sh@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/pci/host/*rcar*
|
||||
|
||||
PCI DRIVER FOR SAMSUNG EXYNOS
|
||||
M: Jingoo Han <jg1.han@samsung.com>
|
||||
L: linux-pci@vger.kernel.org
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
L: linux-samsung-soc@vger.kernel.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
F: drivers/pci/host/pci-exynos.c
|
||||
|
||||
PCI DRIVER FOR SYNOPSIS DESIGNWARE
|
||||
M: Mohit Kumar <mohit.kumar@st.com>
|
||||
M: Jingoo Han <jg1.han@samsung.com>
|
||||
L: linux-pci@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/pci/host/*designware*
|
||||
|
||||
PCMCIA SUBSYSTEM
|
||||
P: Linux PCMCIA Team
|
||||
L: linux-pcmcia@lists.infradead.org
|
||||
|
|
@ -9535,7 +9595,7 @@ F: drivers/xen/*swiotlb*
|
|||
|
||||
XFS FILESYSTEM
|
||||
P: Silicon Graphics Inc
|
||||
M: Dave Chinner <dchinner@fromorbit.com>
|
||||
M: Dave Chinner <david@fromorbit.com>
|
||||
M: Ben Myers <bpm@sgi.com>
|
||||
M: xfs@oss.sgi.com
|
||||
L: xfs@oss.sgi.com
|
||||
|
|
|
|||
24
Makefile
24
Makefile
|
|
@ -1,7 +1,7 @@
|
|||
VERSION = 3
|
||||
PATCHLEVEL = 13
|
||||
SUBLEVEL = 0
|
||||
EXTRAVERSION = -rc2
|
||||
EXTRAVERSION = -rc7
|
||||
NAME = One Giant Leap for Frogkind
|
||||
|
||||
# *DOCUMENTATION*
|
||||
|
|
@ -732,19 +732,15 @@ export mod_strip_cmd
|
|||
# Select initial ramdisk compression format, default is gzip(1).
|
||||
# This shall be used by the dracut(8) tool while creating an initramfs image.
|
||||
#
|
||||
INITRD_COMPRESS=gzip
|
||||
ifeq ($(CONFIG_RD_BZIP2), y)
|
||||
INITRD_COMPRESS=bzip2
|
||||
else ifeq ($(CONFIG_RD_LZMA), y)
|
||||
INITRD_COMPRESS=lzma
|
||||
else ifeq ($(CONFIG_RD_XZ), y)
|
||||
INITRD_COMPRESS=xz
|
||||
else ifeq ($(CONFIG_RD_LZO), y)
|
||||
INITRD_COMPRESS=lzo
|
||||
else ifeq ($(CONFIG_RD_LZ4), y)
|
||||
INITRD_COMPRESS=lz4
|
||||
endif
|
||||
export INITRD_COMPRESS
|
||||
INITRD_COMPRESS-y := gzip
|
||||
INITRD_COMPRESS-$(CONFIG_RD_BZIP2) := bzip2
|
||||
INITRD_COMPRESS-$(CONFIG_RD_LZMA) := lzma
|
||||
INITRD_COMPRESS-$(CONFIG_RD_XZ) := xz
|
||||
INITRD_COMPRESS-$(CONFIG_RD_LZO) := lzo
|
||||
INITRD_COMPRESS-$(CONFIG_RD_LZ4) := lz4
|
||||
# do not export INITRD_COMPRESS, since we didn't actually
|
||||
# choose a sane default compression above.
|
||||
# export INITRD_COMPRESS := $(INITRD_COMPRESS-y)
|
||||
|
||||
ifdef CONFIG_MODULE_SIG_ALL
|
||||
MODSECKEY = ./signing_key.priv
|
||||
|
|
|
|||
|
|
@ -8,6 +8,7 @@
|
|||
|
||||
config ARC
|
||||
def_bool y
|
||||
select BUILDTIME_EXTABLE_SORT
|
||||
select CLONE_BACKWARDS
|
||||
# ARC Busybox based initramfs absolutely relies on DEVTMPFS for /dev
|
||||
select DEVTMPFS if !INITRAMFS_SOURCE=""
|
||||
|
|
|
|||
|
|
@ -8,6 +8,13 @@
|
|||
|
||||
/******** no-legacy-syscalls-ABI *******/
|
||||
|
||||
/*
|
||||
* Non-typical guard macro to enable inclusion twice in ARCH sys.c
|
||||
* That is how the Generic syscall wrapper generator works
|
||||
*/
|
||||
#if !defined(_UAPI_ASM_ARC_UNISTD_H) || defined(__SYSCALL)
|
||||
#define _UAPI_ASM_ARC_UNISTD_H
|
||||
|
||||
#define __ARCH_WANT_SYS_EXECVE
|
||||
#define __ARCH_WANT_SYS_CLONE
|
||||
#define __ARCH_WANT_SYS_VFORK
|
||||
|
|
@ -32,3 +39,7 @@ __SYSCALL(__NR_arc_gettls, sys_arc_gettls)
|
|||
/* Generic syscall (fs/filesystems.c - lost in asm-generic/unistd.h */
|
||||
#define __NR_sysfs (__NR_arch_specific_syscall + 3)
|
||||
__SYSCALL(__NR_sysfs, sys_sysfs)
|
||||
|
||||
#undef __SYSCALL
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -79,9 +79,9 @@ static int arc_pmu_cache_event(u64 config)
|
|||
cache_result = (config >> 16) & 0xff;
|
||||
if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
|
||||
return -EINVAL;
|
||||
if (cache_type >= PERF_COUNT_HW_CACHE_OP_MAX)
|
||||
if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
|
||||
return -EINVAL;
|
||||
if (cache_type >= PERF_COUNT_HW_CACHE_RESULT_MAX)
|
||||
if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
|
||||
return -EINVAL;
|
||||
|
||||
ret = arc_pmu_cache_map[cache_type][cache_op][cache_result];
|
||||
|
|
|
|||
|
|
@ -13,4 +13,83 @@
|
|||
/ {
|
||||
model = "IGEP COM AM335x on AQUILA Expansion";
|
||||
compatible = "isee,am335x-base0033", "isee,am335x-igep0033", "ti,am33xx";
|
||||
|
||||
hdmi {
|
||||
compatible = "ti,tilcdc,slave";
|
||||
i2c = <&i2c0>;
|
||||
pinctrl-names = "default", "off";
|
||||
pinctrl-0 = <&nxp_hdmi_pins>;
|
||||
pinctrl-1 = <&nxp_hdmi_off_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
leds_base {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&leds_base_pins>;
|
||||
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led@0 {
|
||||
label = "base:red:user";
|
||||
gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; /* gpio1_21 */
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led@1 {
|
||||
label = "base:green:user";
|
||||
gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>; /* gpio2_0 */
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&am33xx_pinmux {
|
||||
nxp_hdmi_pins: pinmux_nxp_hdmi_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x1b0 (PIN_OUTPUT | MUX_MODE3) /* xdma_event_intr0.clkout1 */
|
||||
0xa0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data0 */
|
||||
0xa4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data1 */
|
||||
0xa8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data2 */
|
||||
0xac (PIN_OUTPUT | MUX_MODE0) /* lcd_data3 */
|
||||
0xb0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data4 */
|
||||
0xb4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data5 */
|
||||
0xb8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data6 */
|
||||
0xbc (PIN_OUTPUT | MUX_MODE0) /* lcd_data7 */
|
||||
0xc0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data8 */
|
||||
0xc4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data9 */
|
||||
0xc8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data10 */
|
||||
0xcc (PIN_OUTPUT | MUX_MODE0) /* lcd_data11 */
|
||||
0xd0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data12 */
|
||||
0xd4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data13 */
|
||||
0xd8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data14 */
|
||||
0xdc (PIN_OUTPUT | MUX_MODE0) /* lcd_data15 */
|
||||
0xe0 (PIN_OUTPUT | MUX_MODE0) /* lcd_vsync */
|
||||
0xe4 (PIN_OUTPUT | MUX_MODE0) /* lcd_hsync */
|
||||
0xe8 (PIN_OUTPUT | MUX_MODE0) /* lcd_pclk */
|
||||
0xec (PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en */
|
||||
>;
|
||||
};
|
||||
nxp_hdmi_off_pins: pinmux_nxp_hdmi_off_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x1b0 (PIN_OUTPUT | MUX_MODE3) /* xdma_event_intr0.clkout1 */
|
||||
>;
|
||||
};
|
||||
|
||||
leds_base_pins: pinmux_leds_base_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */
|
||||
0x88 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn3.gpio2_0 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&lcdc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
eeprom: eeprom@50 {
|
||||
compatible = "at,24c256";
|
||||
reg = <0x50>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -199,6 +199,35 @@
|
|||
pinctrl-0 = <&uart0_pins>;
|
||||
};
|
||||
|
||||
&usb {
|
||||
status = "okay";
|
||||
|
||||
control@44e10000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb-phy@47401300 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb-phy@47401b00 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb@47401000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb@47401800 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
dma-controller@07402000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
#include "tps65910.dtsi"
|
||||
|
||||
&tps {
|
||||
|
|
|
|||
|
|
@ -7,11 +7,11 @@
|
|||
*/
|
||||
/dts-v1/;
|
||||
|
||||
#include "omap34xx.dtsi"
|
||||
#include "am3517.dtsi"
|
||||
|
||||
/ {
|
||||
model = "TI AM3517 EVM (AM3517/05)";
|
||||
compatible = "ti,am3517-evm", "ti,omap3";
|
||||
model = "TI AM3517 EVM (AM3517/05 TMDSEVM3517)";
|
||||
compatible = "ti,am3517-evm", "ti,am3517", "ti,omap3";
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
|
|
|
|||
|
|
@ -0,0 +1,63 @@
|
|||
/*
|
||||
* Device Tree Source for am3517 SoC
|
||||
*
|
||||
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include "omap3.dtsi"
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
serial3 = &uart4;
|
||||
};
|
||||
|
||||
ocp {
|
||||
am35x_otg_hs: am35x_otg_hs@5c040000 {
|
||||
compatible = "ti,omap3-musb";
|
||||
ti,hwmods = "am35x_otg_hs";
|
||||
status = "disabled";
|
||||
reg = <0x5c040000 0x1000>;
|
||||
interrupts = <71>;
|
||||
interrupt-names = "mc";
|
||||
};
|
||||
|
||||
davinci_emac: ethernet@0x5c000000 {
|
||||
compatible = "ti,am3517-emac";
|
||||
ti,hwmods = "davinci_emac";
|
||||
status = "disabled";
|
||||
reg = <0x5c000000 0x30000>;
|
||||
interrupts = <67 68 69 70>;
|
||||
ti,davinci-ctrl-reg-offset = <0x10000>;
|
||||
ti,davinci-ctrl-mod-reg-offset = <0>;
|
||||
ti,davinci-ctrl-ram-offset = <0x20000>;
|
||||
ti,davinci-ctrl-ram-size = <0x2000>;
|
||||
ti,davinci-rmii-en = /bits/ 8 <1>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
};
|
||||
|
||||
davinci_mdio: ethernet@0x5c030000 {
|
||||
compatible = "ti,davinci_mdio";
|
||||
ti,hwmods = "davinci_mdio";
|
||||
status = "disabled";
|
||||
reg = <0x5c030000 0x1000>;
|
||||
bus_freq = <1000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
uart4: serial@4809e000 {
|
||||
compatible = "ti,omap3-uart";
|
||||
ti,hwmods = "uart4";
|
||||
status = "disabled";
|
||||
reg = <0x4809e000 0x400>;
|
||||
interrupts = <84>;
|
||||
dmas = <&sdma 55 &sdma 54>;
|
||||
dma-names = "tx", "rx";
|
||||
clock-frequency = <48000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -99,6 +99,7 @@
|
|||
spi-max-frequency = <50000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pcie-controller {
|
||||
status = "okay";
|
||||
|
|
@ -117,5 +118,4 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -118,7 +118,7 @@
|
|||
|
||||
coherency-fabric@20200 {
|
||||
compatible = "marvell,coherency-fabric";
|
||||
reg = <0x20200 0xb0>, <0x21810 0x1c>;
|
||||
reg = <0x20200 0xb0>, <0x21010 0x1c>;
|
||||
};
|
||||
|
||||
serial@12000 {
|
||||
|
|
|
|||
|
|
@ -47,7 +47,7 @@
|
|||
/*
|
||||
* MV78230 has 2 PCIe units Gen2.0: One unit can be
|
||||
* configured as x4 or quad x1 lanes. One unit is
|
||||
* x4/x1.
|
||||
* x1 only.
|
||||
*/
|
||||
pcie-controller {
|
||||
compatible = "marvell,armada-xp-pcie";
|
||||
|
|
@ -62,10 +62,10 @@
|
|||
|
||||
ranges =
|
||||
<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
|
||||
0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
|
||||
0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
|
||||
0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
|
||||
0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
|
||||
0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
|
||||
0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
|
||||
0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
|
||||
0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
|
||||
|
|
@ -74,8 +74,8 @@
|
|||
0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
|
||||
0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
|
||||
0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
|
||||
0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
|
||||
0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>;
|
||||
0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
|
||||
0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>;
|
||||
|
||||
pcie@1,0 {
|
||||
device_type = "pci";
|
||||
|
|
@ -145,20 +145,20 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@9,0 {
|
||||
pcie@5,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
|
||||
reg = <0x4800 0 0 0 0>;
|
||||
assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
|
||||
reg = <0x2800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x9 0 1 0>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x5 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 99>;
|
||||
marvell,pcie-port = <2>;
|
||||
interrupt-map = <0 0 0 0 &mpic 62>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 26>;
|
||||
clocks = <&gateclk 9>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -48,7 +48,7 @@
|
|||
/*
|
||||
* MV78260 has 3 PCIe units Gen2.0: Two units can be
|
||||
* configured as x4 or quad x1 lanes. One unit is
|
||||
* x4/x1.
|
||||
* x4 only.
|
||||
*/
|
||||
pcie-controller {
|
||||
compatible = "marvell,armada-xp-pcie";
|
||||
|
|
@ -68,7 +68,9 @@
|
|||
0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
|
||||
0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
|
||||
0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
|
||||
0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
|
||||
0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
|
||||
0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
|
||||
0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
|
||||
0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
|
||||
0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
|
||||
0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
|
||||
|
|
@ -77,10 +79,18 @@
|
|||
0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
|
||||
0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
|
||||
0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
|
||||
0x82000000 0x9 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
|
||||
0x81000000 0x9 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
|
||||
0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
|
||||
0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>;
|
||||
|
||||
0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
|
||||
0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
|
||||
0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
|
||||
0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
|
||||
0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
|
||||
0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
|
||||
0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
|
||||
0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
|
||||
|
||||
0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
|
||||
0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>;
|
||||
|
||||
pcie@1,0 {
|
||||
device_type = "pci";
|
||||
|
|
@ -150,6 +160,74 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@5,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
|
||||
reg = <0x2800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x5 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 62>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 9>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@6,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x84000 0 0x2000>;
|
||||
reg = <0x3000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x6 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 63>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <1>;
|
||||
clocks = <&gateclk 10>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@7,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x88000 0 0x2000>;
|
||||
reg = <0x3800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x7 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 64>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <2>;
|
||||
clocks = <&gateclk 11>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@8,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x8c000 0 0x2000>;
|
||||
reg = <0x4000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x8 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 65>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <3>;
|
||||
clocks = <&gateclk 12>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@9,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
|
||||
|
|
@ -166,23 +244,6 @@
|
|||
clocks = <&gateclk 26>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@10,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x82000 0 0x2000>;
|
||||
reg = <0x5000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
|
||||
0x81000000 0 0 0x81000000 0xa 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 103>;
|
||||
marvell,pcie-port = <3>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 27>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
internal-regs {
|
||||
|
|
|
|||
|
|
@ -11,6 +11,10 @@
|
|||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
serial4 = &usart3;
|
||||
};
|
||||
|
||||
ahb {
|
||||
apb {
|
||||
pinctrl@fffff400 {
|
||||
|
|
|
|||
|
|
@ -559,7 +559,7 @@
|
|||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x10800000 0x1000>;
|
||||
interrupts = <0 33 0>;
|
||||
clocks = <&clock 271>;
|
||||
clocks = <&clock 346>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
|
|
|
|||
|
|
@ -44,8 +44,8 @@
|
|||
gpmc,wr-access-ns = <186>;
|
||||
gpmc,cycle2cycle-samecsen;
|
||||
gpmc,cycle2cycle-diffcsen;
|
||||
vmmc-supply = <&vddvario>;
|
||||
vmmc_aux-supply = <&vdd33a>;
|
||||
vddvario-supply = <&vddvario>;
|
||||
vdd33a-supply = <&vdd33a>;
|
||||
reg-io-width = <4>;
|
||||
smsc,save-mac-address;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -215,3 +215,10 @@
|
|||
&usbhsehci {
|
||||
phys = <0 &hsusb2_phy>;
|
||||
};
|
||||
|
||||
&vaux2 {
|
||||
regulator-name = "usb_1v8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -61,6 +61,14 @@
|
|||
vcc-supply = <&hsusb2_power>;
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "ti,omap-twl4030";
|
||||
ti,model = "omap3beagle";
|
||||
|
||||
ti,mcbsp = <&mcbsp2>;
|
||||
ti,codec = <&twl_audio>;
|
||||
};
|
||||
|
||||
gpio_keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
|
|
@ -120,6 +128,12 @@
|
|||
reg = <0x48>;
|
||||
interrupts = <7>; /* SYS_NIRQ cascaded to intc */
|
||||
interrupt-parent = <&intc>;
|
||||
|
||||
twl_audio: audio {
|
||||
compatible = "ti,twl4030-audio";
|
||||
codec {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -178,3 +192,10 @@
|
|||
mode = <3>;
|
||||
power = <50>;
|
||||
};
|
||||
|
||||
&vaux2 {
|
||||
regulator-name = "vdd_ehci";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Device Tree Source for IGEP Technology devices
|
||||
* Common device tree for IGEP boards based on AM/DM37x
|
||||
*
|
||||
* Copyright (C) 2012 Javier Martinez Canillas <javier@collabora.co.uk>
|
||||
* Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com>
|
||||
|
|
@ -10,7 +10,7 @@
|
|||
*/
|
||||
/dts-v1/;
|
||||
|
||||
#include "omap34xx.dtsi"
|
||||
#include "omap36xx.dtsi"
|
||||
|
||||
/ {
|
||||
memory {
|
||||
|
|
@ -24,6 +24,25 @@
|
|||
ti,mcbsp = <&mcbsp2>;
|
||||
ti,codec = <&twl_audio>;
|
||||
};
|
||||
|
||||
vdd33: regulator-vdd33 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vdd33";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
lbee1usjyc_vmmc: lbee1usjyc_vmmc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&lbee1usjyc_pins>;
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "regulator-lbee1usjyc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>; /* gpio_138 WIFI_PDN */
|
||||
startup-delay-us = <10000>;
|
||||
enable-active-high;
|
||||
vin-supply = <&vdd33>;
|
||||
};
|
||||
};
|
||||
|
||||
&omap3_pmx_core {
|
||||
|
|
@ -48,6 +67,15 @@
|
|||
>;
|
||||
};
|
||||
|
||||
/* WiFi/BT combo */
|
||||
lbee1usjyc_pins: pinmux_lbee1usjyc_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x136 (PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 */
|
||||
0x138 (PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 */
|
||||
0x13a (PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 */
|
||||
>;
|
||||
};
|
||||
|
||||
mcbsp2_pins: pinmux_mcbsp2_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x10c (PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx.mcbsp2_fsx */
|
||||
|
|
@ -65,10 +93,17 @@
|
|||
0x11a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */
|
||||
0x11c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */
|
||||
0x11e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */
|
||||
0x120 (PIN_INPUT | MUX_MODE0) /* sdmmc1_dat4.sdmmc1_dat4 */
|
||||
0x122 (PIN_INPUT | MUX_MODE0) /* sdmmc1_dat5.sdmmc1_dat5 */
|
||||
0x124 (PIN_INPUT | MUX_MODE0) /* sdmmc1_dat6.sdmmc1_dat6 */
|
||||
0x126 (PIN_INPUT | MUX_MODE0) /* sdmmc1_dat7.sdmmc1_dat7 */
|
||||
>;
|
||||
};
|
||||
|
||||
mmc2_pins: pinmux_mmc2_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x128 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */
|
||||
0x12a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */
|
||||
0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */
|
||||
0x12e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */
|
||||
0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */
|
||||
0x132 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */
|
||||
>;
|
||||
};
|
||||
|
||||
|
|
@ -78,10 +113,33 @@
|
|||
>;
|
||||
};
|
||||
|
||||
i2c1_pins: pinmux_i2c1_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x18a (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
|
||||
0x18c (PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
|
||||
>;
|
||||
};
|
||||
|
||||
i2c2_pins: pinmux_i2c2_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x18e (PIN_INPUT | MUX_MODE0) /* i2c2_scl.i2c2_scl */
|
||||
0x190 (PIN_INPUT | MUX_MODE0) /* i2c2_sda.i2c2_sda */
|
||||
>;
|
||||
};
|
||||
|
||||
i2c3_pins: pinmux_i2c3_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x192 (PIN_INPUT | MUX_MODE0) /* i2c3_scl.i2c3_scl */
|
||||
0x194 (PIN_INPUT | MUX_MODE0) /* i2c3_sda.i2c3_sda */
|
||||
>;
|
||||
};
|
||||
|
||||
leds_pins: pinmux_leds_pins { };
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c1_pins>;
|
||||
clock-frequency = <2600000>;
|
||||
|
||||
twl: twl@48 {
|
||||
|
|
@ -101,9 +159,16 @@
|
|||
#include "twl4030_omap3.dtsi"
|
||||
|
||||
&i2c2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c2_pins>;
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c3_pins>;
|
||||
};
|
||||
|
||||
&mcbsp2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcbsp2_pins>;
|
||||
|
|
@ -114,11 +179,15 @@
|
|||
pinctrl-0 = <&mmc1_pins>;
|
||||
vmmc-supply = <&vmmc1>;
|
||||
vmmc_aux-supply = <&vsim>;
|
||||
bus-width = <8>;
|
||||
bus-width = <4>;
|
||||
};
|
||||
|
||||
&mmc2 {
|
||||
status = "disabled";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc2_pins>;
|
||||
vmmc-supply = <&lbee1usjyc_vmmc>;
|
||||
bus-width = <4>;
|
||||
non-removable;
|
||||
};
|
||||
|
||||
&mmc3 {
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Device Tree Source for IGEPv2 board
|
||||
* Device Tree Source for IGEPv2 Rev. (TI OMAP AM/DM37x)
|
||||
*
|
||||
* Copyright (C) 2012 Javier Martinez Canillas <javier@collabora.co.uk>
|
||||
* Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com>
|
||||
|
|
@ -13,7 +13,7 @@
|
|||
#include "omap-gpmc-smsc911x.dtsi"
|
||||
|
||||
/ {
|
||||
model = "IGEPv2";
|
||||
model = "IGEPv2 (TI OMAP AM/DM37x)";
|
||||
compatible = "isee,omap3-igep0020", "ti,omap3";
|
||||
|
||||
leds {
|
||||
|
|
@ -67,6 +67,8 @@
|
|||
pinctrl-names = "default";
|
||||
pinctrl-0 = <
|
||||
&hsusbb1_pins
|
||||
&tfp410_pins
|
||||
&dss_pins
|
||||
>;
|
||||
|
||||
hsusbb1_pins: pinmux_hsusbb1_pins {
|
||||
|
|
@ -85,6 +87,45 @@
|
|||
0x5ba (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d7.hsusb1_data3 */
|
||||
>;
|
||||
};
|
||||
|
||||
tfp410_pins: tfp410_dvi_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x196 (PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */
|
||||
>;
|
||||
};
|
||||
|
||||
dss_pins: pinmux_dss_dvi_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x0a4 (PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
|
||||
0x0a6 (PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
|
||||
0x0a8 (PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
|
||||
0x0aa (PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */
|
||||
0x0ac (PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */
|
||||
0x0ae (PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */
|
||||
0x0b0 (PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */
|
||||
0x0b2 (PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */
|
||||
0x0b4 (PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */
|
||||
0x0b6 (PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */
|
||||
0x0b8 (PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */
|
||||
0x0ba (PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */
|
||||
0x0bc (PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */
|
||||
0x0be (PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */
|
||||
0x0c0 (PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */
|
||||
0x0c2 (PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */
|
||||
0x0c4 (PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */
|
||||
0x0c6 (PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */
|
||||
0x0c8 (PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */
|
||||
0x0ca (PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */
|
||||
0x0cc (PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */
|
||||
0x0ce (PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */
|
||||
0x0d0 (PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */
|
||||
0x0d2 (PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */
|
||||
0x0d4 (PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */
|
||||
0x0d6 (PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */
|
||||
0x0d8 (PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */
|
||||
0x0da (PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&leds_pins {
|
||||
|
|
@ -174,3 +215,8 @@
|
|||
&usbhsehci {
|
||||
phys = <&hsusb1_phy>;
|
||||
};
|
||||
|
||||
&vpll2 {
|
||||
/* Needed for DSS */
|
||||
regulator-name = "vdds_dsi";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Device Tree Source for IGEP COM Module
|
||||
* Device Tree Source for IGEP COM MODULE (TI OMAP AM/DM37x)
|
||||
*
|
||||
* Copyright (C) 2012 Javier Martinez Canillas <javier@collabora.co.uk>
|
||||
* Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com>
|
||||
|
|
@ -12,7 +12,7 @@
|
|||
#include "omap3-igep.dtsi"
|
||||
|
||||
/ {
|
||||
model = "IGEP COM Module";
|
||||
model = "IGEP COM MODULE (TI OMAP AM/DM37x)";
|
||||
compatible = "isee,omap3-igep0030", "ti,omap3";
|
||||
|
||||
leds {
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@
|
|||
|
||||
/dts-v1/;
|
||||
|
||||
#include "omap34xx.dtsi"
|
||||
#include "omap34xx-hs.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Nokia N900";
|
||||
|
|
@ -125,6 +125,21 @@
|
|||
>;
|
||||
};
|
||||
|
||||
mmc2_pins: pinmux_mmc2_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x128 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk */
|
||||
0x12a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd */
|
||||
0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0 */
|
||||
0x12e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1 */
|
||||
0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2 */
|
||||
0x132 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3 */
|
||||
0x134 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat4 */
|
||||
0x136 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat5 */
|
||||
0x138 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat6 */
|
||||
0x13a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat7 */
|
||||
>;
|
||||
};
|
||||
|
||||
display_pins: pinmux_display_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x0d4 (PIN_OUTPUT | MUX_MODE4) /* RX51_LCD_RESET_GPIO */
|
||||
|
|
@ -358,8 +373,14 @@
|
|||
cd-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>; /* 160 */
|
||||
};
|
||||
|
||||
/* most boards use vaux3, only some old versions use vmmc2 instead */
|
||||
&mmc2 {
|
||||
status = "disabled";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc2_pins>;
|
||||
vmmc-supply = <&vaux3>;
|
||||
vmmc_aux-supply = <&vsim>;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
};
|
||||
|
||||
&mmc3 {
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include "omap36xx.dtsi"
|
||||
#include "omap36xx-hs.dtsi"
|
||||
|
||||
/ {
|
||||
cpus {
|
||||
|
|
|
|||
|
|
@ -82,6 +82,13 @@
|
|||
ranges;
|
||||
ti,hwmods = "l3_main";
|
||||
|
||||
aes: aes@480c5000 {
|
||||
compatible = "ti,omap3-aes";
|
||||
ti,hwmods = "aes";
|
||||
reg = <0x480c5000 0x50>;
|
||||
interrupts = <0>;
|
||||
};
|
||||
|
||||
counter32k: counter@48320000 {
|
||||
compatible = "ti,omap-counter32k";
|
||||
reg = <0x48320000 0x20>;
|
||||
|
|
@ -260,6 +267,13 @@
|
|||
ti,hwmods = "i2c3";
|
||||
};
|
||||
|
||||
mailbox: mailbox@48094000 {
|
||||
compatible = "ti,omap3-mailbox";
|
||||
ti,hwmods = "mailbox";
|
||||
reg = <0x48094000 0x200>;
|
||||
interrupts = <26>;
|
||||
};
|
||||
|
||||
mcspi1: spi@48098000 {
|
||||
compatible = "ti,omap2-mcspi";
|
||||
reg = <0x48098000 0x100>;
|
||||
|
|
@ -357,6 +371,13 @@
|
|||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
mmu_isp: mmu@480bd400 {
|
||||
compatible = "ti,omap3-mmu-isp";
|
||||
ti,hwmods = "mmu_isp";
|
||||
reg = <0x480bd400 0x80>;
|
||||
interrupts = <8>;
|
||||
};
|
||||
|
||||
wdt2: wdt@48314000 {
|
||||
compatible = "ti,omap3-wdt";
|
||||
reg = <0x48314000 0x80>;
|
||||
|
|
@ -442,6 +463,27 @@
|
|||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
sham: sham@480c3000 {
|
||||
compatible = "ti,omap3-sham";
|
||||
ti,hwmods = "sham";
|
||||
reg = <0x480c3000 0x64>;
|
||||
interrupts = <49>;
|
||||
};
|
||||
|
||||
smartreflex_core: smartreflex@480cb000 {
|
||||
compatible = "ti,omap3-smartreflex-core";
|
||||
ti,hwmods = "smartreflex_core";
|
||||
reg = <0x480cb000 0x400>;
|
||||
interrupts = <19>;
|
||||
};
|
||||
|
||||
smartreflex_mpu_iva: smartreflex@480c9000 {
|
||||
compatible = "ti,omap3-smartreflex-iva";
|
||||
ti,hwmods = "smartreflex_mpu_iva";
|
||||
reg = <0x480c9000 0x400>;
|
||||
interrupts = <18>;
|
||||
};
|
||||
|
||||
timer1: timer@48318000 {
|
||||
compatible = "ti,omap3430-timer";
|
||||
reg = <0x48318000 0x400>;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,16 @@
|
|||
/* Disabled modules for secure omaps */
|
||||
|
||||
#include "omap34xx.dtsi"
|
||||
|
||||
/* Secure omaps have some devices inaccessible depending on the firmware */
|
||||
&aes {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&sham {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&timer12 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
/* Disabled modules for secure omaps */
|
||||
|
||||
#include "omap36xx.dtsi"
|
||||
|
||||
/* Secure omaps have some devices inaccessible depending on the firmware */
|
||||
&aes {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&sham {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&timer12 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -246,15 +246,6 @@
|
|||
0xf0 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&omap4_pmx_wkup {
|
||||
led_wkgpio_pins: pinmux_leds_wkpins {
|
||||
pinctrl-single,pins = <
|
||||
0x1a (PIN_OUTPUT | MUX_MODE3) /* gpio_wk7 */
|
||||
0x1c (PIN_OUTPUT | MUX_MODE3) /* gpio_wk8 */
|
||||
>;
|
||||
};
|
||||
|
||||
/*
|
||||
* wl12xx GPIO outputs for WLAN_EN, BT_EN, FM_EN, BT_WAKEUP
|
||||
|
|
@ -274,7 +265,7 @@
|
|||
pinctrl-single,pins = <
|
||||
0x38 (PIN_INPUT | MUX_MODE3) /* gpmc_ncs2.gpio_52 */
|
||||
0x3a (PIN_INPUT | MUX_MODE3) /* gpmc_ncs3.gpio_53 */
|
||||
0x108 (PIN_OUTPUT | MUX_MODE0) /* sdmmc5_clk.sdmmc5_clk */
|
||||
0x108 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_clk.sdmmc5_clk */
|
||||
0x10a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_cmd.sdmmc5_cmd */
|
||||
0x10c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat0.sdmmc5_dat0 */
|
||||
0x10e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat1.sdmmc5_dat1 */
|
||||
|
|
@ -284,6 +275,15 @@
|
|||
};
|
||||
};
|
||||
|
||||
&omap4_pmx_wkup {
|
||||
led_wkgpio_pins: pinmux_leds_wkpins {
|
||||
pinctrl-single,pins = <
|
||||
0x1a (PIN_OUTPUT | MUX_MODE3) /* gpio_wk7 */
|
||||
0x1c (PIN_OUTPUT | MUX_MODE3) /* gpio_wk8 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c1_pins>;
|
||||
|
|
|
|||
|
|
@ -300,12 +300,12 @@
|
|||
wl12xx_pins: pinmux_wl12xx_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x3a (PIN_INPUT | MUX_MODE3) /* gpmc_ncs3.gpio_53 */
|
||||
0x108 (PIN_OUTPUT | MUX_MODE3) /* sdmmc5_clk.sdmmc5_clk */
|
||||
0x10a (PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc5_cmd.sdmmc5_cmd */
|
||||
0x10c (PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc5_dat0.sdmmc5_dat0 */
|
||||
0x10e (PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc5_dat1.sdmmc5_dat1 */
|
||||
0x110 (PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc5_dat2.sdmmc5_dat2 */
|
||||
0x112 (PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc5_dat3.sdmmc5_dat3 */
|
||||
0x108 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_clk.sdmmc5_clk */
|
||||
0x10a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_cmd.sdmmc5_cmd */
|
||||
0x10c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat0.sdmmc5_dat0 */
|
||||
0x10e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat1.sdmmc5_dat1 */
|
||||
0x110 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat2.sdmmc5_dat2 */
|
||||
0x112 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat3.sdmmc5_dat3 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -87,9 +87,9 @@
|
|||
interrupts = <1 9 0xf04>;
|
||||
};
|
||||
|
||||
gpio0: gpio@ffc40000 {
|
||||
gpio0: gpio@e6050000 {
|
||||
compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
|
||||
reg = <0 0xffc40000 0 0x2c>;
|
||||
reg = <0 0xe6050000 0 0x50>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 4 0x4>;
|
||||
#gpio-cells = <2>;
|
||||
|
|
@ -99,9 +99,9 @@
|
|||
interrupt-controller;
|
||||
};
|
||||
|
||||
gpio1: gpio@ffc41000 {
|
||||
gpio1: gpio@e6051000 {
|
||||
compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
|
||||
reg = <0 0xffc41000 0 0x2c>;
|
||||
reg = <0 0xe6051000 0 0x50>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 5 0x4>;
|
||||
#gpio-cells = <2>;
|
||||
|
|
@ -111,9 +111,9 @@
|
|||
interrupt-controller;
|
||||
};
|
||||
|
||||
gpio2: gpio@ffc42000 {
|
||||
gpio2: gpio@e6052000 {
|
||||
compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
|
||||
reg = <0 0xffc42000 0 0x2c>;
|
||||
reg = <0 0xe6052000 0 0x50>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 6 0x4>;
|
||||
#gpio-cells = <2>;
|
||||
|
|
@ -123,9 +123,9 @@
|
|||
interrupt-controller;
|
||||
};
|
||||
|
||||
gpio3: gpio@ffc43000 {
|
||||
gpio3: gpio@e6053000 {
|
||||
compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
|
||||
reg = <0 0xffc43000 0 0x2c>;
|
||||
reg = <0 0xe6053000 0 0x50>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 7 0x4>;
|
||||
#gpio-cells = <2>;
|
||||
|
|
@ -135,9 +135,9 @@
|
|||
interrupt-controller;
|
||||
};
|
||||
|
||||
gpio4: gpio@ffc44000 {
|
||||
gpio4: gpio@e6054000 {
|
||||
compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
|
||||
reg = <0 0xffc44000 0 0x2c>;
|
||||
reg = <0 0xe6054000 0 0x50>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 8 0x4>;
|
||||
#gpio-cells = <2>;
|
||||
|
|
@ -147,9 +147,9 @@
|
|||
interrupt-controller;
|
||||
};
|
||||
|
||||
gpio5: gpio@ffc45000 {
|
||||
gpio5: gpio@e6055000 {
|
||||
compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
|
||||
reg = <0 0xffc45000 0 0x2c>;
|
||||
reg = <0 0xe6055000 0 0x50>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 9 0x4>;
|
||||
#gpio-cells = <2>;
|
||||
|
|
@ -241,7 +241,7 @@
|
|||
|
||||
sdhi0: sdhi@ee100000 {
|
||||
compatible = "renesas,sdhi-r8a7790";
|
||||
reg = <0 0xee100000 0 0x100>;
|
||||
reg = <0 0xee100000 0 0x200>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 165 4>;
|
||||
cap-sd-highspeed;
|
||||
|
|
@ -250,7 +250,7 @@
|
|||
|
||||
sdhi1: sdhi@ee120000 {
|
||||
compatible = "renesas,sdhi-r8a7790";
|
||||
reg = <0 0xee120000 0 0x100>;
|
||||
reg = <0 0xee120000 0 0x200>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 166 4>;
|
||||
cap-sd-highspeed;
|
||||
|
|
|
|||
|
|
@ -245,14 +245,14 @@
|
|||
|
||||
mpu_periph_clk: mpu_periph_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-gate-clk";
|
||||
compatible = "altr,socfpga-perip-clk";
|
||||
clocks = <&mpuclk>;
|
||||
fixed-divider = <4>;
|
||||
};
|
||||
|
||||
mpu_l2_ram_clk: mpu_l2_ram_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-gate-clk";
|
||||
compatible = "altr,socfpga-perip-clk";
|
||||
clocks = <&mpuclk>;
|
||||
fixed-divider = <2>;
|
||||
};
|
||||
|
|
@ -266,8 +266,9 @@
|
|||
|
||||
l3_main_clk: l3_main_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-gate-clk";
|
||||
compatible = "altr,socfpga-perip-clk";
|
||||
clocks = <&mainclk>;
|
||||
fixed-divider = <1>;
|
||||
};
|
||||
|
||||
l3_mp_clk: l3_mp_clk {
|
||||
|
|
|
|||
|
|
@ -193,7 +193,10 @@
|
|||
pio: pinctrl@01c20800 {
|
||||
compatible = "allwinner,sun6i-a31-pinctrl";
|
||||
reg = <0x01c20800 0x400>;
|
||||
interrupts = <0 11 1>, <0 15 1>, <0 16 1>, <0 17 1>;
|
||||
interrupts = <0 11 4>,
|
||||
<0 15 4>,
|
||||
<0 16 4>,
|
||||
<0 17 4>;
|
||||
clocks = <&apb1_gates 5>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
|
|
@ -212,11 +215,11 @@
|
|||
timer@01c20c00 {
|
||||
compatible = "allwinner,sun4i-timer";
|
||||
reg = <0x01c20c00 0xa0>;
|
||||
interrupts = <0 18 1>,
|
||||
<0 19 1>,
|
||||
<0 20 1>,
|
||||
<0 21 1>,
|
||||
<0 22 1>;
|
||||
interrupts = <0 18 4>,
|
||||
<0 19 4>,
|
||||
<0 20 4>,
|
||||
<0 21 4>,
|
||||
<0 22 4>;
|
||||
clocks = <&osc24M>;
|
||||
};
|
||||
|
||||
|
|
@ -228,7 +231,7 @@
|
|||
uart0: serial@01c28000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x01c28000 0x400>;
|
||||
interrupts = <0 0 1>;
|
||||
interrupts = <0 0 4>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&apb2_gates 16>;
|
||||
|
|
@ -238,7 +241,7 @@
|
|||
uart1: serial@01c28400 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x01c28400 0x400>;
|
||||
interrupts = <0 1 1>;
|
||||
interrupts = <0 1 4>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&apb2_gates 17>;
|
||||
|
|
@ -248,7 +251,7 @@
|
|||
uart2: serial@01c28800 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x01c28800 0x400>;
|
||||
interrupts = <0 2 1>;
|
||||
interrupts = <0 2 4>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&apb2_gates 18>;
|
||||
|
|
@ -258,7 +261,7 @@
|
|||
uart3: serial@01c28c00 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x01c28c00 0x400>;
|
||||
interrupts = <0 3 1>;
|
||||
interrupts = <0 3 4>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&apb2_gates 19>;
|
||||
|
|
@ -268,7 +271,7 @@
|
|||
uart4: serial@01c29000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x01c29000 0x400>;
|
||||
interrupts = <0 4 1>;
|
||||
interrupts = <0 4 4>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&apb2_gates 20>;
|
||||
|
|
@ -278,7 +281,7 @@
|
|||
uart5: serial@01c29400 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x01c29400 0x400>;
|
||||
interrupts = <0 5 1>;
|
||||
interrupts = <0 5 4>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&apb2_gates 21>;
|
||||
|
|
|
|||
|
|
@ -170,7 +170,7 @@
|
|||
emac: ethernet@01c0b000 {
|
||||
compatible = "allwinner,sun4i-emac";
|
||||
reg = <0x01c0b000 0x1000>;
|
||||
interrupts = <0 55 1>;
|
||||
interrupts = <0 55 4>;
|
||||
clocks = <&ahb_gates 17>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -186,7 +186,7 @@
|
|||
pio: pinctrl@01c20800 {
|
||||
compatible = "allwinner,sun7i-a20-pinctrl";
|
||||
reg = <0x01c20800 0x400>;
|
||||
interrupts = <0 28 1>;
|
||||
interrupts = <0 28 4>;
|
||||
clocks = <&apb0_gates 5>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
|
|
@ -251,12 +251,12 @@
|
|||
timer@01c20c00 {
|
||||
compatible = "allwinner,sun4i-timer";
|
||||
reg = <0x01c20c00 0x90>;
|
||||
interrupts = <0 22 1>,
|
||||
<0 23 1>,
|
||||
<0 24 1>,
|
||||
<0 25 1>,
|
||||
<0 67 1>,
|
||||
<0 68 1>;
|
||||
interrupts = <0 22 4>,
|
||||
<0 23 4>,
|
||||
<0 24 4>,
|
||||
<0 25 4>,
|
||||
<0 67 4>,
|
||||
<0 68 4>;
|
||||
clocks = <&osc24M>;
|
||||
};
|
||||
|
||||
|
|
@ -273,7 +273,7 @@
|
|||
uart0: serial@01c28000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x01c28000 0x400>;
|
||||
interrupts = <0 1 1>;
|
||||
interrupts = <0 1 4>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&apb1_gates 16>;
|
||||
|
|
@ -283,7 +283,7 @@
|
|||
uart1: serial@01c28400 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x01c28400 0x400>;
|
||||
interrupts = <0 2 1>;
|
||||
interrupts = <0 2 4>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&apb1_gates 17>;
|
||||
|
|
@ -293,7 +293,7 @@
|
|||
uart2: serial@01c28800 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x01c28800 0x400>;
|
||||
interrupts = <0 3 1>;
|
||||
interrupts = <0 3 4>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&apb1_gates 18>;
|
||||
|
|
@ -303,7 +303,7 @@
|
|||
uart3: serial@01c28c00 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x01c28c00 0x400>;
|
||||
interrupts = <0 4 1>;
|
||||
interrupts = <0 4 4>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&apb1_gates 19>;
|
||||
|
|
@ -313,7 +313,7 @@
|
|||
uart4: serial@01c29000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x01c29000 0x400>;
|
||||
interrupts = <0 17 1>;
|
||||
interrupts = <0 17 4>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&apb1_gates 20>;
|
||||
|
|
@ -323,7 +323,7 @@
|
|||
uart5: serial@01c29400 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x01c29400 0x400>;
|
||||
interrupts = <0 18 1>;
|
||||
interrupts = <0 18 4>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&apb1_gates 21>;
|
||||
|
|
@ -333,7 +333,7 @@
|
|||
uart6: serial@01c29800 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x01c29800 0x400>;
|
||||
interrupts = <0 19 1>;
|
||||
interrupts = <0 19 4>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&apb1_gates 22>;
|
||||
|
|
@ -343,7 +343,7 @@
|
|||
uart7: serial@01c29c00 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x01c29c00 0x400>;
|
||||
interrupts = <0 20 1>;
|
||||
interrupts = <0 20 4>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&apb1_gates 23>;
|
||||
|
|
@ -353,7 +353,7 @@
|
|||
i2c0: i2c@01c2ac00 {
|
||||
compatible = "allwinner,sun4i-i2c";
|
||||
reg = <0x01c2ac00 0x400>;
|
||||
interrupts = <0 7 1>;
|
||||
interrupts = <0 7 4>;
|
||||
clocks = <&apb1_gates 0>;
|
||||
clock-frequency = <100000>;
|
||||
status = "disabled";
|
||||
|
|
@ -362,7 +362,7 @@
|
|||
i2c1: i2c@01c2b000 {
|
||||
compatible = "allwinner,sun4i-i2c";
|
||||
reg = <0x01c2b000 0x400>;
|
||||
interrupts = <0 8 1>;
|
||||
interrupts = <0 8 4>;
|
||||
clocks = <&apb1_gates 1>;
|
||||
clock-frequency = <100000>;
|
||||
status = "disabled";
|
||||
|
|
@ -371,7 +371,7 @@
|
|||
i2c2: i2c@01c2b400 {
|
||||
compatible = "allwinner,sun4i-i2c";
|
||||
reg = <0x01c2b400 0x400>;
|
||||
interrupts = <0 9 1>;
|
||||
interrupts = <0 9 4>;
|
||||
clocks = <&apb1_gates 2>;
|
||||
clock-frequency = <100000>;
|
||||
status = "disabled";
|
||||
|
|
@ -380,7 +380,7 @@
|
|||
i2c3: i2c@01c2b800 {
|
||||
compatible = "allwinner,sun4i-i2c";
|
||||
reg = <0x01c2b800 0x400>;
|
||||
interrupts = <0 88 1>;
|
||||
interrupts = <0 88 4>;
|
||||
clocks = <&apb1_gates 3>;
|
||||
clock-frequency = <100000>;
|
||||
status = "disabled";
|
||||
|
|
@ -389,7 +389,7 @@
|
|||
i2c4: i2c@01c2bc00 {
|
||||
compatible = "allwinner,sun4i-i2c";
|
||||
reg = <0x01c2bc00 0x400>;
|
||||
interrupts = <0 89 1>;
|
||||
interrupts = <0 89 4>;
|
||||
clocks = <&apb1_gates 15>;
|
||||
clock-frequency = <100000>;
|
||||
status = "disabled";
|
||||
|
|
|
|||
|
|
@ -69,6 +69,7 @@ CONFIG_KS8851=y
|
|||
CONFIG_SMSC911X=y
|
||||
CONFIG_STMMAC_ETH=y
|
||||
CONFIG_MDIO_SUN4I=y
|
||||
CONFIG_TI_CPSW=y
|
||||
CONFIG_KEYBOARD_SPEAR=y
|
||||
CONFIG_SERIO_AMBAKMI=y
|
||||
CONFIG_SERIAL_8250=y
|
||||
|
|
@ -133,12 +134,14 @@ CONFIG_USB_GPIO_VBUS=y
|
|||
CONFIG_USB_ISP1301=y
|
||||
CONFIG_USB_MXS_PHY=y
|
||||
CONFIG_MMC=y
|
||||
CONFIG_MMC_BLOCK_MINORS=16
|
||||
CONFIG_MMC_ARMMMCI=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_PLTFM=y
|
||||
CONFIG_MMC_SDHCI_ESDHC_IMX=y
|
||||
CONFIG_MMC_SDHCI_TEGRA=y
|
||||
CONFIG_MMC_SDHCI_SPEAR=y
|
||||
CONFIG_MMC_SDHCI_BCM_KONA=y
|
||||
CONFIG_MMC_OMAP=y
|
||||
CONFIG_MMC_OMAP_HS=y
|
||||
CONFIG_EDAC=y
|
||||
|
|
|
|||
|
|
@ -173,6 +173,7 @@ CONFIG_MFD_PALMAS=y
|
|||
CONFIG_MFD_TPS65217=y
|
||||
CONFIG_MFD_TPS65910=y
|
||||
CONFIG_TWL6040_CORE=y
|
||||
CONFIG_REGULATOR_FIXED_VOLTAGE=y
|
||||
CONFIG_REGULATOR_PALMAS=y
|
||||
CONFIG_REGULATOR_TPS65023=y
|
||||
CONFIG_REGULATOR_TPS6507X=y
|
||||
|
|
|
|||
|
|
@ -12,6 +12,9 @@ CONFIG_NET=y
|
|||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_PNP=y
|
||||
CONFIG_IP_PNP_DHCP=y
|
||||
CONFIG_IP_PNP_BOOTP=y
|
||||
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
|
||||
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
|
||||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
||||
|
|
@ -58,4 +61,8 @@ CONFIG_LEDS_TRIGGER_HEARTBEAT=y
|
|||
CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
|
||||
CONFIG_COMMON_CLK_DEBUG=y
|
||||
# CONFIG_IOMMU_SUPPORT is not set
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_ROOT_NFS=y
|
||||
CONFIG_NLS=y
|
||||
CONFIG_PRINTK_TIME=y
|
||||
|
|
|
|||
|
|
@ -22,6 +22,7 @@ CONFIG_CMDLINE="root=/dev/ram0 console=ttyAMA2,115200n8"
|
|||
CONFIG_CPU_FREQ=y
|
||||
CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
|
||||
CONFIG_CPU_IDLE=y
|
||||
CONFIG_ARM_U8500_CPUIDLE=y
|
||||
CONFIG_VFP=y
|
||||
CONFIG_NEON=y
|
||||
CONFIG_PM_RUNTIME=y
|
||||
|
|
@ -109,6 +110,8 @@ CONFIG_EXT2_FS_SECURITY=y
|
|||
CONFIG_EXT3_FS=y
|
||||
CONFIG_EXT4_FS=y
|
||||
CONFIG_VFAT_FS=y
|
||||
CONFIG_DEVTMPFS=y
|
||||
CONFIG_DEVTMPFS_MOUNT=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_TMPFS_POSIX_ACL=y
|
||||
# CONFIG_MISC_FILESYSTEMS is not set
|
||||
|
|
|
|||
|
|
@ -58,7 +58,7 @@
|
|||
# define VFP_ABI_FRAME 0
|
||||
# define BSAES_ASM_EXTENDED_KEY
|
||||
# define XTS_CHAIN_TWEAK
|
||||
# define __ARM_ARCH__ __LINUX_ARM_ARCH__
|
||||
# define __ARM_ARCH__ 7
|
||||
#endif
|
||||
|
||||
#ifdef __thumb__
|
||||
|
|
|
|||
|
|
@ -701,7 +701,7 @@ $code.=<<___;
|
|||
# define VFP_ABI_FRAME 0
|
||||
# define BSAES_ASM_EXTENDED_KEY
|
||||
# define XTS_CHAIN_TWEAK
|
||||
# define __ARM_ARCH__ __LINUX_ARM_ARCH__
|
||||
# define __ARM_ARCH__ 7
|
||||
#endif
|
||||
|
||||
#ifdef __thumb__
|
||||
|
|
|
|||
|
|
@ -329,7 +329,7 @@ extern void _memset_io(volatile void __iomem *, int, size_t);
|
|||
*/
|
||||
#define ioremap(cookie,size) __arm_ioremap((cookie), (size), MT_DEVICE)
|
||||
#define ioremap_nocache(cookie,size) __arm_ioremap((cookie), (size), MT_DEVICE)
|
||||
#define ioremap_cached(cookie,size) __arm_ioremap((cookie), (size), MT_DEVICE_CACHED)
|
||||
#define ioremap_cache(cookie,size) __arm_ioremap((cookie), (size), MT_DEVICE_CACHED)
|
||||
#define ioremap_wc(cookie,size) __arm_ioremap((cookie), (size), MT_DEVICE_WC)
|
||||
#define iounmap __arm_iounmap
|
||||
|
||||
|
|
|
|||
|
|
@ -100,23 +100,19 @@
|
|||
#define TASK_UNMAPPED_BASE UL(0x00000000)
|
||||
#endif
|
||||
|
||||
#ifndef PHYS_OFFSET
|
||||
#define PHYS_OFFSET UL(CONFIG_DRAM_BASE)
|
||||
#endif
|
||||
|
||||
#ifndef END_MEM
|
||||
#define END_MEM (UL(CONFIG_DRAM_BASE) + CONFIG_DRAM_SIZE)
|
||||
#endif
|
||||
|
||||
#ifndef PAGE_OFFSET
|
||||
#define PAGE_OFFSET (PHYS_OFFSET)
|
||||
#define PAGE_OFFSET PLAT_PHYS_OFFSET
|
||||
#endif
|
||||
|
||||
/*
|
||||
* The module can be at any place in ram in nommu mode.
|
||||
*/
|
||||
#define MODULES_END (END_MEM)
|
||||
#define MODULES_VADDR (PHYS_OFFSET)
|
||||
#define MODULES_VADDR PAGE_OFFSET
|
||||
|
||||
#define XIP_VIRT_ADDR(physaddr) (physaddr)
|
||||
|
||||
|
|
@ -157,6 +153,16 @@
|
|||
#endif
|
||||
#define ARCH_PGD_MASK ((1 << ARCH_PGD_SHIFT) - 1)
|
||||
|
||||
/*
|
||||
* PLAT_PHYS_OFFSET is the offset (from zero) of the start of physical
|
||||
* memory. This is used for XIP and NoMMU kernels, or by kernels which
|
||||
* have their own mach/memory.h. Assembly code must always use
|
||||
* PLAT_PHYS_OFFSET and not PHYS_OFFSET.
|
||||
*/
|
||||
#ifndef PLAT_PHYS_OFFSET
|
||||
#define PLAT_PHYS_OFFSET UL(CONFIG_PHYS_OFFSET)
|
||||
#endif
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/*
|
||||
|
|
@ -239,6 +245,8 @@ static inline unsigned long __phys_to_virt(phys_addr_t x)
|
|||
|
||||
#else
|
||||
|
||||
#define PHYS_OFFSET PLAT_PHYS_OFFSET
|
||||
|
||||
static inline phys_addr_t __virt_to_phys(unsigned long x)
|
||||
{
|
||||
return (phys_addr_t)x - PAGE_OFFSET + PHYS_OFFSET;
|
||||
|
|
@ -251,17 +259,6 @@ static inline unsigned long __phys_to_virt(phys_addr_t x)
|
|||
|
||||
#endif
|
||||
#endif
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#ifndef PHYS_OFFSET
|
||||
#ifdef PLAT_PHYS_OFFSET
|
||||
#define PHYS_OFFSET PLAT_PHYS_OFFSET
|
||||
#else
|
||||
#define PHYS_OFFSET UL(CONFIG_PHYS_OFFSET)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/*
|
||||
* PFNs are used to describe any physical page; this means
|
||||
|
|
@ -350,7 +347,8 @@ static inline __deprecated void *bus_to_virt(unsigned long x)
|
|||
#define ARCH_PFN_OFFSET PHYS_PFN_OFFSET
|
||||
|
||||
#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
|
||||
#define virt_addr_valid(kaddr) ((unsigned long)(kaddr) >= PAGE_OFFSET && (unsigned long)(kaddr) < (unsigned long)high_memory)
|
||||
#define virt_addr_valid(kaddr) (((unsigned long)(kaddr) >= PAGE_OFFSET && (unsigned long)(kaddr) < (unsigned long)high_memory) \
|
||||
&& pfn_valid(__pa(kaddr) >> PAGE_SHIFT) )
|
||||
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -117,6 +117,6 @@ static inline bool set_phys_to_machine(unsigned long pfn, unsigned long mfn)
|
|||
return __set_phys_to_machine(pfn, mfn);
|
||||
}
|
||||
|
||||
#define xen_remap(cookie, size) ioremap_cached((cookie), (size));
|
||||
#define xen_remap(cookie, size) ioremap_cache((cookie), (size));
|
||||
|
||||
#endif /* _ASM_ARM_XEN_PAGE_H */
|
||||
|
|
|
|||
|
|
@ -68,7 +68,7 @@ ENTRY(stext)
|
|||
|
||||
#ifdef CONFIG_ARM_MPU
|
||||
/* Calculate the size of a region covering just the kernel */
|
||||
ldr r5, =PHYS_OFFSET @ Region start: PHYS_OFFSET
|
||||
ldr r5, =PLAT_PHYS_OFFSET @ Region start: PHYS_OFFSET
|
||||
ldr r6, =(_end) @ Cover whole kernel
|
||||
sub r6, r6, r5 @ Minimum size of region to map
|
||||
clz r6, r6 @ Region size must be 2^N...
|
||||
|
|
@ -213,7 +213,7 @@ ENTRY(__setup_mpu)
|
|||
set_region_nr r0, #MPU_RAM_REGION
|
||||
isb
|
||||
/* Full access from PL0, PL1, shared for CONFIG_SMP, cacheable */
|
||||
ldr r0, =PHYS_OFFSET @ RAM starts at PHYS_OFFSET
|
||||
ldr r0, =PLAT_PHYS_OFFSET @ RAM starts at PHYS_OFFSET
|
||||
ldr r5,=(MPU_AP_PL1RW_PL0RW | MPU_RGN_NORMAL)
|
||||
|
||||
setup_region r0, r5, r6, MPU_DATA_SIDE @ PHYS_OFFSET, shared, enabled
|
||||
|
|
|
|||
|
|
@ -110,7 +110,7 @@ ENTRY(stext)
|
|||
sub r4, r3, r4 @ (PHYS_OFFSET - PAGE_OFFSET)
|
||||
add r8, r8, r4 @ PHYS_OFFSET
|
||||
#else
|
||||
ldr r8, =PHYS_OFFSET @ always constant in this case
|
||||
ldr r8, =PLAT_PHYS_OFFSET @ always constant in this case
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -404,6 +404,7 @@ EXPORT_SYMBOL(dump_fpu);
|
|||
unsigned long get_wchan(struct task_struct *p)
|
||||
{
|
||||
struct stackframe frame;
|
||||
unsigned long stack_page;
|
||||
int count = 0;
|
||||
if (!p || p == current || p->state == TASK_RUNNING)
|
||||
return 0;
|
||||
|
|
@ -412,9 +413,11 @@ unsigned long get_wchan(struct task_struct *p)
|
|||
frame.sp = thread_saved_sp(p);
|
||||
frame.lr = 0; /* recovered from the stack */
|
||||
frame.pc = thread_saved_pc(p);
|
||||
stack_page = (unsigned long)task_stack_page(p);
|
||||
do {
|
||||
int ret = unwind_frame(&frame);
|
||||
if (ret < 0)
|
||||
if (frame.sp < stack_page ||
|
||||
frame.sp >= stack_page + THREAD_SIZE ||
|
||||
unwind_frame(&frame) < 0)
|
||||
return 0;
|
||||
if (!in_sched_functions(frame.pc))
|
||||
return frame.pc;
|
||||
|
|
|
|||
|
|
@ -873,8 +873,6 @@ void __init setup_arch(char **cmdline_p)
|
|||
machine_desc = mdesc;
|
||||
machine_name = mdesc->name;
|
||||
|
||||
setup_dma_zone(mdesc);
|
||||
|
||||
if (mdesc->reboot_mode != REBOOT_HARD)
|
||||
reboot_mode = mdesc->reboot_mode;
|
||||
|
||||
|
|
@ -892,6 +890,7 @@ void __init setup_arch(char **cmdline_p)
|
|||
sort(&meminfo.bank, meminfo.nr_banks, sizeof(meminfo.bank[0]), meminfo_cmp, NULL);
|
||||
|
||||
early_paging_init(mdesc, lookup_processor_type(read_cpuid_id()));
|
||||
setup_dma_zone(mdesc);
|
||||
sanity_check_meminfo();
|
||||
arm_memblock_init(&meminfo, mdesc);
|
||||
|
||||
|
|
|
|||
|
|
@ -31,7 +31,7 @@ int notrace unwind_frame(struct stackframe *frame)
|
|||
high = ALIGN(low, THREAD_SIZE);
|
||||
|
||||
/* check current frame pointer is within bounds */
|
||||
if (fp < (low + 12) || fp + 4 >= high)
|
||||
if (fp < low + 12 || fp > high - 4)
|
||||
return -EINVAL;
|
||||
|
||||
/* restore the registers from the stack frame */
|
||||
|
|
|
|||
|
|
@ -36,7 +36,13 @@
|
|||
#include <asm/system_misc.h>
|
||||
#include <asm/opcodes.h>
|
||||
|
||||
static const char *handler[]= { "prefetch abort", "data abort", "address exception", "interrupt" };
|
||||
static const char *handler[]= {
|
||||
"prefetch abort",
|
||||
"data abort",
|
||||
"address exception",
|
||||
"interrupt",
|
||||
"undefined instruction",
|
||||
};
|
||||
|
||||
void *vectors_page;
|
||||
|
||||
|
|
@ -509,9 +515,10 @@ static inline int
|
|||
__do_cache_op(unsigned long start, unsigned long end)
|
||||
{
|
||||
int ret;
|
||||
unsigned long chunk = PAGE_SIZE;
|
||||
|
||||
do {
|
||||
unsigned long chunk = min(PAGE_SIZE, end - start);
|
||||
|
||||
if (signal_pending(current)) {
|
||||
struct thread_info *ti = current_thread_info();
|
||||
|
||||
|
|
|
|||
|
|
@ -174,7 +174,6 @@ clkevt32k_next_event(unsigned long delta, struct clock_event_device *dev)
|
|||
static struct clock_event_device clkevt = {
|
||||
.name = "at91_tick",
|
||||
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
|
||||
.shift = 32,
|
||||
.rating = 150,
|
||||
.set_next_event = clkevt32k_next_event,
|
||||
.set_mode = clkevt32k_mode,
|
||||
|
|
@ -265,11 +264,9 @@ void __init at91rm9200_timer_init(void)
|
|||
at91_st_write(AT91_ST_RTMR, 1);
|
||||
|
||||
/* Setup timer clockevent, with minimum of two ticks (important!!) */
|
||||
clkevt.mult = div_sc(AT91_SLOW_CLOCK, NSEC_PER_SEC, clkevt.shift);
|
||||
clkevt.max_delta_ns = clockevent_delta2ns(AT91_ST_ALMV, &clkevt);
|
||||
clkevt.min_delta_ns = clockevent_delta2ns(2, &clkevt) + 1;
|
||||
clkevt.cpumask = cpumask_of(0);
|
||||
clockevents_register_device(&clkevt);
|
||||
clockevents_config_and_register(&clkevt, AT91_SLOW_CLOCK,
|
||||
2, AT91_ST_ALMV);
|
||||
|
||||
/* register clocksource */
|
||||
clocksource_register_hz(&clk32k, AT91_SLOW_CLOCK);
|
||||
|
|
|
|||
|
|
@ -16,7 +16,11 @@
|
|||
#include <mach/at91_ramc.h>
|
||||
#include <mach/at91rm9200_sdramc.h>
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
extern void at91_pm_set_standby(void (*at91_standby)(void));
|
||||
#else
|
||||
static inline void at91_pm_set_standby(void (*at91_standby)(void)) { }
|
||||
#endif
|
||||
|
||||
/*
|
||||
* The AT91RM9200 goes into self-refresh mode with this command, and will
|
||||
|
|
|
|||
|
|
@ -95,19 +95,19 @@ static struct clk twi0_clk = {
|
|||
.name = "twi0_clk",
|
||||
.pid = SAMA5D3_ID_TWI0,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
.div = AT91_PMC_PCR_DIV2,
|
||||
.div = AT91_PMC_PCR_DIV8,
|
||||
};
|
||||
static struct clk twi1_clk = {
|
||||
.name = "twi1_clk",
|
||||
.pid = SAMA5D3_ID_TWI1,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
.div = AT91_PMC_PCR_DIV2,
|
||||
.div = AT91_PMC_PCR_DIV8,
|
||||
};
|
||||
static struct clk twi2_clk = {
|
||||
.name = "twi2_clk",
|
||||
.pid = SAMA5D3_ID_TWI2,
|
||||
.type = CLK_TYPE_PERIPHERAL,
|
||||
.div = AT91_PMC_PCR_DIV2,
|
||||
.div = AT91_PMC_PCR_DIV8,
|
||||
};
|
||||
static struct clk mmc0_clk = {
|
||||
.name = "mci0_clk",
|
||||
|
|
|
|||
|
|
@ -487,7 +487,7 @@ int __init da8xx_register_emac(void)
|
|||
|
||||
static struct resource da830_mcasp1_resources[] = {
|
||||
{
|
||||
.name = "mcasp1",
|
||||
.name = "mpu",
|
||||
.start = DAVINCI_DA830_MCASP1_REG_BASE,
|
||||
.end = DAVINCI_DA830_MCASP1_REG_BASE + (SZ_1K * 12) - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
|
|
@ -515,7 +515,7 @@ static struct platform_device da830_mcasp1_device = {
|
|||
|
||||
static struct resource da850_mcasp_resources[] = {
|
||||
{
|
||||
.name = "mcasp",
|
||||
.name = "mpu",
|
||||
.start = DAVINCI_DA8XX_MCASP0_REG_BASE,
|
||||
.end = DAVINCI_DA8XX_MCASP0_REG_BASE + (SZ_1K * 12) - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
|
|
|
|||
|
|
@ -641,6 +641,7 @@ static struct platform_device dm355_edma_device = {
|
|||
|
||||
static struct resource dm355_asp1_resources[] = {
|
||||
{
|
||||
.name = "mpu",
|
||||
.start = DAVINCI_ASP1_BASE,
|
||||
.end = DAVINCI_ASP1_BASE + SZ_8K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
|
|
@ -906,7 +907,7 @@ static struct davinci_gpio_platform_data dm355_gpio_platform_data = {
|
|||
int __init dm355_gpio_register(void)
|
||||
{
|
||||
return davinci_gpio_register(dm355_gpio_resources,
|
||||
sizeof(dm355_gpio_resources),
|
||||
ARRAY_SIZE(dm355_gpio_resources),
|
||||
&dm355_gpio_platform_data);
|
||||
}
|
||||
/*----------------------------------------------------------------------*/
|
||||
|
|
|
|||
|
|
@ -720,7 +720,7 @@ static struct davinci_gpio_platform_data dm365_gpio_platform_data = {
|
|||
int __init dm365_gpio_register(void)
|
||||
{
|
||||
return davinci_gpio_register(dm365_gpio_resources,
|
||||
sizeof(dm365_gpio_resources),
|
||||
ARRAY_SIZE(dm365_gpio_resources),
|
||||
&dm365_gpio_platform_data);
|
||||
}
|
||||
|
||||
|
|
@ -942,6 +942,7 @@ static struct platform_device dm365_edma_device = {
|
|||
|
||||
static struct resource dm365_asp_resources[] = {
|
||||
{
|
||||
.name = "mpu",
|
||||
.start = DAVINCI_DM365_ASP0_BASE,
|
||||
.end = DAVINCI_DM365_ASP0_BASE + SZ_8K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
|
|
|
|||
|
|
@ -572,6 +572,7 @@ static struct platform_device dm644x_edma_device = {
|
|||
/* DM6446 EVM uses ASP0; line-out is a pair of RCA jacks */
|
||||
static struct resource dm644x_asp_resources[] = {
|
||||
{
|
||||
.name = "mpu",
|
||||
.start = DAVINCI_ASP0_BASE,
|
||||
.end = DAVINCI_ASP0_BASE + SZ_8K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
|
|
@ -792,7 +793,7 @@ static struct davinci_gpio_platform_data dm644_gpio_platform_data = {
|
|||
int __init dm644x_gpio_register(void)
|
||||
{
|
||||
return davinci_gpio_register(dm644_gpio_resources,
|
||||
sizeof(dm644_gpio_resources),
|
||||
ARRAY_SIZE(dm644_gpio_resources),
|
||||
&dm644_gpio_platform_data);
|
||||
}
|
||||
/*----------------------------------------------------------------------*/
|
||||
|
|
|
|||
|
|
@ -621,7 +621,7 @@ static struct platform_device dm646x_edma_device = {
|
|||
|
||||
static struct resource dm646x_mcasp0_resources[] = {
|
||||
{
|
||||
.name = "mcasp0",
|
||||
.name = "mpu",
|
||||
.start = DAVINCI_DM646X_MCASP0_REG_BASE,
|
||||
.end = DAVINCI_DM646X_MCASP0_REG_BASE + (SZ_1K << 1) - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
|
|
@ -641,7 +641,7 @@ static struct resource dm646x_mcasp0_resources[] = {
|
|||
|
||||
static struct resource dm646x_mcasp1_resources[] = {
|
||||
{
|
||||
.name = "mcasp1",
|
||||
.name = "mpu",
|
||||
.start = DAVINCI_DM646X_MCASP1_REG_BASE,
|
||||
.end = DAVINCI_DM646X_MCASP1_REG_BASE + (SZ_1K << 1) - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
|
|
@ -769,7 +769,7 @@ static struct davinci_gpio_platform_data dm646x_gpio_platform_data = {
|
|||
int __init dm646x_gpio_register(void)
|
||||
{
|
||||
return davinci_gpio_register(dm646x_gpio_resources,
|
||||
sizeof(dm646x_gpio_resources),
|
||||
ARRAY_SIZE(dm646x_gpio_resources),
|
||||
&dm646x_gpio_platform_data);
|
||||
}
|
||||
/*----------------------------------------------------------------------*/
|
||||
|
|
|
|||
|
|
@ -96,11 +96,12 @@ static struct irqaction footbridge_timer_irq = {
|
|||
void __init footbridge_timer_init(void)
|
||||
{
|
||||
struct clock_event_device *ce = &ckevt_dc21285;
|
||||
unsigned rate = DIV_ROUND_CLOSEST(mem_fclk_21285, 16);
|
||||
|
||||
clocksource_register_hz(&cksrc_dc21285, (mem_fclk_21285 + 8) / 16);
|
||||
clocksource_register_hz(&cksrc_dc21285, rate);
|
||||
|
||||
setup_irq(ce->irq, &footbridge_timer_irq);
|
||||
|
||||
ce->cpumask = cpumask_of(smp_processor_id());
|
||||
clockevents_config_and_register(ce, mem_fclk_21285, 0x4, 0xffffff);
|
||||
clockevents_config_and_register(ce, rate, 0x4, 0xffffff);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -17,12 +17,15 @@
|
|||
#include <linux/clkdev.h>
|
||||
#include <linux/clocksource.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/input.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/irqchip.h>
|
||||
#include <linux/mailbox.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/reboot.h>
|
||||
#include <linux/amba/bus.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
|
|
@ -130,6 +133,24 @@ static struct platform_device highbank_cpuidle_device = {
|
|||
.name = "cpuidle-calxeda",
|
||||
};
|
||||
|
||||
static int hb_keys_notifier(struct notifier_block *nb, unsigned long event, void *data)
|
||||
{
|
||||
u32 key = *(u32 *)data;
|
||||
|
||||
if (event != 0x1000)
|
||||
return 0;
|
||||
|
||||
if (key == KEY_POWER)
|
||||
orderly_poweroff(false);
|
||||
else if (key == 0xffff)
|
||||
ctrl_alt_del();
|
||||
|
||||
return 0;
|
||||
}
|
||||
static struct notifier_block hb_keys_nb = {
|
||||
.notifier_call = hb_keys_notifier,
|
||||
};
|
||||
|
||||
static void __init highbank_init(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
|
|
@ -145,6 +166,8 @@ static void __init highbank_init(void)
|
|||
bus_register_notifier(&platform_bus_type, &highbank_platform_nb);
|
||||
bus_register_notifier(&amba_bustype, &highbank_amba_nb);
|
||||
|
||||
pl320_ipc_register_notifier(&hb_keys_nb);
|
||||
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
||||
|
||||
if (psci_ops.cpu_suspend)
|
||||
|
|
|
|||
|
|
@ -131,6 +131,24 @@ DT_MACHINE_START(OMAP3_GP_DT, "Generic OMAP3-GP (Flattened Device Tree)")
|
|||
.dt_compat = omap3_gp_boards_compat,
|
||||
.restart = omap3xxx_restart,
|
||||
MACHINE_END
|
||||
|
||||
static const char *am3517_boards_compat[] __initdata = {
|
||||
"ti,am3517",
|
||||
NULL,
|
||||
};
|
||||
|
||||
DT_MACHINE_START(AM3517_DT, "Generic AM3517 (Flattened Device Tree)")
|
||||
.reserve = omap_reserve,
|
||||
.map_io = omap3_map_io,
|
||||
.init_early = am35xx_init_early,
|
||||
.init_irq = omap_intc_of_init,
|
||||
.handle_irq = omap3_intc_handle_irq,
|
||||
.init_machine = omap_generic_init,
|
||||
.init_late = omap3_init_late,
|
||||
.init_time = omap3_gptimer_timer_init,
|
||||
.dt_compat = am3517_boards_compat,
|
||||
.restart = omap3xxx_restart,
|
||||
MACHINE_END
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_AM33XX
|
||||
|
|
|
|||
|
|
@ -242,12 +242,18 @@ static void __init ldp_display_init(void)
|
|||
|
||||
static int ldp_twl_gpio_setup(struct device *dev, unsigned gpio, unsigned ngpio)
|
||||
{
|
||||
int res;
|
||||
|
||||
/* LCD enable GPIO */
|
||||
ldp_lcd_pdata.enable_gpio = gpio + 7;
|
||||
|
||||
/* Backlight enable GPIO */
|
||||
ldp_lcd_pdata.backlight_gpio = gpio + 15;
|
||||
|
||||
res = platform_device_register(&ldp_lcd_device);
|
||||
if (res)
|
||||
pr_err("Unable to register LCD: %d\n", res);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -346,7 +352,6 @@ static struct omap2_hsmmc_info mmc[] __initdata = {
|
|||
|
||||
static struct platform_device *ldp_devices[] __initdata = {
|
||||
&ldp_gpio_keys_device,
|
||||
&ldp_lcd_device,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_OMAP_MUX
|
||||
|
|
|
|||
|
|
@ -101,13 +101,51 @@ static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initconst = {
|
|||
{ "dss_hdmi", "omapdss_hdmi", -1 },
|
||||
};
|
||||
|
||||
static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
|
||||
{
|
||||
u32 enable_mask, enable_shift;
|
||||
u32 pipd_mask, pipd_shift;
|
||||
u32 reg;
|
||||
|
||||
if (dsi_id == 0) {
|
||||
enable_mask = OMAP4_DSI1_LANEENABLE_MASK;
|
||||
enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT;
|
||||
pipd_mask = OMAP4_DSI1_PIPD_MASK;
|
||||
pipd_shift = OMAP4_DSI1_PIPD_SHIFT;
|
||||
} else if (dsi_id == 1) {
|
||||
enable_mask = OMAP4_DSI2_LANEENABLE_MASK;
|
||||
enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT;
|
||||
pipd_mask = OMAP4_DSI2_PIPD_MASK;
|
||||
pipd_shift = OMAP4_DSI2_PIPD_SHIFT;
|
||||
} else {
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
reg = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
|
||||
|
||||
reg &= ~enable_mask;
|
||||
reg &= ~pipd_mask;
|
||||
|
||||
reg |= (lanes << enable_shift) & enable_mask;
|
||||
reg |= (lanes << pipd_shift) & pipd_mask;
|
||||
|
||||
omap4_ctrl_pad_writel(reg, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask)
|
||||
{
|
||||
if (cpu_is_omap44xx())
|
||||
return omap4_dsi_mux_pads(dsi_id, lane_mask);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask)
|
||||
{
|
||||
if (cpu_is_omap44xx())
|
||||
omap4_dsi_mux_pads(dsi_id, 0);
|
||||
}
|
||||
|
||||
static int omap_dss_set_min_bus_tput(struct device *dev, unsigned long tput)
|
||||
|
|
|
|||
|
|
@ -223,7 +223,7 @@ void __init omap_4430sdp_display_init_of(void)
|
|||
static struct connector_dvi_platform_data omap3_igep2_dvi_connector_pdata = {
|
||||
.name = "dvi",
|
||||
.source = "tfp410.0",
|
||||
.i2c_bus_num = 3,
|
||||
.i2c_bus_num = 2,
|
||||
};
|
||||
|
||||
static struct platform_device omap3_igep2_dvi_connector_device = {
|
||||
|
|
|
|||
|
|
@ -183,6 +183,10 @@ static int omap_device_build_from_dt(struct platform_device *pdev)
|
|||
odbfd_exit1:
|
||||
kfree(hwmods);
|
||||
odbfd_exit:
|
||||
/* if data/we are at fault.. load up a fail handler */
|
||||
if (ret)
|
||||
pdev->dev.pm_domain = &omap_device_fail_pm_domain;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
@ -604,6 +608,19 @@ static int _od_runtime_resume(struct device *dev)
|
|||
|
||||
return pm_generic_runtime_resume(dev);
|
||||
}
|
||||
|
||||
static int _od_fail_runtime_suspend(struct device *dev)
|
||||
{
|
||||
dev_warn(dev, "%s: FIXME: missing hwmod/omap_dev info\n", __func__);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
static int _od_fail_runtime_resume(struct device *dev)
|
||||
{
|
||||
dev_warn(dev, "%s: FIXME: missing hwmod/omap_dev info\n", __func__);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SUSPEND
|
||||
|
|
@ -657,6 +674,13 @@ static int _od_resume_noirq(struct device *dev)
|
|||
#define _od_resume_noirq NULL
|
||||
#endif
|
||||
|
||||
struct dev_pm_domain omap_device_fail_pm_domain = {
|
||||
.ops = {
|
||||
SET_RUNTIME_PM_OPS(_od_fail_runtime_suspend,
|
||||
_od_fail_runtime_resume, NULL)
|
||||
}
|
||||
};
|
||||
|
||||
struct dev_pm_domain omap_device_pm_domain = {
|
||||
.ops = {
|
||||
SET_RUNTIME_PM_OPS(_od_runtime_suspend, _od_runtime_resume,
|
||||
|
|
|
|||
|
|
@ -29,6 +29,7 @@
|
|||
#include "omap_hwmod.h"
|
||||
|
||||
extern struct dev_pm_domain omap_device_pm_domain;
|
||||
extern struct dev_pm_domain omap_device_fail_pm_domain;
|
||||
|
||||
/* omap_device._state values */
|
||||
#define OMAP_DEVICE_STATE_UNKNOWN 0
|
||||
|
|
|
|||
|
|
@ -399,7 +399,7 @@ static int _set_clockactivity(struct omap_hwmod *oh, u8 clockact, u32 *v)
|
|||
}
|
||||
|
||||
/**
|
||||
* _set_softreset: set OCP_SYSCONFIG.CLOCKACTIVITY bits in @v
|
||||
* _set_softreset: set OCP_SYSCONFIG.SOFTRESET bit in @v
|
||||
* @oh: struct omap_hwmod *
|
||||
* @v: pointer to register contents to modify
|
||||
*
|
||||
|
|
@ -426,6 +426,36 @@ static int _set_softreset(struct omap_hwmod *oh, u32 *v)
|
|||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* _clear_softreset: clear OCP_SYSCONFIG.SOFTRESET bit in @v
|
||||
* @oh: struct omap_hwmod *
|
||||
* @v: pointer to register contents to modify
|
||||
*
|
||||
* Clear the SOFTRESET bit in @v for hwmod @oh. Returns -EINVAL upon
|
||||
* error or 0 upon success.
|
||||
*/
|
||||
static int _clear_softreset(struct omap_hwmod *oh, u32 *v)
|
||||
{
|
||||
u32 softrst_mask;
|
||||
|
||||
if (!oh->class->sysc ||
|
||||
!(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET))
|
||||
return -EINVAL;
|
||||
|
||||
if (!oh->class->sysc->sysc_fields) {
|
||||
WARN(1,
|
||||
"omap_hwmod: %s: sysc_fields absent for sysconfig class\n",
|
||||
oh->name);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
softrst_mask = (0x1 << oh->class->sysc->sysc_fields->srst_shift);
|
||||
|
||||
*v &= ~softrst_mask;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* _wait_softreset_complete - wait for an OCP softreset to complete
|
||||
* @oh: struct omap_hwmod * to wait on
|
||||
|
|
@ -785,6 +815,7 @@ static int _init_interface_clks(struct omap_hwmod *oh)
|
|||
pr_warning("omap_hwmod: %s: cannot clk_get interface_clk %s\n",
|
||||
oh->name, os->clk);
|
||||
ret = -EINVAL;
|
||||
continue;
|
||||
}
|
||||
os->_clk = c;
|
||||
/*
|
||||
|
|
@ -821,6 +852,7 @@ static int _init_opt_clks(struct omap_hwmod *oh)
|
|||
pr_warning("omap_hwmod: %s: cannot clk_get opt_clk %s\n",
|
||||
oh->name, oc->clk);
|
||||
ret = -EINVAL;
|
||||
continue;
|
||||
}
|
||||
oc->_clk = c;
|
||||
/*
|
||||
|
|
@ -1911,6 +1943,12 @@ static int _ocp_softreset(struct omap_hwmod *oh)
|
|||
ret = _set_softreset(oh, &v);
|
||||
if (ret)
|
||||
goto dis_opt_clks;
|
||||
|
||||
_write_sysconfig(v, oh);
|
||||
ret = _clear_softreset(oh, &v);
|
||||
if (ret)
|
||||
goto dis_opt_clks;
|
||||
|
||||
_write_sysconfig(v, oh);
|
||||
|
||||
if (oh->class->sysc->srst_udelay)
|
||||
|
|
@ -2326,38 +2364,80 @@ static int _shutdown(struct omap_hwmod *oh)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int of_dev_find_hwmod(struct device_node *np,
|
||||
struct omap_hwmod *oh)
|
||||
{
|
||||
int count, i, res;
|
||||
const char *p;
|
||||
|
||||
count = of_property_count_strings(np, "ti,hwmods");
|
||||
if (count < 1)
|
||||
return -ENODEV;
|
||||
|
||||
for (i = 0; i < count; i++) {
|
||||
res = of_property_read_string_index(np, "ti,hwmods",
|
||||
i, &p);
|
||||
if (res)
|
||||
continue;
|
||||
if (!strcmp(p, oh->name)) {
|
||||
pr_debug("omap_hwmod: dt %s[%i] uses hwmod %s\n",
|
||||
np->name, i, oh->name);
|
||||
return i;
|
||||
}
|
||||
}
|
||||
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/**
|
||||
* of_dev_hwmod_lookup - look up needed hwmod from dt blob
|
||||
* @np: struct device_node *
|
||||
* @oh: struct omap_hwmod *
|
||||
* @index: index of the entry found
|
||||
* @found: struct device_node * found or NULL
|
||||
*
|
||||
* Parse the dt blob and find out needed hwmod. Recursive function is
|
||||
* implemented to take care hierarchical dt blob parsing.
|
||||
* Return: The device node on success or NULL on failure.
|
||||
* Return: Returns 0 on success, -ENODEV when not found.
|
||||
*/
|
||||
static struct device_node *of_dev_hwmod_lookup(struct device_node *np,
|
||||
struct omap_hwmod *oh)
|
||||
static int of_dev_hwmod_lookup(struct device_node *np,
|
||||
struct omap_hwmod *oh,
|
||||
int *index,
|
||||
struct device_node **found)
|
||||
{
|
||||
struct device_node *np0 = NULL, *np1 = NULL;
|
||||
const char *p;
|
||||
struct device_node *np0 = NULL;
|
||||
int res;
|
||||
|
||||
res = of_dev_find_hwmod(np, oh);
|
||||
if (res >= 0) {
|
||||
*found = np;
|
||||
*index = res;
|
||||
return 0;
|
||||
}
|
||||
|
||||
for_each_child_of_node(np, np0) {
|
||||
if (of_find_property(np0, "ti,hwmods", NULL)) {
|
||||
p = of_get_property(np0, "ti,hwmods", NULL);
|
||||
if (!strcmp(p, oh->name))
|
||||
return np0;
|
||||
np1 = of_dev_hwmod_lookup(np0, oh);
|
||||
if (np1)
|
||||
return np1;
|
||||
struct device_node *fc;
|
||||
int i;
|
||||
|
||||
res = of_dev_hwmod_lookup(np0, oh, &i, &fc);
|
||||
if (res == 0) {
|
||||
*found = fc;
|
||||
*index = i;
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
return NULL;
|
||||
|
||||
*found = NULL;
|
||||
*index = 0;
|
||||
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/**
|
||||
* _init_mpu_rt_base - populate the virtual address for a hwmod
|
||||
* @oh: struct omap_hwmod * to locate the virtual address
|
||||
* @data: (unused, caller should pass NULL)
|
||||
* @index: index of the reg entry iospace in device tree
|
||||
* @np: struct device_node * of the IP block's device node in the DT data
|
||||
*
|
||||
* Cache the virtual address used by the MPU to access this IP block's
|
||||
|
|
@ -2368,7 +2448,7 @@ static struct device_node *of_dev_hwmod_lookup(struct device_node *np,
|
|||
* -ENXIO on absent or invalid register target address space.
|
||||
*/
|
||||
static int __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data,
|
||||
struct device_node *np)
|
||||
int index, struct device_node *np)
|
||||
{
|
||||
struct omap_hwmod_addr_space *mem;
|
||||
void __iomem *va_start = NULL;
|
||||
|
|
@ -2390,13 +2470,17 @@ static int __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data,
|
|||
if (!np)
|
||||
return -ENXIO;
|
||||
|
||||
va_start = of_iomap(np, oh->mpu_rt_idx);
|
||||
va_start = of_iomap(np, index + oh->mpu_rt_idx);
|
||||
} else {
|
||||
va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start);
|
||||
}
|
||||
|
||||
if (!va_start) {
|
||||
if (mem)
|
||||
pr_err("omap_hwmod: %s: Could not ioremap\n", oh->name);
|
||||
else
|
||||
pr_err("omap_hwmod: %s: Missing dt reg%i for %s\n",
|
||||
oh->name, index, np->full_name);
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
|
|
@ -2422,17 +2506,29 @@ static int __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data,
|
|||
*/
|
||||
static int __init _init(struct omap_hwmod *oh, void *data)
|
||||
{
|
||||
int r;
|
||||
int r, index;
|
||||
struct device_node *np = NULL;
|
||||
|
||||
if (oh->_state != _HWMOD_STATE_REGISTERED)
|
||||
return 0;
|
||||
|
||||
if (of_have_populated_dt())
|
||||
np = of_dev_hwmod_lookup(of_find_node_by_name(NULL, "ocp"), oh);
|
||||
if (of_have_populated_dt()) {
|
||||
struct device_node *bus;
|
||||
|
||||
bus = of_find_node_by_name(NULL, "ocp");
|
||||
if (!bus)
|
||||
return -ENODEV;
|
||||
|
||||
r = of_dev_hwmod_lookup(bus, oh, &index, &np);
|
||||
if (r)
|
||||
pr_debug("omap_hwmod: %s missing dt data\n", oh->name);
|
||||
else if (np && index)
|
||||
pr_warn("omap_hwmod: %s using broken dt data from %s\n",
|
||||
oh->name, np->name);
|
||||
}
|
||||
|
||||
if (oh->class->sysc) {
|
||||
r = _init_mpu_rt_base(oh, NULL, np);
|
||||
r = _init_mpu_rt_base(oh, NULL, index, np);
|
||||
if (r < 0) {
|
||||
WARN(1, "omap_hwmod: %s: doesn't have mpu register target base\n",
|
||||
oh->name);
|
||||
|
|
@ -3169,6 +3265,11 @@ int omap_hwmod_softreset(struct omap_hwmod *oh)
|
|||
goto error;
|
||||
_write_sysconfig(v, oh);
|
||||
|
||||
ret = _clear_softreset(oh, &v);
|
||||
if (ret)
|
||||
goto error;
|
||||
_write_sysconfig(v, oh);
|
||||
|
||||
error:
|
||||
return ret;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -796,7 +796,7 @@ struct omap_hwmod omap2xxx_counter_32k_hwmod = {
|
|||
|
||||
/* gpmc */
|
||||
static struct omap_hwmod_irq_info omap2xxx_gpmc_irqs[] = {
|
||||
{ .irq = 20 },
|
||||
{ .irq = 20 + OMAP_INTC_START, },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
|
|
@ -841,7 +841,7 @@ static struct omap_hwmod_class omap2_rng_hwmod_class = {
|
|||
};
|
||||
|
||||
static struct omap_hwmod_irq_info omap2_rng_mpu_irqs[] = {
|
||||
{ .irq = 52 },
|
||||
{ .irq = 52 + OMAP_INTC_START, },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -1943,7 +1943,8 @@ static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = {
|
|||
.syss_offs = 0x0014,
|
||||
.sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
|
||||
SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
|
||||
SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
|
||||
SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
|
||||
SYSS_HAS_RESET_STATUS),
|
||||
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
||||
MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
|
||||
.sysc_fields = &omap_hwmod_sysc_type1,
|
||||
|
|
@ -2021,15 +2022,7 @@ static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
|
|||
* hence HWMOD_SWSUP_MSTANDBY
|
||||
*/
|
||||
|
||||
/*
|
||||
* During system boot; If the hwmod framework resets the module
|
||||
* the module will have smart idle settings; which can lead to deadlock
|
||||
* (above Errata Id:i660); so, dont reset the module during boot;
|
||||
* Use HWMOD_INIT_NO_RESET.
|
||||
*/
|
||||
|
||||
.flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
|
||||
HWMOD_INIT_NO_RESET,
|
||||
.flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
|
||||
};
|
||||
|
||||
/*
|
||||
|
|
@ -2172,7 +2165,7 @@ static struct omap_hwmod_class omap3xxx_gpmc_hwmod_class = {
|
|||
};
|
||||
|
||||
static struct omap_hwmod_irq_info omap3xxx_gpmc_irqs[] = {
|
||||
{ .irq = 20 },
|
||||
{ .irq = 20 + OMAP_INTC_START, },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
|
|
@ -3006,7 +2999,7 @@ static struct omap_mmu_dev_attr mmu_isp_dev_attr = {
|
|||
|
||||
static struct omap_hwmod omap3xxx_mmu_isp_hwmod;
|
||||
static struct omap_hwmod_irq_info omap3xxx_mmu_isp_irqs[] = {
|
||||
{ .irq = 24 },
|
||||
{ .irq = 24 + OMAP_INTC_START, },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
|
|
@ -3048,7 +3041,7 @@ static struct omap_mmu_dev_attr mmu_iva_dev_attr = {
|
|||
|
||||
static struct omap_hwmod omap3xxx_mmu_iva_hwmod;
|
||||
static struct omap_hwmod_irq_info omap3xxx_mmu_iva_irqs[] = {
|
||||
{ .irq = 28 },
|
||||
{ .irq = 28 + OMAP_INTC_START, },
|
||||
{ .irq = -1 }
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -2937,7 +2937,7 @@ static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
|
|||
.sysc_offs = 0x0010,
|
||||
.syss_offs = 0x0014,
|
||||
.sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
|
||||
SYSC_HAS_SOFTRESET),
|
||||
SYSC_HAS_SOFTRESET | SYSC_HAS_RESET_STATUS),
|
||||
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
||||
SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
|
||||
MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
|
||||
|
|
@ -3001,15 +3001,7 @@ static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
|
|||
* hence HWMOD_SWSUP_MSTANDBY
|
||||
*/
|
||||
|
||||
/*
|
||||
* During system boot; If the hwmod framework resets the module
|
||||
* the module will have smart idle settings; which can lead to deadlock
|
||||
* (above Errata Id:i660); so, dont reset the module during boot;
|
||||
* Use HWMOD_INIT_NO_RESET.
|
||||
*/
|
||||
|
||||
.flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
|
||||
HWMOD_INIT_NO_RESET,
|
||||
.flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
|
||||
};
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -1544,7 +1544,8 @@ static struct omap_hwmod_class_sysconfig omap54xx_usb_host_hs_sysc = {
|
|||
.rev_offs = 0x0000,
|
||||
.sysc_offs = 0x0010,
|
||||
.sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
|
||||
SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
|
||||
SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
|
||||
SYSC_HAS_RESET_STATUS),
|
||||
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
||||
SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
|
||||
MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
|
||||
|
|
@ -1598,15 +1599,7 @@ static struct omap_hwmod omap54xx_usb_host_hs_hwmod = {
|
|||
* hence HWMOD_SWSUP_MSTANDBY
|
||||
*/
|
||||
|
||||
/*
|
||||
* During system boot; If the hwmod framework resets the module
|
||||
* the module will have smart idle settings; which can lead to deadlock
|
||||
* (above Errata Id:i660); so, dont reset the module during boot;
|
||||
* Use HWMOD_INIT_NO_RESET.
|
||||
*/
|
||||
|
||||
.flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
|
||||
HWMOD_INIT_NO_RESET,
|
||||
.flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
|
||||
.main_clk = "l3init_60m_fclk",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
|
|
|
|||
|
|
@ -1637,7 +1637,7 @@ static struct omap_hwmod dra7xx_uart1_hwmod = {
|
|||
.class = &dra7xx_uart_hwmod_class,
|
||||
.clkdm_name = "l4per_clkdm",
|
||||
.main_clk = "uart1_gfclk_mux",
|
||||
.flags = HWMOD_SWSUP_SIDLE_ACT,
|
||||
.flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP2UART1_FLAGS,
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
|
||||
|
|
|
|||
|
|
@ -139,6 +139,7 @@ struct of_dev_auxdata omap_auxdata_lookup[] __initdata = {
|
|||
|
||||
static struct pdata_init pdata_quirks[] __initdata = {
|
||||
#ifdef CONFIG_ARCH_OMAP3
|
||||
{ "nokia,omap3-n900", hsmmc2_internal_input_clk, },
|
||||
{ "nokia,omap3-n9", hsmmc2_internal_input_clk, },
|
||||
{ "nokia,omap3-n950", hsmmc2_internal_input_clk, },
|
||||
{ "isee,omap3-igep0020", omap3_igep0020_legacy_init, },
|
||||
|
|
|
|||
|
|
@ -128,6 +128,7 @@ skip_voltdm:
|
|||
for (i = 0; i < pwrdm->banks; i++)
|
||||
pwrdm->ret_mem_off_counter[i] = 0;
|
||||
|
||||
if (arch_pwrdm && arch_pwrdm->pwrdm_wait_transition)
|
||||
arch_pwrdm->pwrdm_wait_transition(pwrdm);
|
||||
pwrdm->state = pwrdm_read_pwrst(pwrdm);
|
||||
pwrdm->state_counter[pwrdm->state] = 1;
|
||||
|
|
|
|||
|
|
@ -10,6 +10,8 @@
|
|||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <mach/irqs.h>
|
||||
|
||||
#define LUBBOCK_ETH_PHYS PXA_CS3_PHYS
|
||||
|
||||
#define LUBBOCK_FPGA_PHYS PXA_CS2_PHYS
|
||||
|
|
|
|||
|
|
@ -13,6 +13,7 @@
|
|||
|
||||
#include <mach/regs-ost.h>
|
||||
#include <mach/reset.h>
|
||||
#include <mach/smemc.h>
|
||||
|
||||
unsigned int reset_status;
|
||||
EXPORT_SYMBOL(reset_status);
|
||||
|
|
@ -81,6 +82,12 @@ static void do_hw_reset(void)
|
|||
writel_relaxed(OSSR_M3, OSSR);
|
||||
/* ... in 100 ms */
|
||||
writel_relaxed(readl_relaxed(OSCR) + 368640, OSMR3);
|
||||
/*
|
||||
* SDRAM hangs on watchdog reset on Marvell PXA270 (erratum 71)
|
||||
* we put SDRAM into self-refresh to prevent that
|
||||
*/
|
||||
while (1)
|
||||
writel_relaxed(MDREFR_SLFRSH, MDREFR);
|
||||
}
|
||||
|
||||
void pxa_restart(enum reboot_mode mode, const char *cmd)
|
||||
|
|
@ -104,4 +111,3 @@ void pxa_restart(enum reboot_mode mode, const char *cmd)
|
|||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -425,57 +425,57 @@ static struct platform_device tosa_power_device = {
|
|||
* Tosa Keyboard
|
||||
*/
|
||||
static const uint32_t tosakbd_keymap[] = {
|
||||
KEY(0, 2, KEY_W),
|
||||
KEY(0, 6, KEY_K),
|
||||
KEY(0, 7, KEY_BACKSPACE),
|
||||
KEY(0, 8, KEY_P),
|
||||
KEY(1, 1, KEY_Q),
|
||||
KEY(1, 2, KEY_E),
|
||||
KEY(1, 3, KEY_T),
|
||||
KEY(1, 4, KEY_Y),
|
||||
KEY(1, 6, KEY_O),
|
||||
KEY(1, 7, KEY_I),
|
||||
KEY(1, 8, KEY_COMMA),
|
||||
KEY(2, 1, KEY_A),
|
||||
KEY(2, 2, KEY_D),
|
||||
KEY(2, 3, KEY_G),
|
||||
KEY(2, 4, KEY_U),
|
||||
KEY(2, 6, KEY_L),
|
||||
KEY(2, 7, KEY_ENTER),
|
||||
KEY(2, 8, KEY_DOT),
|
||||
KEY(3, 1, KEY_Z),
|
||||
KEY(3, 2, KEY_C),
|
||||
KEY(3, 3, KEY_V),
|
||||
KEY(3, 4, KEY_J),
|
||||
KEY(3, 5, TOSA_KEY_ADDRESSBOOK),
|
||||
KEY(3, 6, TOSA_KEY_CANCEL),
|
||||
KEY(3, 7, TOSA_KEY_CENTER),
|
||||
KEY(3, 8, TOSA_KEY_OK),
|
||||
KEY(3, 9, KEY_LEFTSHIFT),
|
||||
KEY(4, 1, KEY_S),
|
||||
KEY(4, 2, KEY_R),
|
||||
KEY(4, 3, KEY_B),
|
||||
KEY(4, 4, KEY_N),
|
||||
KEY(4, 5, TOSA_KEY_CALENDAR),
|
||||
KEY(4, 6, TOSA_KEY_HOMEPAGE),
|
||||
KEY(4, 7, KEY_LEFTCTRL),
|
||||
KEY(4, 8, TOSA_KEY_LIGHT),
|
||||
KEY(4, 10, KEY_RIGHTSHIFT),
|
||||
KEY(5, 1, KEY_TAB),
|
||||
KEY(5, 2, KEY_SLASH),
|
||||
KEY(5, 3, KEY_H),
|
||||
KEY(5, 4, KEY_M),
|
||||
KEY(5, 5, TOSA_KEY_MENU),
|
||||
KEY(5, 7, KEY_UP),
|
||||
KEY(5, 11, TOSA_KEY_FN),
|
||||
KEY(6, 1, KEY_X),
|
||||
KEY(6, 2, KEY_F),
|
||||
KEY(6, 3, KEY_SPACE),
|
||||
KEY(6, 4, KEY_APOSTROPHE),
|
||||
KEY(6, 5, TOSA_KEY_MAIL),
|
||||
KEY(6, 6, KEY_LEFT),
|
||||
KEY(6, 7, KEY_DOWN),
|
||||
KEY(6, 8, KEY_RIGHT),
|
||||
KEY(0, 1, KEY_W),
|
||||
KEY(0, 5, KEY_K),
|
||||
KEY(0, 6, KEY_BACKSPACE),
|
||||
KEY(0, 7, KEY_P),
|
||||
KEY(1, 0, KEY_Q),
|
||||
KEY(1, 1, KEY_E),
|
||||
KEY(1, 2, KEY_T),
|
||||
KEY(1, 3, KEY_Y),
|
||||
KEY(1, 5, KEY_O),
|
||||
KEY(1, 6, KEY_I),
|
||||
KEY(1, 7, KEY_COMMA),
|
||||
KEY(2, 0, KEY_A),
|
||||
KEY(2, 1, KEY_D),
|
||||
KEY(2, 2, KEY_G),
|
||||
KEY(2, 3, KEY_U),
|
||||
KEY(2, 5, KEY_L),
|
||||
KEY(2, 6, KEY_ENTER),
|
||||
KEY(2, 7, KEY_DOT),
|
||||
KEY(3, 0, KEY_Z),
|
||||
KEY(3, 1, KEY_C),
|
||||
KEY(3, 2, KEY_V),
|
||||
KEY(3, 3, KEY_J),
|
||||
KEY(3, 4, TOSA_KEY_ADDRESSBOOK),
|
||||
KEY(3, 5, TOSA_KEY_CANCEL),
|
||||
KEY(3, 6, TOSA_KEY_CENTER),
|
||||
KEY(3, 7, TOSA_KEY_OK),
|
||||
KEY(3, 8, KEY_LEFTSHIFT),
|
||||
KEY(4, 0, KEY_S),
|
||||
KEY(4, 1, KEY_R),
|
||||
KEY(4, 2, KEY_B),
|
||||
KEY(4, 3, KEY_N),
|
||||
KEY(4, 4, TOSA_KEY_CALENDAR),
|
||||
KEY(4, 5, TOSA_KEY_HOMEPAGE),
|
||||
KEY(4, 6, KEY_LEFTCTRL),
|
||||
KEY(4, 7, TOSA_KEY_LIGHT),
|
||||
KEY(4, 9, KEY_RIGHTSHIFT),
|
||||
KEY(5, 0, KEY_TAB),
|
||||
KEY(5, 1, KEY_SLASH),
|
||||
KEY(5, 2, KEY_H),
|
||||
KEY(5, 3, KEY_M),
|
||||
KEY(5, 4, TOSA_KEY_MENU),
|
||||
KEY(5, 6, KEY_UP),
|
||||
KEY(5, 10, TOSA_KEY_FN),
|
||||
KEY(6, 0, KEY_X),
|
||||
KEY(6, 1, KEY_F),
|
||||
KEY(6, 2, KEY_SPACE),
|
||||
KEY(6, 3, KEY_APOSTROPHE),
|
||||
KEY(6, 4, TOSA_KEY_MAIL),
|
||||
KEY(6, 5, KEY_LEFT),
|
||||
KEY(6, 6, KEY_DOWN),
|
||||
KEY(6, 7, KEY_RIGHT),
|
||||
};
|
||||
|
||||
static struct matrix_keymap_data tosakbd_keymap_data = {
|
||||
|
|
|
|||
|
|
@ -8,8 +8,6 @@
|
|||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/irqchip.h>
|
||||
#include <linux/of_platform.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
|
|
@ -48,15 +46,9 @@ static void __init s3c64xx_dt_map_io(void)
|
|||
panic("SoC is not S3C64xx!");
|
||||
}
|
||||
|
||||
static void __init s3c64xx_dt_init_irq(void)
|
||||
{
|
||||
of_clk_init(NULL);
|
||||
samsung_wdt_reset_of_init();
|
||||
irqchip_init();
|
||||
};
|
||||
|
||||
static void __init s3c64xx_dt_init_machine(void)
|
||||
{
|
||||
samsung_wdt_reset_of_init();
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
||||
}
|
||||
|
||||
|
|
@ -79,7 +71,6 @@ DT_MACHINE_START(S3C6400_DT, "Samsung S3C64xx (Flattened Device Tree)")
|
|||
/* Maintainer: Tomasz Figa <tomasz.figa@gmail.com> */
|
||||
.dt_compat = s3c64xx_dt_compat,
|
||||
.map_io = s3c64xx_dt_map_io,
|
||||
.init_irq = s3c64xx_dt_init_irq,
|
||||
.init_machine = s3c64xx_dt_init_machine,
|
||||
.restart = s3c64xx_dt_restart,
|
||||
MACHINE_END
|
||||
|
|
|
|||
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