i40e/i40evf: always set the CLEARPBA flag when re-enabling interrupts
In the past we changed driver behavior to not clear the PBA when
re-enabling interrupts. This change was motivated by the flawed belief
that clearing the PBA would cause a lost interrupt if a receive
interrupt occurred while interrupts were disabled.
According to empirical testing this isn't the case. Additionally, the
data sheet specifically says that we should set the CLEARPBA bit when
re-enabling interrupts in a polling setup.
This reverts commit 40d72a5098
("i40e/i40evf: don't lose interrupts")
Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Tested-by: Andrew Bowers <andrewx.bowers@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
This commit is contained in:
Родитель
4270255929
Коммит
dbadbbe235
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@ -949,9 +949,6 @@ static inline void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
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struct i40e_hw *hw = &pf->hw;
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u32 val;
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/* definitely clear the PBA here, as this function is meant to
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* clean out all previous interrupts AND enable the interrupt
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*/
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val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
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I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
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(I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
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@ -960,7 +957,7 @@ static inline void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
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}
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void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf);
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void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf, bool clearpba);
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void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf);
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int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd);
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int i40e_open(struct net_device *netdev);
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int i40e_close(struct net_device *netdev);
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@ -3403,15 +3403,14 @@ void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf)
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/**
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* i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0
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* @pf: board private structure
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* @clearpba: true when all pending interrupt events should be cleared
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**/
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void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf, bool clearpba)
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void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf)
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{
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struct i40e_hw *hw = &pf->hw;
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u32 val;
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val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
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(clearpba ? I40E_PFINT_DYN_CTL0_CLEARPBA_MASK : 0) |
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I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
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(I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);
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wr32(hw, I40E_PFINT_DYN_CTL0, val);
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@ -3597,7 +3596,7 @@ static int i40e_vsi_enable_irq(struct i40e_vsi *vsi)
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for (i = 0; i < vsi->num_q_vectors; i++)
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i40e_irq_dynamic_enable(vsi, i);
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} else {
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i40e_irq_dynamic_enable_icr0(pf, true);
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i40e_irq_dynamic_enable_icr0(pf);
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}
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i40e_flush(&pf->hw);
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@ -3746,7 +3745,7 @@ enable_intr:
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wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);
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if (!test_bit(__I40E_DOWN, pf->state)) {
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i40e_service_event_schedule(pf);
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i40e_irq_dynamic_enable_icr0(pf, false);
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i40e_irq_dynamic_enable_icr0(pf);
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}
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return ret;
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@ -8455,7 +8454,7 @@ static int i40e_setup_misc_vector(struct i40e_pf *pf)
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i40e_flush(hw);
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i40e_irq_dynamic_enable_icr0(pf, true);
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i40e_irq_dynamic_enable_icr0(pf);
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return err;
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}
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@ -2202,9 +2202,7 @@ static u32 i40e_buildreg_itr(const int type, const u16 itr)
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u32 val;
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val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
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/* Don't clear PBA because that can cause lost interrupts that
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* came in while we were cleaning/polling
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*/
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I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
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(type << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
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(itr << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT);
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@ -2241,7 +2239,7 @@ static inline void i40e_update_enable_itr(struct i40e_vsi *vsi,
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/* If we don't have MSIX, then we only need to re-enable icr0 */
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if (!(vsi->back->flags & I40E_FLAG_MSIX_ENABLED)) {
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i40e_irq_dynamic_enable_icr0(vsi->back, false);
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i40e_irq_dynamic_enable_icr0(vsi->back);
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return;
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}
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@ -1358,7 +1358,7 @@ err_alloc:
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i40e_free_vfs(pf);
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err_iov:
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/* Re-enable interrupt 0. */
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i40e_irq_dynamic_enable_icr0(pf, false);
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i40e_irq_dynamic_enable_icr0(pf);
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return ret;
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}
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@ -1409,9 +1409,7 @@ static u32 i40e_buildreg_itr(const int type, const u16 itr)
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u32 val;
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val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
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/* Don't clear PBA because that can cause lost interrupts that
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* came in while we were cleaning/polling
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*/
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I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
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(type << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
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(itr << I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT);
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