i3c: master: cdns: add data hold delay support
This patch adds support for THD_DEL (Data Hold Delay) to Cadence I3C master constoller driver. As per MIPI I3C Specification 1.0, Table 75 (page 142) defines non-zero minimal tHD_PP timing on master output (Fig 65). This setting allows to meet this timing on master's soc outputs, regardless of PCB balancing. Signed-off-by: Przemyslaw Gaj <pgaj@cadence.com> Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
This commit is contained in:
Родитель
e42617b825
Коммит
dbd6654329
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@ -22,6 +22,7 @@
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/workqueue.h>
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#include <linux/of_device.h>
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#define DEV_ID 0x0
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#define DEV_ID_I3C_MASTER 0x5034
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@ -60,6 +61,7 @@
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#define CTRL_HALT_EN BIT(30)
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#define CTRL_MCS BIT(29)
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#define CTRL_MCS_EN BIT(28)
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#define CTRL_THD_DELAY(x) (((x) << 24) & GENMASK(25, 24))
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#define CTRL_HJ_DISEC BIT(8)
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#define CTRL_MST_ACK BIT(7)
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#define CTRL_HJ_ACK BIT(6)
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@ -70,6 +72,7 @@
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#define CTRL_MIXED_FAST_BUS_MODE 2
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#define CTRL_MIXED_SLOW_BUS_MODE 3
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#define CTRL_BUS_MODE_MASK GENMASK(1, 0)
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#define THD_DELAY_MAX 3
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#define PRESCL_CTRL0 0x14
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#define PRESCL_CTRL0_I2C(x) ((x) << 16)
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@ -388,6 +391,10 @@ struct cdns_i3c_xfer {
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struct cdns_i3c_cmd cmds[0];
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};
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struct cdns_i3c_data {
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u8 thd_delay_ns;
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};
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struct cdns_i3c_master {
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struct work_struct hj_work;
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struct i3c_master_controller base;
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@ -408,6 +415,7 @@ struct cdns_i3c_master {
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struct clk *pclk;
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struct cdns_i3c_master_caps caps;
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unsigned long i3c_scl_lim;
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const struct cdns_i3c_data *devdata;
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};
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static inline struct cdns_i3c_master *
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@ -1181,6 +1189,20 @@ static int cdns_i3c_master_do_daa(struct i3c_master_controller *m)
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return 0;
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}
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static u8 cdns_i3c_master_calculate_thd_delay(struct cdns_i3c_master *master)
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{
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unsigned long sysclk_rate = clk_get_rate(master->sysclk);
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u8 thd_delay = DIV_ROUND_UP(master->devdata->thd_delay_ns,
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(NSEC_PER_SEC / sysclk_rate));
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/* Every value greater than 3 is not valid. */
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if (thd_delay > THD_DELAY_MAX)
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thd_delay = THD_DELAY_MAX;
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/* CTLR_THD_DEL value is encoded. */
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return (THD_DELAY_MAX - thd_delay);
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}
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static int cdns_i3c_master_bus_init(struct i3c_master_controller *m)
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{
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struct cdns_i3c_master *master = to_cdns_i3c_master(m);
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@ -1264,6 +1286,15 @@ static int cdns_i3c_master_bus_init(struct i3c_master_controller *m)
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* We will issue ENTDAA afterwards from the threaded IRQ handler.
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*/
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ctrl |= CTRL_HJ_ACK | CTRL_HJ_DISEC | CTRL_HALT_EN | CTRL_MCS_EN;
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/*
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* Configure data hold delay based on device-specific data.
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*
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* MIPI I3C Specification 1.0 defines non-zero minimal tHD_PP timing on
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* master output. This setting allows to meet this timing on master's
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* SoC outputs, regardless of PCB balancing.
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*/
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ctrl |= CTRL_THD_DELAY(cdns_i3c_master_calculate_thd_delay(master));
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writel(ctrl, master->regs + CTRL);
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cdns_i3c_master_enable(master);
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@ -1521,6 +1552,15 @@ static void cdns_i3c_master_hj(struct work_struct *work)
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i3c_master_do_daa(&master->base);
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}
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static struct cdns_i3c_data cdns_i3c_devdata = {
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.thd_delay_ns = 10,
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};
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static const struct of_device_id cdns_i3c_master_of_ids[] = {
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{ .compatible = "cdns,i3c-master", .data = &cdns_i3c_devdata },
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{ /* sentinel */ },
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};
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static int cdns_i3c_master_probe(struct platform_device *pdev)
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{
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struct cdns_i3c_master *master;
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@ -1532,6 +1572,10 @@ static int cdns_i3c_master_probe(struct platform_device *pdev)
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if (!master)
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return -ENOMEM;
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master->devdata = of_device_get_match_data(&pdev->dev);
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if (!master->devdata)
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return -EINVAL;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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master->regs = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(master->regs))
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@ -1631,11 +1675,6 @@ static int cdns_i3c_master_remove(struct platform_device *pdev)
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return 0;
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}
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static const struct of_device_id cdns_i3c_master_of_ids[] = {
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{ .compatible = "cdns,i3c-master" },
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{ /* sentinel */ },
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};
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static struct platform_driver cdns_i3c_master = {
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.probe = cdns_i3c_master_probe,
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.remove = cdns_i3c_master_remove,
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