media: dt-bindings: media: qcom,camss: Fix whitespaces
Use tabs. CC: Rob Herring <robh+dt@kernel.org> CC: Mark Rutland <mark.rutland@arm.com> CC: devicetree@vger.kernel.org Signed-off-by: Todor Tomov <todor.tomov@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Hans Verkuil <hansverk@cisco.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
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@ -53,25 +53,25 @@ Qualcomm Camera Subsystem
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Usage: required
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Value type: <stringlist>
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Definition: Should contain the following entries:
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- "top_ahb"
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- "ispif_ahb"
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- "csiphy0_timer"
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- "csiphy1_timer"
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- "csi0_ahb"
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- "csi0"
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- "csi0_phy"
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- "csi0_pix"
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- "csi0_rdi"
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- "csi1_ahb"
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- "csi1"
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- "csi1_phy"
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- "csi1_pix"
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- "csi1_rdi"
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- "ahb"
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- "vfe0"
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- "csi_vfe0"
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- "vfe_ahb"
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- "vfe_axi"
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- "top_ahb"
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- "ispif_ahb"
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- "csiphy0_timer"
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- "csiphy1_timer"
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- "csi0_ahb"
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- "csi0"
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- "csi0_phy"
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- "csi0_pix"
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- "csi0_rdi"
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- "csi1_ahb"
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- "csi1"
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- "csi1_phy"
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- "csi1_pix"
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- "csi1_rdi"
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- "ahb"
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- "vfe0"
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- "csi_vfe0"
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- "vfe_ahb"
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- "vfe_axi"
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- vdda-supply:
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Usage: required
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Value type: <phandle>
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@ -95,17 +95,17 @@ Qualcomm Camera Subsystem
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- clock-lanes:
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Usage: required
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Value type: <u32>
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Definition: The physical clock lane index. The value
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must always be <1> as the physical clock
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lane is lane 1.
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Definition: The physical clock lane index. The value
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must always be <1> as the physical clock
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lane is lane 1.
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- data-lanes:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: An array of physical data lanes indexes.
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Position of an entry determines the logical
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lane number, while the value of an entry
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indicates physical lane index. Lane swapping
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is supported.
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Definition: An array of physical data lanes indexes.
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Position of an entry determines the logical
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lane number, while the value of an entry
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indicates physical lane index. Lane swapping
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is supported.
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* An Example
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@ -161,25 +161,25 @@ Qualcomm Camera Subsystem
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<&gcc GCC_CAMSS_CSI_VFE0_CLK>,
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<&gcc GCC_CAMSS_VFE_AHB_CLK>,
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<&gcc GCC_CAMSS_VFE_AXI_CLK>;
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clock-names = "top_ahb",
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"ispif_ahb",
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"csiphy0_timer",
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"csiphy1_timer",
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"csi0_ahb",
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"csi0",
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"csi0_phy",
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"csi0_pix",
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"csi0_rdi",
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"csi1_ahb",
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"csi1",
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"csi1_phy",
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"csi1_pix",
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"csi1_rdi",
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"ahb",
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"vfe0",
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"csi_vfe0",
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"vfe_ahb",
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"vfe_axi";
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clock-names = "top_ahb",
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"ispif_ahb",
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"csiphy0_timer",
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"csiphy1_timer",
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"csi0_ahb",
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"csi0",
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"csi0_phy",
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"csi0_pix",
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"csi0_rdi",
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"csi1_ahb",
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"csi1",
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"csi1_phy",
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"csi1_pix",
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"csi1_rdi",
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"ahb",
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"vfe0",
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"csi_vfe0",
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"vfe_ahb",
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"vfe_axi";
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vdda-supply = <&pm8916_l2>;
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iommus = <&apps_iommu 3>;
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ports {
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