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ARM: imx: remove ENABLE and BYPASS bits from clk-pllv3 driver 

Since ENABLE and BYPASS bits of PLLs are now implemented as separate
gate and mux clocks by clock drivers, the code handling these two bits
can be removed from clk-pllv3 driver.

Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
This commit is contained in:
Shawn Guo 2014-08-26 23:06:33 +08:00
Родитель db7c065945
Коммит dc4805c2e7
1 изменённых файлов: 0 добавлений и 37 удалений
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37
arch/arm/mach-imx/clk-pllv3.c
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@ -23,8 +23,6 @@
#define PLL_DENOM_OFFSET 0x20 #define PLL_DENOM_OFFSET 0x20
#define BM_PLL_POWER (0x1 << 12) #define BM_PLL_POWER (0x1 << 12)
#define BM_PLL_ENABLE (0x1 << 13)
#define BM_PLL_BYPASS (0x1 << 16)
#define BM_PLL_LOCK (0x1 << 31) #define BM_PLL_LOCK (0x1 << 31)
/** /**
@ -84,10 +82,6 @@ static int clk_pllv3_prepare(struct clk_hw *hw)
if (ret) if (ret)
return ret; return ret;
val = readl_relaxed(pll->base);
val &= ~BM_PLL_BYPASS;
writel_relaxed(val, pll->base);
return 0; return 0;
} }
@ -97,7 +91,6 @@ static void clk_pllv3_unprepare(struct clk_hw *hw)
u32 val; u32 val;
val = readl_relaxed(pll->base); val = readl_relaxed(pll->base);
val |= BM_PLL_BYPASS;
if (pll->powerup_set) if (pll->powerup_set)
val &= ~BM_PLL_POWER; val &= ~BM_PLL_POWER;
else else
@ -105,28 +98,6 @@ static void clk_pllv3_unprepare(struct clk_hw *hw)
writel_relaxed(val, pll->base); writel_relaxed(val, pll->base);
} }
static int clk_pllv3_enable(struct clk_hw *hw)
{
struct clk_pllv3 *pll = to_clk_pllv3(hw);
u32 val;
val = readl_relaxed(pll->base);
val |= BM_PLL_ENABLE;
writel_relaxed(val, pll->base);
return 0;
}
static void clk_pllv3_disable(struct clk_hw *hw)
{
struct clk_pllv3 *pll = to_clk_pllv3(hw);
u32 val;
val = readl_relaxed(pll->base);
val &= ~BM_PLL_ENABLE;
writel_relaxed(val, pll->base);
}
static unsigned long clk_pllv3_recalc_rate(struct clk_hw *hw, static unsigned long clk_pllv3_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate) unsigned long parent_rate)
{ {
@ -169,8 +140,6 @@ static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate,
static const struct clk_ops clk_pllv3_ops = { static const struct clk_ops clk_pllv3_ops = {
.prepare = clk_pllv3_prepare, .prepare = clk_pllv3_prepare,
.unprepare = clk_pllv3_unprepare, .unprepare = clk_pllv3_unprepare,
.enable = clk_pllv3_enable,
.disable = clk_pllv3_disable,
.recalc_rate = clk_pllv3_recalc_rate, .recalc_rate = clk_pllv3_recalc_rate,
.round_rate = clk_pllv3_round_rate, .round_rate = clk_pllv3_round_rate,
.set_rate = clk_pllv3_set_rate, .set_rate = clk_pllv3_set_rate,
@ -225,8 +194,6 @@ static int clk_pllv3_sys_set_rate(struct clk_hw *hw, unsigned long rate,
static const struct clk_ops clk_pllv3_sys_ops = { static const struct clk_ops clk_pllv3_sys_ops = {
.prepare = clk_pllv3_prepare, .prepare = clk_pllv3_prepare,
.unprepare = clk_pllv3_unprepare, .unprepare = clk_pllv3_unprepare,
.enable = clk_pllv3_enable,
.disable = clk_pllv3_disable,
.recalc_rate = clk_pllv3_sys_recalc_rate, .recalc_rate = clk_pllv3_sys_recalc_rate,
.round_rate = clk_pllv3_sys_round_rate, .round_rate = clk_pllv3_sys_round_rate,
.set_rate = clk_pllv3_sys_set_rate, .set_rate = clk_pllv3_sys_set_rate,
@ -299,8 +266,6 @@ static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate,
static const struct clk_ops clk_pllv3_av_ops = { static const struct clk_ops clk_pllv3_av_ops = {
.prepare = clk_pllv3_prepare, .prepare = clk_pllv3_prepare,
.unprepare = clk_pllv3_unprepare, .unprepare = clk_pllv3_unprepare,
.enable = clk_pllv3_enable,
.disable = clk_pllv3_disable,
.recalc_rate = clk_pllv3_av_recalc_rate, .recalc_rate = clk_pllv3_av_recalc_rate,
.round_rate = clk_pllv3_av_round_rate, .round_rate = clk_pllv3_av_round_rate,
.set_rate = clk_pllv3_av_set_rate, .set_rate = clk_pllv3_av_set_rate,
@ -315,8 +280,6 @@ static unsigned long clk_pllv3_enet_recalc_rate(struct clk_hw *hw,
static const struct clk_ops clk_pllv3_enet_ops = { static const struct clk_ops clk_pllv3_enet_ops = {
.prepare = clk_pllv3_prepare, .prepare = clk_pllv3_prepare,
.unprepare = clk_pllv3_unprepare, .unprepare = clk_pllv3_unprepare,
.enable = clk_pllv3_enable,
.disable = clk_pllv3_disable,
.recalc_rate = clk_pllv3_enet_recalc_rate, .recalc_rate = clk_pllv3_enet_recalc_rate,
}; };