radeon: Fix KMS CP writeback on big endian machines.
This is necessary even with PCI(e) GART, and it makes writeback work even with AGP on my PowerBook. Might still be unreliable with older revisions of UniNorth and other AGP bridges though. Signed-off-by: Michel Dänzer <daenzer@vmware.com> Reviewed-by: Alex Deucher <alex.deucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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0a0883c843
Коммит
dc66b325f1
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@ -79,7 +79,7 @@ static bool radeon_fence_poll_locked(struct radeon_device *rdev)
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scratch_index = R600_WB_EVENT_OFFSET + rdev->fence_drv.scratch_reg - rdev->scratch.reg_base;
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else
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scratch_index = RADEON_WB_SCRATCH_OFFSET + rdev->fence_drv.scratch_reg - rdev->scratch.reg_base;
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seq = rdev->wb.wb[scratch_index/4];
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seq = le32_to_cpu(rdev->wb.wb[scratch_index/4]);
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} else
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seq = RREG32(rdev->fence_drv.scratch_reg);
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if (seq != rdev->fence_drv.last_seq) {
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@ -248,7 +248,7 @@ void radeon_ib_pool_fini(struct radeon_device *rdev)
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void radeon_ring_free_size(struct radeon_device *rdev)
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{
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if (rdev->wb.enabled)
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rdev->cp.rptr = rdev->wb.wb[RADEON_WB_CP_RPTR_OFFSET/4];
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rdev->cp.rptr = le32_to_cpu(rdev->wb.wb[RADEON_WB_CP_RPTR_OFFSET/4]);
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else {
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if (rdev->family >= CHIP_R600)
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rdev->cp.rptr = RREG32(R600_CP_RB_RPTR);
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