ASoC: qcom: Add register definition for codec rddma and wrdma
Add register definitions for codec read dma and write dma lpass interface. Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> Co-developed-by: Venkata Prasad Potturu <quic_potturu@quicinc.com> Signed-off-by: Venkata Prasad Potturu <quic_potturu@quicinc.com> Reviewed-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Link: https://lore.kernel.org/r/1645716828-15305-5-git-send-email-quic_srivasam@quicinc.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Srinivasa Rao Mandadapu
Mark Brown
Родитель
16413d5c5a
Коммит
dc8d9766bc
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@ -74,6 +74,21 @@
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#define LPAIF_IRQSTAT_REG(v, port) LPAIF_IRQ_REG_ADDR(v, 0x4, (port))
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#define LPAIF_IRQCLEAR_REG(v, port) LPAIF_IRQ_REG_ADDR(v, 0xC, (port))
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/* LPAIF RXTX IRQ */
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#define LPAIF_RXTX_IRQ_REG_ADDR(v, addr, port) \
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(v->rxtx_irq_reg_base + (addr) + v->rxtx_irq_reg_stride * (port))
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#define LPAIF_RXTX_IRQEN_REG(v, port) LPAIF_RXTX_IRQ_REG_ADDR(v, 0x0, port)
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#define LPAIF_RXTX_IRQSTAT_REG(v, port) LPAIF_RXTX_IRQ_REG_ADDR(v, 0x4, port)
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#define LPAIF_RXTX_IRQCLEAR_REG(v, port) LPAIF_RXTX_IRQ_REG_ADDR(v, 0xC, port)
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/* LPAIF VA IRQ */
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#define LPAIF_VA_IRQ_REG_ADDR(v, addr, port) \
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(v->va_irq_reg_base + (addr) + v->va_irq_reg_stride * (port))
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#define LPAIF_VA_IRQEN_REG(v, port) LPAIF_VA_IRQ_REG_ADDR(v, 0x0, port)
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#define LPAIF_VA_IRQSTAT_REG(v, port) LPAIF_VA_IRQ_REG_ADDR(v, 0x4, port)
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#define LPAIF_VA_IRQCLEAR_REG(v, port) LPAIF_VA_IRQ_REG_ADDR(v, 0xC, port)
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#define LPASS_HDMITX_APP_IRQ_REG_ADDR(v, addr) \
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((v->hdmi_irq_reg_base) + (addr))
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@ -139,12 +154,112 @@
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(LPAIF_INTFDMA_REG(v, chan, reg, dai_id)) : \
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LPAIF_WRDMA##reg##_REG(v, chan))
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#define LPAIF_DMACTL_REG(v, chan, dir, dai_id) __LPAIF_DMA_REG(v, chan, dir, CTL, dai_id)
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#define LPAIF_DMABASE_REG(v, chan, dir, dai_id) __LPAIF_DMA_REG(v, chan, dir, BASE, dai_id)
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#define LPAIF_DMABUFF_REG(v, chan, dir, dai_id) __LPAIF_DMA_REG(v, chan, dir, BUFF, dai_id)
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#define LPAIF_DMACURR_REG(v, chan, dir, dai_id) __LPAIF_DMA_REG(v, chan, dir, CURR, dai_id)
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#define LPAIF_DMAPER_REG(v, chan, dir, dai_id) __LPAIF_DMA_REG(v, chan, dir, PER, dai_id)
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#define LPAIF_DMAPERCNT_REG(v, chan, dir, dai_id) __LPAIF_DMA_REG(v, chan, dir, PERCNT, dai_id)
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#define LPAIF_DMACTL_REG(v, chan, dir, dai_id) \
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(is_cdc_dma_port(dai_id) ? \
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__LPAIF_CDC_DMA_REG(v, chan, dir, CTL, dai_id) : \
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__LPAIF_DMA_REG(v, chan, dir, CTL, dai_id))
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#define LPAIF_DMABASE_REG(v, chan, dir, dai_id) \
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(is_cdc_dma_port(dai_id) ? \
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__LPAIF_CDC_DMA_REG(v, chan, dir, BASE, dai_id) : \
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__LPAIF_DMA_REG(v, chan, dir, BASE, dai_id))
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#define LPAIF_DMABUFF_REG(v, chan, dir, dai_id) \
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(is_cdc_dma_port(dai_id) ? \
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__LPAIF_CDC_DMA_REG(v, chan, dir, BUFF, dai_id) : \
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__LPAIF_DMA_REG(v, chan, dir, BUFF, dai_id))
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#define LPAIF_DMACURR_REG(v, chan, dir, dai_id) \
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(is_cdc_dma_port(dai_id) ? \
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__LPAIF_CDC_DMA_REG(v, chan, dir, CURR, dai_id) : \
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__LPAIF_DMA_REG(v, chan, dir, CURR, dai_id))
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#define LPAIF_DMAPER_REG(v, chan, dir, dai_id) \
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(is_cdc_dma_port(dai_id) ? \
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__LPAIF_CDC_DMA_REG(v, chan, dir, PER, dai_id) : \
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__LPAIF_DMA_REG(v, chan, dir, PER, dai_id))
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#define LPAIF_DMAPERCNT_REG(v, chan, dir, dai_id) \
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(is_cdc_dma_port(dai_id) ? \
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__LPAIF_CDC_DMA_REG(v, chan, dir, PERCNT, dai_id) : \
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__LPAIF_DMA_REG(v, chan, dir, PERCNT, dai_id))
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#define LPAIF_CDC_RDMA_REG_ADDR(v, addr, chan, dai_id) \
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(is_rxtx_cdc_dma_port(dai_id) ? \
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(v->rxtx_rdma_reg_base + (addr) + v->rxtx_rdma_reg_stride * (chan)) : \
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(v->va_rdma_reg_base + (addr) + v->va_rdma_reg_stride * (chan)))
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#define LPAIF_CDC_RXTX_RDMACTL_REG(v, chan, dai_id) \
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LPAIF_CDC_RDMA_REG_ADDR(v, 0x00, (chan), dai_id)
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#define LPAIF_CDC_RXTX_RDMABASE_REG(v, chan, dai_id) \
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LPAIF_CDC_RDMA_REG_ADDR(v, 0x04, (chan), dai_id)
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#define LPAIF_CDC_RXTX_RDMABUFF_REG(v, chan, dai_id) \
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LPAIF_CDC_RDMA_REG_ADDR(v, 0x08, (chan), dai_id)
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#define LPAIF_CDC_RXTX_RDMACURR_REG(v, chan, dai_id) \
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LPAIF_CDC_RDMA_REG_ADDR(v, 0x0C, (chan), dai_id)
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#define LPAIF_CDC_RXTX_RDMAPER_REG(v, chan, dai_id) \
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LPAIF_CDC_RDMA_REG_ADDR(v, 0x10, (chan), dai_id)
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#define LPAIF_CDC_RXTX_RDMA_INTF_REG(v, chan, dai_id) \
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LPAIF_CDC_RDMA_REG_ADDR(v, 0x50, (chan), dai_id)
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#define LPAIF_CDC_VA_RDMACTL_REG(v, chan, dai_id) LPAIF_CDC_RDMA_REG_ADDR(v, 0x00, (chan), dai_id)
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#define LPAIF_CDC_VA_RDMABASE_REG(v, chan, dai_id) LPAIF_CDC_RDMA_REG_ADDR(v, 0x04, (chan), dai_id)
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#define LPAIF_CDC_VA_RDMABUFF_REG(v, chan, dai_id) LPAIF_CDC_RDMA_REG_ADDR(v, 0x08, (chan), dai_id)
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#define LPAIF_CDC_VA_RDMACURR_REG(v, chan, dai_id) LPAIF_CDC_RDMA_REG_ADDR(v, 0x0C, (chan), dai_id)
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#define LPAIF_CDC_VA_RDMAPER_REG(v, chan, dai_id) LPAIF_CDC_RDMA_REG_ADDR(v, 0x10, (chan), dai_id)
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#define LPAIF_CDC_VA_RDMA_INTF_REG(v, chan, dai_id) \
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LPAIF_CDC_RDMA_REG_ADDR(v, 0x50, (chan), dai_id)
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#define LPAIF_CDC_WRDMA_REG_ADDR(v, addr, chan, dai_id) \
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(is_rxtx_cdc_dma_port(dai_id) ? \
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(v->rxtx_wrdma_reg_base + (addr) + \
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v->rxtx_wrdma_reg_stride * (chan - v->rxtx_wrdma_channel_start)) : \
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(v->va_wrdma_reg_base + (addr) + \
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v->va_wrdma_reg_stride * (chan - v->va_wrdma_channel_start)))
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#define LPAIF_CDC_RXTX_WRDMACTL_REG(v, chan, dai_id) \
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LPAIF_CDC_WRDMA_REG_ADDR(v, 0x00, (chan), dai_id)
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#define LPAIF_CDC_RXTX_WRDMABASE_REG(v, chan, dai_id) \
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LPAIF_CDC_WRDMA_REG_ADDR(v, 0x04, (chan), dai_id)
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#define LPAIF_CDC_RXTX_WRDMABUFF_REG(v, chan, dai_id) \
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LPAIF_CDC_WRDMA_REG_ADDR(v, 0x08, (chan), dai_id)
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#define LPAIF_CDC_RXTX_WRDMACURR_REG(v, chan, dai_id) \
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LPAIF_CDC_WRDMA_REG_ADDR(v, 0x0C, (chan), dai_id)
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#define LPAIF_CDC_RXTX_WRDMAPER_REG(v, chan, dai_id) \
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LPAIF_CDC_WRDMA_REG_ADDR(v, 0x10, (chan), dai_id)
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#define LPAIF_CDC_RXTX_WRDMA_INTF_REG(v, chan, dai_id) \
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LPAIF_CDC_WRDMA_REG_ADDR(v, 0x50, (chan), dai_id)
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#define LPAIF_CDC_VA_WRDMACTL_REG(v, chan, dai_id) \
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LPAIF_CDC_WRDMA_REG_ADDR(v, 0x00, (chan), dai_id)
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#define LPAIF_CDC_VA_WRDMABASE_REG(v, chan, dai_id) \
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LPAIF_CDC_WRDMA_REG_ADDR(v, 0x04, (chan), dai_id)
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#define LPAIF_CDC_VA_WRDMABUFF_REG(v, chan, dai_id) \
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LPAIF_CDC_WRDMA_REG_ADDR(v, 0x08, (chan), dai_id)
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#define LPAIF_CDC_VA_WRDMACURR_REG(v, chan, dai_id) \
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LPAIF_CDC_WRDMA_REG_ADDR(v, 0x0C, (chan), dai_id)
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#define LPAIF_CDC_VA_WRDMAPER_REG(v, chan, dai_id) \
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LPAIF_CDC_WRDMA_REG_ADDR(v, 0x10, (chan), dai_id)
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#define LPAIF_CDC_VA_WRDMA_INTF_REG(v, chan, dai_id) \
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LPAIF_CDC_WRDMA_REG_ADDR(v, 0x50, (chan), dai_id)
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#define __LPAIF_CDC_RDDMA_REG(v, chan, dir, reg, dai_id) \
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(is_rxtx_cdc_dma_port(dai_id) ? LPAIF_CDC_RXTX_RDMA##reg##_REG(v, chan, dai_id) : \
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LPAIF_CDC_VA_RDMA##reg##_REG(v, chan, dai_id))
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#define __LPAIF_CDC_WRDMA_REG(v, chan, dir, reg, dai_id) \
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(is_rxtx_cdc_dma_port(dai_id) ? LPAIF_CDC_RXTX_WRDMA##reg##_REG(v, chan, dai_id) : \
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LPAIF_CDC_VA_WRDMA##reg##_REG(v, chan, dai_id))
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#define __LPAIF_CDC_DMA_REG(v, chan, dir, reg, dai_id) \
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((dir == SNDRV_PCM_STREAM_PLAYBACK) ? \
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__LPAIF_CDC_RDDMA_REG(v, chan, dir, reg, dai_id) : \
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__LPAIF_CDC_WRDMA_REG(v, chan, dir, reg, dai_id))
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#define LPAIF_CDC_INTF_REG(v, chan, dir, dai_id) \
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((dir == SNDRV_PCM_STREAM_PLAYBACK) ? \
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LPAIF_CDC_RDMA_INTF_REG(v, chan, dai_id) : \
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LPAIF_CDC_WRDMA_INTF_REG(v, chan, dai_id))
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#define LPAIF_INTF_REG(v, chan, dir, dai_id) \
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(is_cdc_dma_port(dai_id) ? \
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LPAIF_CDC_INTF_REG(v, chan, dir, dai_id) : \
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LPAIF_DMACTL_REG(v, chan, dir, dai_id))
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#define LPAIF_DMACTL_BURSTEN_SINGLE 0
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#define LPAIF_DMACTL_BURSTEN_INCR4 1
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@ -38,6 +38,27 @@
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return -EINVAL; \
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} while (0)
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static inline bool is_cdc_dma_port(int dai_id)
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{
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switch (dai_id) {
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case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9:
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case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8:
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case LPASS_CDC_DMA_VA_TX0 ... LPASS_CDC_DMA_VA_TX8:
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return true;
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}
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return false;
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}
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static inline bool is_rxtx_cdc_dma_port(int dai_id)
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{
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switch (dai_id) {
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case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9:
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case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8:
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return true;
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}
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return false;
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}
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struct lpaif_i2sctl {
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struct regmap_field *loopback;
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struct regmap_field *spken;
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