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ARM: dts: qcom-msm8974: change invalid flag IRQ NONE to valid value 

Change the third field of the "interrupts" property from
IRQ_TYPE_NONE to the correct value.

I do not have hardware documentation for these devices, so I
followed a mail list suggestion to copy the flag values from the same
type of node in arch/arm64/boot/dts/qcom/msm8916.dtsi

Signed-off-by: Frank Rowand <frank.rowand@sony.com>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This commit is contained in:
Frank Rowand 2018-09-06 22:33:14 -07:00 коммит произвёл Andy Gross
Родитель 23a81d371b
Коммит dcf1450114
1 изменённых файлов: 13 добавлений и 13 удалений
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26
arch/arm/boot/dts/qcom-msm8974.dtsi
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@ -586,7 +586,7 @@
blsp1_uart1: serial@f991d000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0xf991d000 0x1000>;
interrupts = <GIC_SPI 107 IRQ_TYPE_NONE>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
status = "disabled";
@ -595,7 +595,7 @@
blsp1_uart2: serial@f991e000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0xf991e000 0x1000>;
interrupts = <GIC_SPI 108 IRQ_TYPE_NONE>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
status = "disabled";
@ -605,8 +605,8 @@
compatible = "qcom,sdhci-msm-v4";
reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
reg-names = "hc_mem", "core_mem";
interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>,
<GIC_SPI 138 IRQ_TYPE_NONE>;
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC1_APPS_CLK>,
<&gcc GCC_SDCC1_AHB_CLK>,
@ -619,8 +619,8 @@
compatible = "qcom,sdhci-msm-v4";
reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
reg-names = "hc_mem", "core_mem";
interrupts = <GIC_SPI 127 IRQ_TYPE_NONE>,
<GIC_SPI 224 IRQ_TYPE_NONE>;
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC3_APPS_CLK>,
<&gcc GCC_SDCC3_AHB_CLK>,
@ -633,8 +633,8 @@
compatible = "qcom,sdhci-msm-v4";
reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
reg-names = "hc_mem", "core_mem";
interrupts = <GIC_SPI 125 IRQ_TYPE_NONE>,
<GIC_SPI 221 IRQ_TYPE_NONE>;
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC2_APPS_CLK>,
<&gcc GCC_SDCC2_AHB_CLK>,
@ -701,14 +701,14 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 208 IRQ_TYPE_NONE>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
};
i2c@f9924000 {
status = "disabled";
compatible = "qcom,i2c-qup-v2.1.1";
reg = <0xf9924000 0x1000>;
interrupts = <GIC_SPI 96 IRQ_TYPE_NONE>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
#address-cells = <1>;
@ -719,7 +719,7 @@
status = "disabled";
compatible = "qcom,i2c-qup-v2.1.1";
reg = <0xf9964000 0x1000>;
interrupts = <GIC_SPI 102 IRQ_TYPE_NONE>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
#address-cells = <1>;
@ -730,7 +730,7 @@
status = "disabled";
compatible = "qcom,i2c-qup-v2.1.1";
reg = <0xf9967000 0x1000>;
interrupts = <GIC_SPI 105 IRQ_TYPE_NONE>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
#address-cells = <1>;
@ -746,7 +746,7 @@
<0xfc4cb000 0x1000>,
<0xfc4ca000 0x1000>;
interrupt-names = "periph_irq";
interrupts = <GIC_SPI 190 IRQ_TYPE_NONE>;
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
qcom,ee = <0>;
qcom,channel = <0>;
#address-cells = <2>;