OMAPDSS: HDMI: move irq & phy pwr handling
HDMI IRQ handling was moved into hdmi_phy.c when restructuring the HDMI driver. While this worked fine, it's not correct. The HDMI IRQ handling should be either in the hdmi_wp, or in the main hdmi driver. This patch moves the handling to the main hdmi driver, as I feel it's a more appropriate choice. This move also requires changing the handling of the PHY power, as that was partly handled in the IRQ handler. The PHY power is handled via the WP module. An option would be to give HDMI PHY driver function pointers that it could use to manage the PHY power, but as the PHY power is not needed to access the PHY registers, the handling was also moved to the main HDMI driver. This could be changed later if need be. Note that there's slightly similar power issue with the PLL: the HDMI PLLs power is also handled via the WP module. For now, the PLL power handling is still done inside the PLL driver. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
This commit is contained in:
Tomi Valkeinen
Родитель
543e761fb9
Коммит
dcf5f7299e
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@ -351,8 +351,6 @@ struct hdmi_pll_data {
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struct hdmi_phy_data {
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void __iomem *base;
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int irq;
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u8 lane_function[4];
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u8 lane_polarity[4];
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};
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@ -420,9 +418,7 @@ void hdmi_pll_compute(struct hdmi_pll_data *pll, unsigned long clkin, int phy);
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int hdmi_pll_init(struct platform_device *pdev, struct hdmi_pll_data *pll);
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/* HDMI PHY funcs */
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int hdmi_phy_enable(struct hdmi_phy_data *phy, struct hdmi_wp_data *wp,
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struct hdmi_config *cfg);
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void hdmi_phy_disable(struct hdmi_phy_data *phy, struct hdmi_wp_data *wp);
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int hdmi_phy_configure(struct hdmi_phy_data *phy, struct hdmi_config *cfg);
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void hdmi_phy_dump(struct hdmi_phy_data *phy, struct seq_file *s);
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int hdmi_phy_init(struct platform_device *pdev, struct hdmi_phy_data *phy);
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int hdmi_phy_parse_lanes(struct hdmi_phy_data *phy, const u32 *lanes);
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@ -81,6 +81,37 @@ static void hdmi_runtime_put(void)
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WARN_ON(r < 0 && r != -ENOSYS);
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}
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static irqreturn_t hdmi_irq_handler(int irq, void *data)
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{
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struct hdmi_wp_data *wp = data;
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u32 irqstatus;
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irqstatus = hdmi_wp_get_irqstatus(wp);
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hdmi_wp_set_irqstatus(wp, irqstatus);
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if ((irqstatus & HDMI_IRQ_LINK_CONNECT) &&
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irqstatus & HDMI_IRQ_LINK_DISCONNECT) {
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/*
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* If we get both connect and disconnect interrupts at the same
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* time, turn off the PHY, clear interrupts, and restart, which
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* raises connect interrupt if a cable is connected, or nothing
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* if cable is not connected.
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*/
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hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF);
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hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT |
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HDMI_IRQ_LINK_DISCONNECT);
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hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
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} else if (irqstatus & HDMI_IRQ_LINK_CONNECT) {
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hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON);
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} else if (irqstatus & HDMI_IRQ_LINK_DISCONNECT) {
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hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
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}
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return IRQ_HANDLED;
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}
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static int hdmi_init_regulator(void)
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{
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int r;
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@ -150,11 +181,16 @@ static int hdmi_power_on_full(struct omap_dss_device *dssdev)
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struct omap_video_timings *p;
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struct omap_overlay_manager *mgr = hdmi.output.manager;
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unsigned long phy;
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struct hdmi_wp_data *wp = &hdmi.wp;
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r = hdmi_power_on_core(dssdev);
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if (r)
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return r;
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/* disable and clear irqs */
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hdmi_wp_clear_irqenable(wp, 0xffffffff);
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hdmi_wp_set_irqstatus(wp, 0xffffffff);
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p = &hdmi.cfg.timings;
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DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p->x_res, p->y_res);
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@ -171,12 +207,16 @@ static int hdmi_power_on_full(struct omap_dss_device *dssdev)
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goto err_pll_enable;
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}
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r = hdmi_phy_enable(&hdmi.phy, &hdmi.wp, &hdmi.cfg);
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r = hdmi_phy_configure(&hdmi.phy, &hdmi.cfg);
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if (r) {
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DSSDBG("Failed to start PHY\n");
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goto err_phy_enable;
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DSSDBG("Failed to configure PHY\n");
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goto err_phy_cfg;
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}
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r = hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
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if (r)
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goto err_phy_pwr;
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hdmi4_configure(&hdmi.core, &hdmi.wp, &hdmi.cfg);
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/* bypass TV gamma table */
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@ -193,13 +233,17 @@ static int hdmi_power_on_full(struct omap_dss_device *dssdev)
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if (r)
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goto err_mgr_enable;
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hdmi_wp_set_irqenable(wp,
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HDMI_IRQ_LINK_CONNECT | HDMI_IRQ_LINK_DISCONNECT);
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return 0;
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err_mgr_enable:
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hdmi_wp_video_stop(&hdmi.wp);
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err_vid_enable:
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hdmi_phy_disable(&hdmi.phy, &hdmi.wp);
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err_phy_enable:
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err_phy_cfg:
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hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF);
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err_phy_pwr:
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hdmi_pll_disable(&hdmi.pll, &hdmi.wp);
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err_pll_enable:
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hdmi_power_off_core(dssdev);
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@ -210,10 +254,14 @@ static void hdmi_power_off_full(struct omap_dss_device *dssdev)
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{
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struct omap_overlay_manager *mgr = hdmi.output.manager;
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hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff);
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dss_mgr_disable(mgr);
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hdmi_wp_video_stop(&hdmi.wp);
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hdmi_phy_disable(&hdmi.phy, &hdmi.wp);
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hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF);
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hdmi_pll_disable(&hdmi.pll, &hdmi.wp);
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hdmi_power_off_core(dssdev);
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@ -636,6 +684,7 @@ err:
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static int omapdss_hdmihw_probe(struct platform_device *pdev)
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{
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int r;
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int irq;
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hdmi.pdev = pdev;
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@ -669,6 +718,20 @@ static int omapdss_hdmihw_probe(struct platform_device *pdev)
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return r;
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}
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irq = platform_get_irq(pdev, 0);
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if (irq < 0) {
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DSSERR("platform_get_irq failed\n");
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return -ENODEV;
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}
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r = devm_request_threaded_irq(&pdev->dev, irq,
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NULL, hdmi_irq_handler,
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IRQF_ONESHOT, "OMAP HDMI", &hdmi.wp);
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if (r) {
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DSSERR("HDMI IRQ request failed\n");
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return r;
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}
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pm_runtime_enable(&pdev->dev);
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hdmi_init_output(pdev);
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@ -28,37 +28,6 @@ void hdmi_phy_dump(struct hdmi_phy_data *phy, struct seq_file *s)
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DUMPPHY(HDMI_TXPHY_PAD_CFG_CTRL);
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}
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static irqreturn_t hdmi_irq_handler(int irq, void *data)
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{
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struct hdmi_wp_data *wp = data;
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u32 irqstatus;
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irqstatus = hdmi_wp_get_irqstatus(wp);
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hdmi_wp_set_irqstatus(wp, irqstatus);
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if ((irqstatus & HDMI_IRQ_LINK_CONNECT) &&
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irqstatus & HDMI_IRQ_LINK_DISCONNECT) {
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/*
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* If we get both connect and disconnect interrupts at the same
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* time, turn off the PHY, clear interrupts, and restart, which
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* raises connect interrupt if a cable is connected, or nothing
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* if cable is not connected.
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*/
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hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF);
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hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT |
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HDMI_IRQ_LINK_DISCONNECT);
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hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
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} else if (irqstatus & HDMI_IRQ_LINK_CONNECT) {
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hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON);
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} else if (irqstatus & HDMI_IRQ_LINK_DISCONNECT) {
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hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
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}
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return IRQ_HANDLED;
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}
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int hdmi_phy_parse_lanes(struct hdmi_phy_data *phy, const u32 *lanes)
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{
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int i;
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@ -150,21 +119,8 @@ static void hdmi_phy_configure_lanes(struct hdmi_phy_data *phy)
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REG_FLD_MOD(phy->base, HDMI_TXPHY_PAD_CFG_CTRL, pol_val, 30, 27);
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}
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int hdmi_phy_enable(struct hdmi_phy_data *phy, struct hdmi_wp_data *wp,
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struct hdmi_config *cfg)
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int hdmi_phy_configure(struct hdmi_phy_data *phy, struct hdmi_config *cfg)
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{
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u16 r = 0;
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u32 irqstatus;
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hdmi_wp_clear_irqenable(wp, 0xffffffff);
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irqstatus = hdmi_wp_get_irqstatus(wp);
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hdmi_wp_set_irqstatus(wp, irqstatus);
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r = hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
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if (r)
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return r;
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/*
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* Read address 0 in order to get the SCP reset done completed
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* Dummy access performed to make sure reset is done
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@ -185,27 +141,9 @@ int hdmi_phy_enable(struct hdmi_phy_data *phy, struct hdmi_wp_data *wp,
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hdmi_phy_configure_lanes(phy);
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r = request_threaded_irq(phy->irq, NULL, hdmi_irq_handler,
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IRQF_ONESHOT, "OMAP HDMI", wp);
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if (r) {
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DSSERR("HDMI IRQ request failed\n");
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hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF);
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return r;
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}
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hdmi_wp_set_irqenable(wp,
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HDMI_IRQ_LINK_CONNECT | HDMI_IRQ_LINK_DISCONNECT);
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return 0;
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}
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void hdmi_phy_disable(struct hdmi_phy_data *phy, struct hdmi_wp_data *wp)
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{
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free_irq(phy->irq, wp);
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hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF);
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}
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#define PHY_OFFSET 0x300
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#define PHY_SIZE 0x100
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@ -240,11 +178,5 @@ int hdmi_phy_init(struct platform_device *pdev, struct hdmi_phy_data *phy)
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return -ENOMEM;
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}
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phy->irq = platform_get_irq(pdev, 0);
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if (phy->irq < 0) {
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DSSERR("platform_get_irq failed\n");
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return -ENODEV;
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}
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return 0;
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}
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