x86: Cleanup io_apic
Sanitize functions. Remove irq_desc pointer magic. Preparatory patch for further cleanups. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Thomas Gleixner
Родитель
d4eba29770
Коммит
dd5f15e5cf
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@ -572,11 +572,6 @@ static void __unmask_and_level_IO_APIC_irq(struct irq_pin_list *entry)
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IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
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}
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static void __unmask_IO_APIC_irq(struct irq_cfg *cfg)
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{
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io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
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}
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static void io_apic_sync(struct irq_pin_list *entry)
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{
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/*
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@ -588,44 +583,41 @@ static void io_apic_sync(struct irq_pin_list *entry)
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readl(&io_apic->data);
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}
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static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
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static void mask_ioapic(struct irq_cfg *cfg)
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{
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unsigned long flags;
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raw_spin_lock_irqsave(&ioapic_lock, flags);
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io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
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}
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static void mask_IO_APIC_irq_desc(struct irq_desc *desc)
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{
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struct irq_cfg *cfg = get_irq_desc_chip_data(desc);
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unsigned long flags;
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BUG_ON(!cfg);
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raw_spin_lock_irqsave(&ioapic_lock, flags);
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__mask_IO_APIC_irq(cfg);
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raw_spin_unlock_irqrestore(&ioapic_lock, flags);
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}
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static void unmask_IO_APIC_irq_desc(struct irq_desc *desc)
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static void mask_ioapic_irq(unsigned int irq)
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{
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struct irq_cfg *cfg = get_irq_chip_data(irq);
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mask_ioapic(cfg);
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}
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static void __unmask_ioapic(struct irq_cfg *cfg)
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{
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io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
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}
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static void unmask_ioapic(struct irq_cfg *cfg)
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{
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struct irq_cfg *cfg = get_irq_desc_chip_data(desc);
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unsigned long flags;
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raw_spin_lock_irqsave(&ioapic_lock, flags);
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__unmask_IO_APIC_irq(cfg);
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__unmask_ioapic(cfg);
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raw_spin_unlock_irqrestore(&ioapic_lock, flags);
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}
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static void mask_IO_APIC_irq(unsigned int irq)
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static void unmask_ioapic_irq(unsigned int irq)
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{
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struct irq_desc *desc = irq_to_desc(irq);
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struct irq_cfg *cfg = get_irq_chip_data(irq);
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mask_IO_APIC_irq_desc(desc);
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}
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static void unmask_IO_APIC_irq(unsigned int irq)
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{
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struct irq_desc *desc = irq_to_desc(irq);
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unmask_IO_APIC_irq_desc(desc);
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unmask_ioapic(cfg);
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}
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static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
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@ -2239,7 +2231,7 @@ static unsigned int startup_ioapic_irq(unsigned int irq)
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was_pending = 1;
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}
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cfg = irq_cfg(irq);
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__unmask_IO_APIC_irq(cfg);
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__unmask_ioapic(cfg);
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raw_spin_unlock_irqrestore(&ioapic_lock, flags);
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return was_pending;
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@ -2498,10 +2490,8 @@ unlock:
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irq_exit();
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}
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static void __irq_complete_move(struct irq_desc **descp, unsigned vector)
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static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector)
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{
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struct irq_desc *desc = *descp;
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struct irq_cfg *cfg = get_irq_desc_chip_data(desc);
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unsigned me;
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if (likely(!cfg->move_in_progress))
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@ -2513,30 +2503,29 @@ static void __irq_complete_move(struct irq_desc **descp, unsigned vector)
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send_cleanup_vector(cfg);
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}
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static void irq_complete_move(struct irq_desc **descp)
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static void irq_complete_move(struct irq_cfg *cfg)
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{
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__irq_complete_move(descp, ~get_irq_regs()->orig_ax);
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__irq_complete_move(cfg, ~get_irq_regs()->orig_ax);
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}
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void irq_force_complete_move(int irq)
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{
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struct irq_desc *desc = irq_to_desc(irq);
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struct irq_cfg *cfg = get_irq_desc_chip_data(desc);
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struct irq_cfg *cfg = get_irq_chip_data(irq);
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if (!cfg)
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return;
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__irq_complete_move(&desc, cfg->vector);
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__irq_complete_move(cfg, cfg->vector);
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}
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#else
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static inline void irq_complete_move(struct irq_desc **descp) {}
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static inline void irq_complete_move(struct irq_cfg *cfg) { }
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#endif
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static void ack_apic_edge(unsigned int irq)
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{
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struct irq_desc *desc = irq_to_desc(irq);
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struct irq_cfg *cfg = get_irq_chip_data(irq);
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irq_complete_move(&desc);
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irq_complete_move(cfg);
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move_native_irq(irq);
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ack_APIC_irq();
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}
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@ -2559,10 +2548,12 @@ atomic_t irq_mis_count;
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* Otherwise, we simulate the EOI message manually by changing the trigger
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* mode to edge and then back to level, with RTE being masked during this.
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*/
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static void __eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
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static void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
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{
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struct irq_pin_list *entry;
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unsigned long flags;
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raw_spin_lock_irqsave(&ioapic_lock, flags);
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for_each_irq_pin(entry, cfg->irq_2_pin) {
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if (mp_ioapics[entry->apic].apicver >= 0x20) {
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/*
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@ -2580,36 +2571,22 @@ static void __eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
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__unmask_and_level_IO_APIC_irq(entry);
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}
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}
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}
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static void eoi_ioapic_irq(struct irq_desc *desc)
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{
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struct irq_cfg *cfg;
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unsigned long flags;
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unsigned int irq;
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irq = desc->irq;
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cfg = get_irq_desc_chip_data(desc);
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raw_spin_lock_irqsave(&ioapic_lock, flags);
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__eoi_ioapic_irq(irq, cfg);
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raw_spin_unlock_irqrestore(&ioapic_lock, flags);
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}
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static void ack_apic_level(unsigned int irq)
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{
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struct irq_desc *desc = irq_to_desc(irq);
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struct irq_cfg *cfg = get_irq_desc_chip_data(desc);
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int i, do_unmask_irq = 0;
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unsigned long v;
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int i;
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struct irq_cfg *cfg;
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int do_unmask_irq = 0;
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irq_complete_move(&desc);
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irq_complete_move(cfg);
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#ifdef CONFIG_GENERIC_PENDING_IRQ
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/* If we are moving the irq we need to mask it */
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if (unlikely(desc->status & IRQ_MOVE_PENDING)) {
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do_unmask_irq = 1;
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mask_IO_APIC_irq_desc(desc);
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mask_ioapic(cfg);
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}
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#endif
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@ -2645,7 +2622,6 @@ static void ack_apic_level(unsigned int irq)
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* we use the above logic (mask+edge followed by unmask+level) from
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* Manfred Spraul to clear the remote IRR.
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*/
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cfg = get_irq_desc_chip_data(desc);
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i = cfg->vector;
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v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
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@ -2665,7 +2641,7 @@ static void ack_apic_level(unsigned int irq)
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if (!(v & (1 << (i & 0x1f)))) {
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atomic_inc(&irq_mis_count);
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eoi_ioapic_irq(desc);
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eoi_ioapic_irq(irq, cfg);
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}
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/* Now we can move and renable the irq */
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@ -2696,10 +2672,9 @@ static void ack_apic_level(unsigned int irq)
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* accurate and is causing problems then it is a hardware bug
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* and you can go talk to the chipset vendor about it.
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*/
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cfg = get_irq_desc_chip_data(desc);
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if (!io_apic_level_ack_pending(cfg))
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move_masked_irq(irq);
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unmask_IO_APIC_irq_desc(desc);
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unmask_ioapic(cfg);
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}
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}
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@ -2711,18 +2686,18 @@ static void ir_ack_apic_edge(unsigned int irq)
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static void ir_ack_apic_level(unsigned int irq)
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{
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struct irq_desc *desc = irq_to_desc(irq);
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struct irq_cfg *cfg = get_irq_chip_data(irq);
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ack_APIC_irq();
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eoi_ioapic_irq(desc);
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eoi_ioapic_irq(irq, cfg);
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}
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#endif /* CONFIG_INTR_REMAP */
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static struct irq_chip ioapic_chip __read_mostly = {
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.name = "IO-APIC",
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.startup = startup_ioapic_irq,
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.mask = mask_IO_APIC_irq,
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.unmask = unmask_IO_APIC_irq,
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.mask = mask_ioapic_irq,
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.unmask = unmask_ioapic_irq,
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.ack = ack_apic_edge,
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.eoi = ack_apic_level,
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#ifdef CONFIG_SMP
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@ -2734,8 +2709,8 @@ static struct irq_chip ioapic_chip __read_mostly = {
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static struct irq_chip ir_ioapic_chip __read_mostly = {
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.name = "IR-IO-APIC",
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.startup = startup_ioapic_irq,
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.mask = mask_IO_APIC_irq,
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.unmask = unmask_IO_APIC_irq,
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.mask = mask_ioapic_irq,
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.unmask = unmask_ioapic_irq,
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#ifdef CONFIG_INTR_REMAP
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.ack = ir_ack_apic_edge,
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.eoi = ir_ack_apic_level,
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@ -2996,7 +2971,7 @@ static inline void __init check_timer(void)
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int idx;
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idx = find_irq_entry(apic1, pin1, mp_INT);
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if (idx != -1 && irq_trigger(idx))
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unmask_IO_APIC_irq_desc(desc);
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unmask_ioapic(cfg);
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}
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if (timer_irq_works()) {
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if (nmi_watchdog == NMI_IO_APIC) {
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