x86/cpu: Add 'unsafe_fsgsbase' to enable CR4.FSGSBASE
This is temporary. It will allow the next few patches to be tested incrementally. Setting unsafe_fsgsbase is a root hole. Don't do it. Signed-off-by: Andy Lutomirski <luto@kernel.org> Signed-off-by: Chang S. Bae <chang.seok.bae@intel.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Sasha Levin <sashal@kernel.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Andi Kleen <ak@linux.intel.com> Reviewed-by: Andy Lutomirski <luto@kernel.org> Link: https://lkml.kernel.org/r/1557309753-24073-4-git-send-email-chang.seok.bae@intel.com Link: https://lkml.kernel.org/r/20200528201402.1708239-3-sashal@kernel.org
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@ -3079,6 +3079,9 @@
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no5lvl [X86-64] Disable 5-level paging mode. Forces
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kernel to use 4-level paging instead.
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unsafe_fsgsbase [X86] Allow FSGSBASE instructions. This will be
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replaced with a nofsgsbase flag.
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no_console_suspend
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[HW] Never suspend the console
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Disable suspending of consoles during suspend and
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@ -441,6 +441,22 @@ static void __init setup_cr_pinning(void)
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static_key_enable(&cr_pinning.key);
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}
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/*
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* Temporary hack: FSGSBASE is unsafe until a few kernel code paths are
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* updated. This allows us to get the kernel ready incrementally.
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*
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* Once all the pieces are in place, these will go away and be replaced with
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* a nofsgsbase chicken flag.
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*/
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static bool unsafe_fsgsbase;
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static __init int setup_unsafe_fsgsbase(char *arg)
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{
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unsafe_fsgsbase = true;
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return 1;
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}
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__setup("unsafe_fsgsbase", setup_unsafe_fsgsbase);
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/*
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* Protection Keys are not available in 32-bit mode.
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*/
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@ -1495,6 +1511,14 @@ static void identify_cpu(struct cpuinfo_x86 *c)
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setup_smap(c);
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setup_umip(c);
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/* Enable FSGSBASE instructions if available. */
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if (cpu_has(c, X86_FEATURE_FSGSBASE)) {
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if (unsafe_fsgsbase)
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cr4_set_bits(X86_CR4_FSGSBASE);
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else
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clear_cpu_cap(c, X86_FEATURE_FSGSBASE);
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}
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/*
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* The vendor-specific functions might have changed features.
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* Now we do "generic changes."
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