i2c: uniphier: add UniPhier FIFO-less I2C driver
Add support for on-chip I2C controller used on old UniPhier SoCs such as PH1-LD4, PH1-sLD8, etc. This adapter is so simple that it has no FIFO in it. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
This commit is contained in:
Masahiro Yamada
Wolfram Sang
Родитель
3eddad96c4
Коммит
dd6fd4a327
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@ -0,0 +1,25 @@
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UniPhier I2C controller (FIFO-less)
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Required properties:
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- compatible: should be "socionext,uniphier-i2c".
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- #address-cells: should be 1.
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- #size-cells: should be 0.
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- reg: offset and length of the register set for the device.
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- interrupts: a single interrupt specifier.
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- clocks: phandle to the input clock.
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Optional properties:
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- clock-frequency: desired I2C bus frequency in Hz. The maximum supported
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value is 400000. Defaults to 100000 if not specified.
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Examples:
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i2c0: i2c@58400000 {
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compatible = "socionext,uniphier-i2c";
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reg = <0x58400000 0x40>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 41 1>;
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clocks = <&i2c_clk>;
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clock-frequency = <100000>;
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};
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@ -1607,6 +1607,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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S: Maintained
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F: arch/arm/boot/dts/uniphier*
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F: arch/arm/mach-uniphier/
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F: drivers/i2c/busses/i2c-uniphier*
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F: drivers/pinctrl/uniphier/
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F: drivers/tty/serial/8250/8250_uniphier.c
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N: uniphier
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@ -902,6 +902,14 @@ config I2C_TEGRA
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If you say yes to this option, support will be included for the
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I2C controller embedded in NVIDIA Tegra SOCs
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config I2C_UNIPHIER
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tristate "UniPhier FIFO-less I2C controller"
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depends on ARCH_UNIPHIER
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help
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If you say yes to this option, support will be included for
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the UniPhier FIFO-less I2C interface embedded in PH1-LD4, PH1-sLD8,
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or older UniPhier SoCs.
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config I2C_VERSATILE
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tristate "ARM Versatile/Realview I2C bus support"
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depends on ARCH_VERSATILE || ARCH_REALVIEW || ARCH_VEXPRESS
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@ -87,6 +87,7 @@ obj-$(CONFIG_I2C_ST) += i2c-st.o
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obj-$(CONFIG_I2C_STU300) += i2c-stu300.o
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obj-$(CONFIG_I2C_SUN6I_P2WI) += i2c-sun6i-p2wi.o
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obj-$(CONFIG_I2C_TEGRA) += i2c-tegra.o
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obj-$(CONFIG_I2C_UNIPHIER) += i2c-uniphier.o
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obj-$(CONFIG_I2C_VERSATILE) += i2c-versatile.o
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obj-$(CONFIG_I2C_WMT) += i2c-wmt.o
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obj-$(CONFIG_I2C_OCTEON) += i2c-octeon.o
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@ -0,0 +1,441 @@
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/*
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* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk.h>
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#include <linux/i2c.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#define UNIPHIER_I2C_DTRM 0x00 /* TX register */
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#define UNIPHIER_I2C_DTRM_IRQEN BIT(11) /* enable interrupt */
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#define UNIPHIER_I2C_DTRM_STA BIT(10) /* start condition */
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#define UNIPHIER_I2C_DTRM_STO BIT(9) /* stop condition */
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#define UNIPHIER_I2C_DTRM_NACK BIT(8) /* do not return ACK */
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#define UNIPHIER_I2C_DTRM_RD BIT(0) /* read transaction */
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#define UNIPHIER_I2C_DREC 0x04 /* RX register */
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#define UNIPHIER_I2C_DREC_MST BIT(14) /* 1 = master, 0 = slave */
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#define UNIPHIER_I2C_DREC_TX BIT(13) /* 1 = transmit, 0 = receive */
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#define UNIPHIER_I2C_DREC_STS BIT(12) /* stop condition detected */
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#define UNIPHIER_I2C_DREC_LRB BIT(11) /* no ACK */
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#define UNIPHIER_I2C_DREC_LAB BIT(9) /* arbitration lost */
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#define UNIPHIER_I2C_DREC_BBN BIT(8) /* bus not busy */
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#define UNIPHIER_I2C_MYAD 0x08 /* slave address */
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#define UNIPHIER_I2C_CLK 0x0c /* clock frequency control */
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#define UNIPHIER_I2C_BRST 0x10 /* bus reset */
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#define UNIPHIER_I2C_BRST_FOEN BIT(1) /* normal operation */
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#define UNIPHIER_I2C_BRST_RSCL BIT(0) /* release SCL */
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#define UNIPHIER_I2C_HOLD 0x14 /* hold time control */
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#define UNIPHIER_I2C_BSTS 0x18 /* bus status monitor */
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#define UNIPHIER_I2C_BSTS_SDA BIT(1) /* readback of SDA line */
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#define UNIPHIER_I2C_BSTS_SCL BIT(0) /* readback of SCL line */
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#define UNIPHIER_I2C_NOISE 0x1c /* noise filter control */
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#define UNIPHIER_I2C_SETUP 0x20 /* setup time control */
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#define UNIPHIER_I2C_DEFAULT_SPEED 100000
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#define UNIPHIER_I2C_MAX_SPEED 400000
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struct uniphier_i2c_priv {
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struct completion comp;
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struct i2c_adapter adap;
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void __iomem *membase;
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struct clk *clk;
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unsigned int busy_cnt;
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};
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static irqreturn_t uniphier_i2c_interrupt(int irq, void *dev_id)
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{
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struct uniphier_i2c_priv *priv = dev_id;
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/*
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* This hardware uses edge triggered interrupt. Do not touch the
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* hardware registers in this handler to make sure to catch the next
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* interrupt edge. Just send a complete signal and return.
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*/
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complete(&priv->comp);
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return IRQ_HANDLED;
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}
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static int uniphier_i2c_xfer_byte(struct i2c_adapter *adap, u32 txdata,
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u32 *rxdatap)
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{
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struct uniphier_i2c_priv *priv = i2c_get_adapdata(adap);
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unsigned long time_left;
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u32 rxdata;
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reinit_completion(&priv->comp);
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txdata |= UNIPHIER_I2C_DTRM_IRQEN;
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dev_dbg(&adap->dev, "write data: 0x%04x\n", txdata);
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writel(txdata, priv->membase + UNIPHIER_I2C_DTRM);
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time_left = wait_for_completion_timeout(&priv->comp, adap->timeout);
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if (unlikely(!time_left)) {
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dev_err(&adap->dev, "transaction timeout\n");
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return -ETIMEDOUT;
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}
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rxdata = readl(priv->membase + UNIPHIER_I2C_DREC);
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dev_dbg(&adap->dev, "read data: 0x%04x\n", rxdata);
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if (rxdatap)
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*rxdatap = rxdata;
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return 0;
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}
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static int uniphier_i2c_send_byte(struct i2c_adapter *adap, u32 txdata)
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{
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u32 rxdata;
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int ret;
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ret = uniphier_i2c_xfer_byte(adap, txdata, &rxdata);
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if (ret)
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return ret;
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if (unlikely(rxdata & UNIPHIER_I2C_DREC_LAB)) {
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dev_dbg(&adap->dev, "arbitration lost\n");
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return -EAGAIN;
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}
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if (unlikely(rxdata & UNIPHIER_I2C_DREC_LRB)) {
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dev_dbg(&adap->dev, "could not get ACK\n");
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return -ENXIO;
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}
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return 0;
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}
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static int uniphier_i2c_tx(struct i2c_adapter *adap, u16 addr, u16 len,
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const u8 *buf)
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{
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int ret;
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dev_dbg(&adap->dev, "start condition\n");
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ret = uniphier_i2c_send_byte(adap, addr << 1 |
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UNIPHIER_I2C_DTRM_STA |
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UNIPHIER_I2C_DTRM_NACK);
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if (ret)
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return ret;
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while (len--) {
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ret = uniphier_i2c_send_byte(adap,
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UNIPHIER_I2C_DTRM_NACK | *buf++);
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if (ret)
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return ret;
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}
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return 0;
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}
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static int uniphier_i2c_rx(struct i2c_adapter *adap, u16 addr, u16 len,
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u8 *buf)
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{
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int ret;
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dev_dbg(&adap->dev, "start condition\n");
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ret = uniphier_i2c_send_byte(adap, addr << 1 |
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UNIPHIER_I2C_DTRM_STA |
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UNIPHIER_I2C_DTRM_NACK |
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UNIPHIER_I2C_DTRM_RD);
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if (ret)
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return ret;
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while (len--) {
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u32 rxdata;
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ret = uniphier_i2c_xfer_byte(adap,
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len ? 0 : UNIPHIER_I2C_DTRM_NACK,
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&rxdata);
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if (ret)
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return ret;
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*buf++ = rxdata;
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}
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return 0;
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}
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static int uniphier_i2c_stop(struct i2c_adapter *adap)
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{
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dev_dbg(&adap->dev, "stop condition\n");
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return uniphier_i2c_send_byte(adap, UNIPHIER_I2C_DTRM_STO |
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UNIPHIER_I2C_DTRM_NACK);
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}
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static int uniphier_i2c_master_xfer_one(struct i2c_adapter *adap,
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struct i2c_msg *msg, bool stop)
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{
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bool is_read = msg->flags & I2C_M_RD;
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bool recovery = false;
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int ret;
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dev_dbg(&adap->dev, "%s: addr=0x%02x, len=%d, stop=%d\n",
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is_read ? "receive" : "transmit", msg->addr, msg->len, stop);
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if (is_read)
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ret = uniphier_i2c_rx(adap, msg->addr, msg->len, msg->buf);
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else
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ret = uniphier_i2c_tx(adap, msg->addr, msg->len, msg->buf);
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if (ret == -EAGAIN) /* could not acquire bus. bail out without STOP */
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return ret;
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if (ret == -ETIMEDOUT) {
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/* This error is fatal. Needs recovery. */
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stop = false;
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recovery = true;
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}
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if (stop) {
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int ret2 = uniphier_i2c_stop(adap);
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if (ret2) {
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/* Failed to issue STOP. The bus needs recovery. */
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recovery = true;
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ret = ret ?: ret2;
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}
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}
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if (recovery)
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i2c_recover_bus(adap);
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return ret;
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}
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static int uniphier_i2c_check_bus_busy(struct i2c_adapter *adap)
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{
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struct uniphier_i2c_priv *priv = i2c_get_adapdata(adap);
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if (!(readl(priv->membase + UNIPHIER_I2C_DREC) &
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UNIPHIER_I2C_DREC_BBN)) {
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if (priv->busy_cnt++ > 3) {
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/*
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* If bus busy continues too long, it is probably
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* in a wrong state. Try bus recovery.
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*/
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i2c_recover_bus(adap);
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priv->busy_cnt = 0;
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}
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return -EAGAIN;
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}
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priv->busy_cnt = 0;
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return 0;
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}
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static int uniphier_i2c_master_xfer(struct i2c_adapter *adap,
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struct i2c_msg *msgs, int num)
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{
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struct i2c_msg *msg, *emsg = msgs + num;
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int ret;
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ret = uniphier_i2c_check_bus_busy(adap);
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if (ret)
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return ret;
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for (msg = msgs; msg < emsg; msg++) {
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/* If next message is read, skip the stop condition */
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bool stop = !(msg + 1 < emsg && msg[1].flags & I2C_M_RD);
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/* but, force it if I2C_M_STOP is set */
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if (msg->flags & I2C_M_STOP)
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stop = true;
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ret = uniphier_i2c_master_xfer_one(adap, msg, stop);
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if (ret)
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return ret;
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}
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return num;
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}
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static u32 uniphier_i2c_functionality(struct i2c_adapter *adap)
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{
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return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
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}
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static const struct i2c_algorithm uniphier_i2c_algo = {
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.master_xfer = uniphier_i2c_master_xfer,
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.functionality = uniphier_i2c_functionality,
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};
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static void uniphier_i2c_reset(struct uniphier_i2c_priv *priv, bool reset_on)
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{
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u32 val = UNIPHIER_I2C_BRST_RSCL;
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val |= reset_on ? 0 : UNIPHIER_I2C_BRST_FOEN;
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writel(val, priv->membase + UNIPHIER_I2C_BRST);
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}
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static int uniphier_i2c_get_scl(struct i2c_adapter *adap)
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{
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struct uniphier_i2c_priv *priv = i2c_get_adapdata(adap);
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return !!(readl(priv->membase + UNIPHIER_I2C_BSTS) &
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UNIPHIER_I2C_BSTS_SCL);
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}
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static void uniphier_i2c_set_scl(struct i2c_adapter *adap, int val)
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{
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struct uniphier_i2c_priv *priv = i2c_get_adapdata(adap);
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writel(val ? UNIPHIER_I2C_BRST_RSCL : 0,
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priv->membase + UNIPHIER_I2C_BRST);
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}
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static int uniphier_i2c_get_sda(struct i2c_adapter *adap)
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{
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struct uniphier_i2c_priv *priv = i2c_get_adapdata(adap);
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return !!(readl(priv->membase + UNIPHIER_I2C_BSTS) &
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UNIPHIER_I2C_BSTS_SDA);
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}
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static void uniphier_i2c_unprepare_recovery(struct i2c_adapter *adap)
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{
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uniphier_i2c_reset(i2c_get_adapdata(adap), false);
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}
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static struct i2c_bus_recovery_info uniphier_i2c_bus_recovery_info = {
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.recover_bus = i2c_generic_scl_recovery,
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.get_scl = uniphier_i2c_get_scl,
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.set_scl = uniphier_i2c_set_scl,
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.get_sda = uniphier_i2c_get_sda,
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.unprepare_recovery = uniphier_i2c_unprepare_recovery,
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};
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static int uniphier_i2c_clk_init(struct device *dev,
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struct uniphier_i2c_priv *priv)
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{
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struct device_node *np = dev->of_node;
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unsigned long clk_rate;
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u32 bus_speed;
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int ret;
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if (of_property_read_u32(np, "clock-frequency", &bus_speed))
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bus_speed = UNIPHIER_I2C_DEFAULT_SPEED;
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if (bus_speed > UNIPHIER_I2C_MAX_SPEED)
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bus_speed = UNIPHIER_I2C_MAX_SPEED;
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/* Get input clk rate through clk driver */
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priv->clk = devm_clk_get(dev, NULL);
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if (IS_ERR(priv->clk)) {
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dev_err(dev, "failed to get clock\n");
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return PTR_ERR(priv->clk);
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}
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ret = clk_prepare_enable(priv->clk);
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if (ret)
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return ret;
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clk_rate = clk_get_rate(priv->clk);
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uniphier_i2c_reset(priv, true);
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writel((clk_rate / bus_speed / 2 << 16) | (clk_rate / bus_speed),
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priv->membase + UNIPHIER_I2C_CLK);
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uniphier_i2c_reset(priv, false);
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return 0;
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}
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static int uniphier_i2c_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct uniphier_i2c_priv *priv;
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struct resource *regs;
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int irq;
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int ret;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
|
||||
return -ENOMEM;
|
||||
|
||||
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
priv->membase = devm_ioremap_resource(dev, regs);
|
||||
if (IS_ERR(priv->membase))
|
||||
return PTR_ERR(priv->membase);
|
||||
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq < 0) {
|
||||
dev_err(dev, "failed to get IRQ number");
|
||||
return irq;
|
||||
}
|
||||
|
||||
init_completion(&priv->comp);
|
||||
priv->adap.owner = THIS_MODULE;
|
||||
priv->adap.algo = &uniphier_i2c_algo;
|
||||
priv->adap.dev.parent = dev;
|
||||
priv->adap.dev.of_node = dev->of_node;
|
||||
strlcpy(priv->adap.name, "UniPhier I2C", sizeof(priv->adap.name));
|
||||
priv->adap.bus_recovery_info = &uniphier_i2c_bus_recovery_info;
|
||||
i2c_set_adapdata(&priv->adap, priv);
|
||||
platform_set_drvdata(pdev, priv);
|
||||
|
||||
ret = uniphier_i2c_clk_init(dev, priv);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = devm_request_irq(dev, irq, uniphier_i2c_interrupt, 0, pdev->name,
|
||||
priv);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to request irq %d\n", irq);
|
||||
goto err;
|
||||
}
|
||||
|
||||
ret = i2c_add_adapter(&priv->adap);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to add I2C adapter\n");
|
||||
goto err;
|
||||
}
|
||||
|
||||
err:
|
||||
if (ret)
|
||||
clk_disable_unprepare(priv->clk);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int uniphier_i2c_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct uniphier_i2c_priv *priv = platform_get_drvdata(pdev);
|
||||
|
||||
i2c_del_adapter(&priv->adap);
|
||||
clk_disable_unprepare(priv->clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id uniphier_i2c_match[] = {
|
||||
{ .compatible = "socionext,uniphier-i2c" },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, uniphier_i2c_match);
|
||||
|
||||
static struct platform_driver uniphier_i2c_drv = {
|
||||
.probe = uniphier_i2c_probe,
|
||||
.remove = uniphier_i2c_remove,
|
||||
.driver = {
|
||||
.name = "uniphier-i2c",
|
||||
.of_match_table = uniphier_i2c_match,
|
||||
},
|
||||
};
|
||||
module_platform_driver(uniphier_i2c_drv);
|
||||
|
||||
MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
|
||||
MODULE_DESCRIPTION("UniPhier I2C bus driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
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