[PATCH] x86_64: Update TSC sync algorithm
The new TSC sync algorithm recently submitted did not work too well. The result was that some MP machines where the TSC came up of the BIOS very unsynchronized and that did not have HPET support were nearly unusable because the time would jump forwards and backwards between CPUs. After a lot of research ;-) and some more prototypes I ended up with just using the one from IA64 which looks best. It has some internal self tuning that should adapt to changing interconnect latencies. It holds up in my tests so far. I believe it was originally written by David Mosberger, I just ported it over to x86-64. See the inline comment for a description. This cleans up the code because it uses smp_call_function for syncing instead of having custom hooks in SMP bootup. Please note that the cycle numbers it outputs are too optimistic because they do not take into account the latency of WRMSR and RDTSC, which can be hundreds of cycles. It seems to be able to sync a dual Opteron to 200-300 cycles, which is probably good enough. There is a timing window during AP bootup where interrupts can see inconsistent time before the TSC is synced. It is hard to avoid unfortunately because we can only do the TSC sync after some setup, and we need to enable interrupts before that. I just ignored it for now. Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
This commit is contained in:
Andi Kleen
Linus Torvalds
Родитель
93ef70a217
Коммит
dda50e716d
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@ -125,97 +125,211 @@ static void __cpuinit smp_store_cpu_info(int id)
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*c = boot_cpu_data;
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identify_cpu(c);
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print_cpu_info(c);
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}
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/*
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* Synchronize TSCs of CPUs
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* New Funky TSC sync algorithm borrowed from IA64.
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* Main advantage is that it doesn't reset the TSCs fully and
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* in general looks more robust and it works better than my earlier
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* attempts. I believe it was written by David Mosberger. Some minor
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* adjustments for x86-64 by me -AK
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*
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* This new algorithm is less accurate than the old "zero TSCs"
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* one, but we cannot zero TSCs anymore in the new hotplug CPU
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* model.
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* Original comment reproduced below.
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*
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* Synchronize TSC of the current (slave) CPU with the TSC of the
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* MASTER CPU (normally the time-keeper CPU). We use a closed loop to
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* eliminate the possibility of unaccounted-for errors (such as
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* getting a machine check in the middle of a calibration step). The
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* basic idea is for the slave to ask the master what itc value it has
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* and to read its own itc before and after the master responds. Each
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* iteration gives us three timestamps:
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*
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* slave master
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*
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* t0 ---\
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* ---\
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* --->
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* tm
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* /---
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* /---
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* t1 <---
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*
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*
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* The goal is to adjust the slave's TSC such that tm falls exactly
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* half-way between t0 and t1. If we achieve this, the clocks are
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* synchronized provided the interconnect between the slave and the
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* master is symmetric. Even if the interconnect were asymmetric, we
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* would still know that the synchronization error is smaller than the
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* roundtrip latency (t0 - t1).
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*
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* When the interconnect is quiet and symmetric, this lets us
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* synchronize the TSC to within one or two cycles. However, we can
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* only *guarantee* that the synchronization is accurate to within a
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* round-trip time, which is typically in the range of several hundred
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* cycles (e.g., ~500 cycles). In practice, this means that the TSCs
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* are usually almost perfectly synchronized, but we shouldn't assume
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* that the accuracy is much better than half a micro second or so.
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*
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* [there are other errors like the latency of RDTSC and of the
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* WRMSR. These can also account to hundreds of cycles. So it's
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* probably worse. It claims 153 cycles error on a dual Opteron,
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* but I suspect the numbers are actually somewhat worse -AK]
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*/
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static atomic_t __cpuinitdata tsc_flag;
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#define MASTER 0
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#define SLAVE (SMP_CACHE_BYTES/8)
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/* Intentionally don't use cpu_relax() while TSC synchronization
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because we don't want to go into funky power save modi or cause
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hypervisors to schedule us away. Going to sleep would likely affect
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latency and low latency is the primary objective here. -AK */
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#define no_cpu_relax() barrier()
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static __cpuinitdata DEFINE_SPINLOCK(tsc_sync_lock);
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static unsigned long long __cpuinitdata bp_tsc, ap_tsc;
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static volatile __cpuinitdata unsigned long go[SLAVE + 1];
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static int notscsync __cpuinitdata;
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#define NR_LOOPS 5
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#undef DEBUG_TSC_SYNC
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static void __cpuinit sync_tsc_bp_init(int init)
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#define NUM_ROUNDS 64 /* magic value */
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#define NUM_ITERS 5 /* likewise */
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/* Callback on boot CPU */
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static __cpuinit void sync_master(void *arg)
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{
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if (init)
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_raw_spin_lock(&tsc_sync_lock);
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else
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_raw_spin_unlock(&tsc_sync_lock);
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atomic_set(&tsc_flag, 0);
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}
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unsigned long flags, i;
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/*
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* Synchronize TSC on AP with BP.
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*/
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static void __cpuinit __sync_tsc_ap(void)
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{
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if (!cpu_has_tsc)
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return;
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Dprintk("AP %d syncing TSC\n", smp_processor_id());
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while (atomic_read(&tsc_flag) != 0)
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cpu_relax();
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atomic_inc(&tsc_flag);
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mb();
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_raw_spin_lock(&tsc_sync_lock);
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wrmsrl(MSR_IA32_TSC, bp_tsc);
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_raw_spin_unlock(&tsc_sync_lock);
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rdtscll(ap_tsc);
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mb();
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atomic_inc(&tsc_flag);
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mb();
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}
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static void __cpuinit sync_tsc_ap(void)
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{
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int i;
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for (i = 0; i < NR_LOOPS; i++)
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__sync_tsc_ap();
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}
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/*
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* Synchronize TSC from BP to AP.
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*/
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static void __cpuinit __sync_tsc_bp(int cpu)
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{
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if (!cpu_has_tsc)
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if (smp_processor_id() != boot_cpu_id)
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return;
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/* Wait for AP */
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while (atomic_read(&tsc_flag) == 0)
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cpu_relax();
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/* Save BPs TSC */
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sync_core();
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rdtscll(bp_tsc);
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/* Don't do the sync core here to avoid too much latency. */
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mb();
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/* Start the AP */
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_raw_spin_unlock(&tsc_sync_lock);
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/* Wait for AP again */
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while (atomic_read(&tsc_flag) < 2)
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cpu_relax();
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rdtscl(bp_tsc);
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barrier();
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}
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go[MASTER] = 0;
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static void __cpuinit sync_tsc_bp(int cpu)
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{
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int i;
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for (i = 0; i < NR_LOOPS - 1; i++) {
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__sync_tsc_bp(cpu);
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sync_tsc_bp_init(1);
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local_irq_save(flags);
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{
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for (i = 0; i < NUM_ROUNDS*NUM_ITERS; ++i) {
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while (!go[MASTER])
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no_cpu_relax();
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go[MASTER] = 0;
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rdtscll(go[SLAVE]);
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}
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__sync_tsc_bp(cpu);
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printk(KERN_INFO "Synced TSC of CPU %d difference %Ld\n",
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cpu, ap_tsc - bp_tsc);
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}
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local_irq_restore(flags);
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}
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/*
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* Return the number of cycles by which our tsc differs from the tsc
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* on the master (time-keeper) CPU. A positive number indicates our
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* tsc is ahead of the master, negative that it is behind.
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*/
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static inline long
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get_delta(long *rt, long *master)
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{
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unsigned long best_t0 = 0, best_t1 = ~0UL, best_tm = 0;
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unsigned long tcenter, t0, t1, tm;
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int i;
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for (i = 0; i < NUM_ITERS; ++i) {
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rdtscll(t0);
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go[MASTER] = 1;
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while (!(tm = go[SLAVE]))
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no_cpu_relax();
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go[SLAVE] = 0;
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rdtscll(t1);
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if (t1 - t0 < best_t1 - best_t0)
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best_t0 = t0, best_t1 = t1, best_tm = tm;
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}
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*rt = best_t1 - best_t0;
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*master = best_tm - best_t0;
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/* average best_t0 and best_t1 without overflow: */
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tcenter = (best_t0/2 + best_t1/2);
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if (best_t0 % 2 + best_t1 % 2 == 2)
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++tcenter;
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return tcenter - best_tm;
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}
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static __cpuinit void sync_tsc(void)
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{
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int i, done = 0;
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long delta, adj, adjust_latency = 0;
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unsigned long flags, rt, master_time_stamp, bound;
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#if DEBUG_TSC_SYNC
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static struct syncdebug {
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long rt; /* roundtrip time */
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long master; /* master's timestamp */
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long diff; /* difference between midpoint and master's timestamp */
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long lat; /* estimate of tsc adjustment latency */
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} t[NUM_ROUNDS] __cpuinitdata;
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#endif
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go[MASTER] = 1;
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smp_call_function(sync_master, NULL, 1, 0);
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while (go[MASTER]) /* wait for master to be ready */
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no_cpu_relax();
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spin_lock_irqsave(&tsc_sync_lock, flags);
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{
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for (i = 0; i < NUM_ROUNDS; ++i) {
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delta = get_delta(&rt, &master_time_stamp);
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if (delta == 0) {
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done = 1; /* let's lock on to this... */
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bound = rt;
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}
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if (!done) {
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unsigned long t;
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if (i > 0) {
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adjust_latency += -delta;
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adj = -delta + adjust_latency/4;
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} else
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adj = -delta;
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rdtscll(t);
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wrmsrl(MSR_IA32_TSC, t + adj);
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}
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#if DEBUG_TSC_SYNC
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t[i].rt = rt;
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t[i].master = master_time_stamp;
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t[i].diff = delta;
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t[i].lat = adjust_latency/4;
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#endif
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}
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}
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spin_unlock_irqrestore(&tsc_sync_lock, flags);
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#if DEBUG_TSC_SYNC
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for (i = 0; i < NUM_ROUNDS; ++i)
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printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n",
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t[i].rt, t[i].master, t[i].diff, t[i].lat);
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#endif
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printk(KERN_INFO
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"CPU %d: synchronized TSC with CPU %u (last diff %ld cycles, "
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"maxerr %lu cycles)\n",
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smp_processor_id(), boot_cpu_id, delta, rt);
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}
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static void __cpuinit tsc_sync_wait(void)
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{
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if (notscsync || !cpu_has_tsc)
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return;
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printk(KERN_INFO "CPU %d: Syncing TSC to CPU %u.\n", smp_processor_id(),
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boot_cpu_id);
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sync_tsc();
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}
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static __init int notscsync_setup(char *s)
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{
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notscsync = 1;
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return 0;
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}
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__setup("notscsync", notscsync_setup);
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static atomic_t init_deasserted __cpuinitdata;
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/*
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@ -315,11 +429,6 @@ void __cpuinit start_secondary(void)
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cpu_init();
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smp_callin();
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/*
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* Synchronize the TSC with the BP
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*/
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sync_tsc_ap();
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/* otherwise gcc will move up the smp_processor_id before the cpu_init */
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barrier();
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@ -334,7 +443,6 @@ void __cpuinit start_secondary(void)
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enable_8259A_irq(0);
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}
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enable_APIC_timer();
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/*
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@ -343,6 +451,11 @@ void __cpuinit start_secondary(void)
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cpu_set(smp_processor_id(), cpu_online_map);
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mb();
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/* Wait for TSC sync to not schedule things before.
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We still process interrupts, which could see an inconsistent
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time in that window unfortunately. */
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tsc_sync_wait();
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cpu_idle();
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}
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@ -600,8 +713,6 @@ static int __cpuinit do_boot_cpu(int cpu, int apicid)
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if (cpu_isset(cpu, cpu_callin_map)) {
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/* number CPUs logically, starting from 1 (BSP is 0) */
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Dprintk("OK.\n");
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print_cpu_info(&cpu_data[cpu]);
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Dprintk("CPU has booted.\n");
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} else {
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boot_error = 1;
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@ -889,18 +1000,14 @@ int __cpuinit __cpu_up(unsigned int cpu)
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printk("__cpu_up: bad cpu %d\n", cpu);
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return -EINVAL;
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}
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sync_tsc_bp_init(1);
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/* Boot it! */
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err = do_boot_cpu(cpu, apicid);
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if (err < 0) {
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sync_tsc_bp_init(0);
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Dprintk("do_boot_cpu failed %d\n", err);
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return err;
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}
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sync_tsc_bp(cpu);
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/* Unleash the CPU! */
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Dprintk("waiting for cpu %d\n", cpu);
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