soundwire: qcom: update register read/write routine
In the existing code every soundwire register read and register write are kinda blocked. Each of these are using a special command id that generates interrupt after it successfully finishes. This is really overhead, limiting and not really necessary unless we are doing something special. We can simply read/write the fifo that should also give exactly what we need! This will also allow to read/write registers in interrupt context, which was not possible with the special command approach. With previous approach number of interrupts generated after enumeration are around 130: $ cat /proc/interrupts | grep soundwire 21: 130 0 0 0 0 0 0 0 GICv3 234 Edge soundwire after this patch they are just 3 interrupts $ cat /proc/interrupts | grep soundwire 21: 3 0 0 0 0 0 0 0 GICv3 234 Edge soundwire This has significantly not only reduced interrupting CPU during enumeration but also during streaming! Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Link: https://lore.kernel.org/r/20210330144719.13284-6-srinivas.kandagatla@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Srinivas Kandagatla
Vinod Koul
Родитель
a866a04902
Коммит
ddea6cf7b6
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@ -38,11 +38,13 @@
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#define SWRM_CMD_FIFO_WR_CMD 0x300
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#define SWRM_CMD_FIFO_RD_CMD 0x304
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#define SWRM_CMD_FIFO_CMD 0x308
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#define SWRM_CMD_FIFO_FLUSH 0x1
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#define SWRM_CMD_FIFO_STATUS 0x30C
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#define SWRM_CMD_FIFO_CFG_ADDR 0x314
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#define SWRM_CONTINUE_EXEC_ON_CMD_IGNORE BIT(31)
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#define SWRM_RD_WR_CMD_RETRIES 0x7
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#define SWRM_CMD_FIFO_RD_FIFO_ADDR 0x318
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#define SWRM_RD_FIFO_CMD_ID_MASK GENMASK(11, 8)
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#define SWRM_ENUMERATOR_CFG_ADDR 0x500
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#define SWRM_MCP_FRAME_CTRL_BANK_ADDR(m) (0x101C + 0x40 * (m))
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#define SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK GENMASK(2, 0)
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@ -78,13 +80,16 @@
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#define SWRM_SPECIAL_CMD_ID 0xF
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#define MAX_FREQ_NUM 1
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#define TIMEOUT_MS (2 * HZ)
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#define QCOM_SWRM_MAX_RD_LEN 0xf
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#define QCOM_SWRM_MAX_RD_LEN 0x1
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#define QCOM_SDW_MAX_PORTS 14
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#define DEFAULT_CLK_FREQ 9600000
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#define SWRM_MAX_DAIS 0xF
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#define SWR_INVALID_PARAM 0xFF
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#define SWR_HSTOP_MAX_VAL 0xF
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#define SWR_HSTART_MIN_VAL 0x0
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#define SWR_BROADCAST_CMD_ID 0x0F
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#define SWR_MAX_CMD_ID 14
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#define MAX_FIFO_RD_RETRY 3
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struct qcom_swrm_port_config {
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u8 si;
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@ -103,10 +108,8 @@ struct qcom_swrm_ctrl {
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struct device *dev;
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struct regmap *regmap;
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void __iomem *mmio;
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struct completion *comp;
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struct completion broadcast;
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struct work_struct slave_work;
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/* read/write lock */
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spinlock_t comp_lock;
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/* Port alloc/free lock */
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struct mutex port_lock;
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struct clk *hclk;
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@ -120,6 +123,8 @@ struct qcom_swrm_ctrl {
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int rows_index;
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unsigned long dout_port_mask;
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unsigned long din_port_mask;
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u8 rcmd_id;
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u8 wcmd_id;
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struct qcom_swrm_port_config pconfig[QCOM_SDW_MAX_PORTS];
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struct sdw_stream_runtime *sruntime[SWRM_MAX_DAIS];
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enum sdw_slave_status status[SDW_MAX_DEVICES];
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@ -198,77 +203,106 @@ static int qcom_swrm_cpu_reg_write(struct qcom_swrm_ctrl *ctrl, int reg,
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return SDW_CMD_OK;
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}
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static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl *ctrl, u8 cmd_data,
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static u32 swrm_get_packed_reg_val(u8 *cmd_id, u8 cmd_data,
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u8 dev_addr, u16 reg_addr)
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{
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DECLARE_COMPLETION_ONSTACK(comp);
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unsigned long flags;
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u32 val;
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int ret;
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u8 id = *cmd_id;
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spin_lock_irqsave(&ctrl->comp_lock, flags);
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ctrl->comp = ∁
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spin_unlock_irqrestore(&ctrl->comp_lock, flags);
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val = SWRM_REG_VAL_PACK(cmd_data, dev_addr,
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SWRM_SPECIAL_CMD_ID, reg_addr);
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ret = ctrl->reg_write(ctrl, SWRM_CMD_FIFO_WR_CMD, val);
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if (ret)
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goto err;
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if (id != SWR_BROADCAST_CMD_ID) {
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if (id < SWR_MAX_CMD_ID)
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id += 1;
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else
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id = 0;
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*cmd_id = id;
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}
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val = SWRM_REG_VAL_PACK(cmd_data, dev_addr, id, reg_addr);
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ret = wait_for_completion_timeout(ctrl->comp,
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return val;
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}
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static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl *swrm, u8 cmd_data,
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u8 dev_addr, u16 reg_addr)
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{
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u32 val;
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int ret = 0;
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u8 cmd_id = 0x0;
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if (dev_addr == SDW_BROADCAST_DEV_NUM) {
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cmd_id = SWR_BROADCAST_CMD_ID;
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val = swrm_get_packed_reg_val(&cmd_id, cmd_data,
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dev_addr, reg_addr);
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} else {
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val = swrm_get_packed_reg_val(&swrm->wcmd_id, cmd_data,
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dev_addr, reg_addr);
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}
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/* Its assumed that write is okay as we do not get any status back */
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swrm->reg_write(swrm, SWRM_CMD_FIFO_WR_CMD, val);
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/* version 1.3 or less */
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if (swrm->version <= 0x01030000)
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usleep_range(150, 155);
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if (cmd_id == SWR_BROADCAST_CMD_ID) {
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/*
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* sleep for 10ms for MSM soundwire variant to allow broadcast
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* command to complete.
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*/
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ret = wait_for_completion_timeout(&swrm->broadcast,
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msecs_to_jiffies(TIMEOUT_MS));
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if (!ret)
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ret = SDW_CMD_IGNORED;
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else
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ret = SDW_CMD_OK;
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err:
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spin_lock_irqsave(&ctrl->comp_lock, flags);
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ctrl->comp = NULL;
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spin_unlock_irqrestore(&ctrl->comp_lock, flags);
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return ret;
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}
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static int qcom_swrm_cmd_fifo_rd_cmd(struct qcom_swrm_ctrl *ctrl,
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u8 dev_addr, u16 reg_addr,
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u32 len, u8 *rval)
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{
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int i, ret;
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u32 val;
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DECLARE_COMPLETION_ONSTACK(comp);
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unsigned long flags;
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spin_lock_irqsave(&ctrl->comp_lock, flags);
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ctrl->comp = ∁
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spin_unlock_irqrestore(&ctrl->comp_lock, flags);
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val = SWRM_REG_VAL_PACK(len, dev_addr, SWRM_SPECIAL_CMD_ID, reg_addr);
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ret = ctrl->reg_write(ctrl, SWRM_CMD_FIFO_RD_CMD, val);
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if (ret)
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goto err;
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ret = wait_for_completion_timeout(ctrl->comp,
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msecs_to_jiffies(TIMEOUT_MS));
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if (!ret) {
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ret = SDW_CMD_IGNORED;
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goto err;
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} else {
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ret = SDW_CMD_OK;
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}
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return ret;
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}
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for (i = 0; i < len; i++) {
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ctrl->reg_read(ctrl, SWRM_CMD_FIFO_RD_FIFO_ADDR, &val);
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rval[i] = val & 0xFF;
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static int qcom_swrm_cmd_fifo_rd_cmd(struct qcom_swrm_ctrl *swrm,
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u8 dev_addr, u16 reg_addr,
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u32 len, u8 *rval)
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{
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u32 cmd_data, cmd_id, val, retry_attempt = 0;
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val = swrm_get_packed_reg_val(&swrm->rcmd_id, len, dev_addr, reg_addr);
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/* wait for FIFO RD to complete to avoid overflow */
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usleep_range(100, 105);
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swrm->reg_write(swrm, SWRM_CMD_FIFO_RD_CMD, val);
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/* wait for FIFO RD CMD complete to avoid overflow */
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usleep_range(250, 255);
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do {
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swrm->reg_read(swrm, SWRM_CMD_FIFO_RD_FIFO_ADDR, &cmd_data);
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rval[0] = cmd_data & 0xFF;
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cmd_id = FIELD_GET(SWRM_RD_FIFO_CMD_ID_MASK, cmd_data);
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if (cmd_id != swrm->rcmd_id) {
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if (retry_attempt < (MAX_FIFO_RD_RETRY - 1)) {
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/* wait 500 us before retry on fifo read failure */
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usleep_range(500, 505);
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swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD,
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SWRM_CMD_FIFO_FLUSH);
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swrm->reg_write(swrm, SWRM_CMD_FIFO_RD_CMD, val);
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}
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retry_attempt++;
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} else {
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return SDW_CMD_OK;
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}
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err:
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spin_lock_irqsave(&ctrl->comp_lock, flags);
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ctrl->comp = NULL;
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spin_unlock_irqrestore(&ctrl->comp_lock, flags);
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} while (retry_attempt < MAX_FIFO_RD_RETRY);
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return ret;
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dev_err(swrm->dev, "failed to read fifo: reg: 0x%x, rcmd_id: 0x%x,\
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dev_num: 0x%x, cmd_data: 0x%x\n",
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reg_addr, swrm->rcmd_id, dev_addr, cmd_data);
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return SDW_CMD_IGNORED;
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}
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static void qcom_swrm_get_device_status(struct qcom_swrm_ctrl *ctrl)
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@ -291,7 +325,6 @@ static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id)
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{
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struct qcom_swrm_ctrl *ctrl = dev_id;
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u32 sts, value;
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unsigned long flags;
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ctrl->reg_read(ctrl, SWRM_INTERRUPT_STATUS, &sts);
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@ -304,8 +337,10 @@ static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id)
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}
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if ((sts & SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED) ||
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sts & SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS)
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schedule_work(&ctrl->slave_work);
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sts & SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS) {
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qcom_swrm_get_device_status(ctrl);
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sdw_handle_slave_status(&ctrl->bus, ctrl->status);
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}
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/**
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* clear the interrupt before complete() is called, as complete can
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@ -314,15 +349,12 @@ static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id)
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*/
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ctrl->reg_write(ctrl, SWRM_INTERRUPT_CLEAR, sts);
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if (sts & SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED) {
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spin_lock_irqsave(&ctrl->comp_lock, flags);
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if (ctrl->comp)
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complete(ctrl->comp);
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spin_unlock_irqrestore(&ctrl->comp_lock, flags);
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}
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if (sts & SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED)
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complete(&ctrl->broadcast);
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return IRQ_HANDLED;
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}
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static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl)
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{
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u32 val;
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@ -562,16 +594,6 @@ static u32 qcom_swrm_freq_tbl[MAX_FREQ_NUM] = {
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DEFAULT_CLK_FREQ,
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};
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static void qcom_swrm_slave_wq(struct work_struct *work)
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{
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struct qcom_swrm_ctrl *ctrl =
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container_of(work, struct qcom_swrm_ctrl, slave_work);
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qcom_swrm_get_device_status(ctrl);
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sdw_handle_slave_status(&ctrl->bus, ctrl->status);
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}
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static void qcom_swrm_stream_free_ports(struct qcom_swrm_ctrl *ctrl,
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struct sdw_stream_runtime *stream)
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{
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@ -930,9 +952,8 @@ static int qcom_swrm_probe(struct platform_device *pdev)
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ctrl->dev = dev;
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dev_set_drvdata(&pdev->dev, ctrl);
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spin_lock_init(&ctrl->comp_lock);
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mutex_init(&ctrl->port_lock);
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INIT_WORK(&ctrl->slave_work, qcom_swrm_slave_wq);
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init_completion(&ctrl->broadcast);
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ctrl->bus.ops = &qcom_swrm_ops;
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ctrl->bus.port_ops = &qcom_swrm_port_ops;
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