drm/i915: extract compute_dpll from ironlake_crtc_mode_set
Too many lines just to compute the value of a single variable, so move this to its own function. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Paulo Zanoni
Daniel Vetter
Родитель
f48d8f235a
Коммит
de13a2e3f8
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@ -4783,6 +4783,109 @@ static void ironlake_set_m_n(struct drm_crtc *crtc,
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I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
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}
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static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
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struct drm_display_mode *adjusted_mode,
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intel_clock_t *clock, u32 fp)
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{
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struct drm_crtc *crtc = &intel_crtc->base;
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_encoder *intel_encoder;
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uint32_t dpll;
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int factor, pixel_multiplier, num_connectors = 0;
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bool is_lvds = false, is_sdvo = false, is_tv = false;
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bool is_dp = false, is_cpu_edp = false;
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for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
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switch (intel_encoder->type) {
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case INTEL_OUTPUT_LVDS:
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is_lvds = true;
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break;
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case INTEL_OUTPUT_SDVO:
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case INTEL_OUTPUT_HDMI:
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is_sdvo = true;
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if (intel_encoder->needs_tv_clock)
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is_tv = true;
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break;
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case INTEL_OUTPUT_TVOUT:
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is_tv = true;
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break;
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case INTEL_OUTPUT_DISPLAYPORT:
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is_dp = true;
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break;
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case INTEL_OUTPUT_EDP:
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is_dp = true;
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if (!intel_encoder_is_pch_edp(&intel_encoder->base))
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is_cpu_edp = true;
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break;
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}
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num_connectors++;
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}
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/* Enable autotuning of the PLL clock (if permissible) */
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factor = 21;
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if (is_lvds) {
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if ((intel_panel_use_ssc(dev_priv) &&
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dev_priv->lvds_ssc_freq == 100) ||
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(I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
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factor = 25;
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} else if (is_sdvo && is_tv)
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factor = 20;
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if (clock->m < factor * clock->n)
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fp |= FP_CB_TUNE;
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dpll = 0;
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if (is_lvds)
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dpll |= DPLLB_MODE_LVDS;
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else
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dpll |= DPLLB_MODE_DAC_SERIAL;
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if (is_sdvo) {
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pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
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if (pixel_multiplier > 1) {
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dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
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}
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dpll |= DPLL_DVO_HIGH_SPEED;
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}
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if (is_dp && !is_cpu_edp)
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dpll |= DPLL_DVO_HIGH_SPEED;
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/* compute bitmask from p1 value */
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dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
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/* also FPA1 */
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dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
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switch (clock->p2) {
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case 5:
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dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
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break;
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case 7:
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dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
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break;
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case 10:
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dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
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break;
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case 14:
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dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
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break;
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}
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if (is_sdvo && is_tv)
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dpll |= PLL_REF_INPUT_TVCLKINBC;
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else if (is_tv)
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/* XXX: just matching BIOS for now */
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/* dpll |= PLL_REF_INPUT_TVCLKINBC; */
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dpll |= 3;
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else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
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dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
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else
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dpll |= PLL_REF_INPUT_DREFCLK;
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return dpll;
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}
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static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
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struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode,
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@ -4801,7 +4904,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
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bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
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struct intel_encoder *encoder;
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u32 temp;
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int ret, factor;
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int ret;
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bool dither;
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bool is_cpu_edp = false, is_pch_edp = false;
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@ -4857,65 +4960,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
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fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
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reduced_clock.m2;
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/* Enable autotuning of the PLL clock (if permissible) */
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factor = 21;
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if (is_lvds) {
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if ((intel_panel_use_ssc(dev_priv) &&
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dev_priv->lvds_ssc_freq == 100) ||
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(I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
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factor = 25;
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} else if (is_sdvo && is_tv)
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factor = 20;
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if (clock.m < factor * clock.n)
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fp |= FP_CB_TUNE;
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dpll = 0;
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if (is_lvds)
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dpll |= DPLLB_MODE_LVDS;
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else
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dpll |= DPLLB_MODE_DAC_SERIAL;
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if (is_sdvo) {
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int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
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if (pixel_multiplier > 1) {
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dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
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}
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dpll |= DPLL_DVO_HIGH_SPEED;
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}
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if (is_dp && !is_cpu_edp)
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dpll |= DPLL_DVO_HIGH_SPEED;
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/* compute bitmask from p1 value */
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dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
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/* also FPA1 */
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dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
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switch (clock.p2) {
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case 5:
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dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
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break;
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case 7:
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dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
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break;
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case 10:
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dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
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break;
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case 14:
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dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
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break;
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}
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if (is_sdvo && is_tv)
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dpll |= PLL_REF_INPUT_TVCLKINBC;
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else if (is_tv)
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/* XXX: just matching BIOS for now */
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/* dpll |= PLL_REF_INPUT_TVCLKINBC; */
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dpll |= 3;
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else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
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dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
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else
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dpll |= PLL_REF_INPUT_DREFCLK;
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dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
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DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
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drm_mode_debug_printmodeline(mode);
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