staging: sm750fb: Edit CamelCase in local variables
Edit CamelCase in local variables across 4 files: - sm750fb/ddk750_chip.c - sm750fb/ddk750_chip.h - sm750fb/ddk750_dvi.c - sm750fb/ddk750_sii164.c to comply with the coding style. Also edit associated comments accordingly. Issue found with Checkpatch. Signed-off-by: Nishka Dasgupta <nishka.dasgupta@yahoo.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Nishka Dasgupta
Greg Kroah-Hartman
Родитель
256ab3efbe
Коммит
de5e4aea88
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@ -15,14 +15,14 @@ enum logical_chip_type sm750_get_chip_type(void)
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return chip;
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}
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void sm750_set_chip_type(unsigned short devId, u8 revId)
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void sm750_set_chip_type(unsigned short dev_id, u8 rev_id)
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{
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if (devId == 0x718) {
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if (dev_id == 0x718) {
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chip = SM718;
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} else if (devId == 0x750) {
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} else if (dev_id == 0x750) {
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chip = SM750;
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/* SM750 and SM750LE are different in their revision ID only. */
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if (revId == SM750LE_REVISION_ID) {
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if (rev_id == SM750LE_REVISION_ID) {
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chip = SM750LE;
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pr_info("found sm750le\n");
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}
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@ -321,7 +321,7 @@ unsigned int sm750_calc_pll_value(unsigned int request_orig,
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int mini_diff;
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unsigned int RN, quo, rem, fl_quo;
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unsigned int input, request;
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unsigned int tmpClock, ret;
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unsigned int tmp_clock, ret;
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const int max_OD = 3;
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int max_d = 6;
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@ -365,8 +365,8 @@ unsigned int sm750_calc_pll_value(unsigned int request_orig,
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if (M < 256 && M > 0) {
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unsigned int diff;
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tmpClock = pll->inputFreq * M / N / X;
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diff = abs(tmpClock - request_orig);
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tmp_clock = pll->inputFreq * M / N / X;
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diff = abs(tmp_clock - request_orig);
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if (diff < mini_diff) {
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pll->M = M;
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pll->N = N;
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@ -375,7 +375,7 @@ unsigned int sm750_calc_pll_value(unsigned int request_orig,
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pll->POD = d - max_OD;
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pll->OD = d - pll->POD;
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mini_diff = diff;
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ret = tmpClock;
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ret = tmp_clock;
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}
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}
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}
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@ -93,7 +93,7 @@ struct initchip_param {
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};
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enum logical_chip_type sm750_get_chip_type(void);
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void sm750_set_chip_type(unsigned short devId, u8 revId);
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void sm750_set_chip_type(unsigned short dev_id, u8 rev_id);
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unsigned int sm750_calc_pll_value(unsigned int request, struct pll_value *pll);
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unsigned int sm750_format_pll_reg(struct pll_value *pPLL);
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unsigned int ddk750_get_vm_size(void);
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@ -30,31 +30,31 @@ static struct dvi_ctrl_device g_dcftSupportedDviController[] = {
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#endif
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};
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int dviInit(unsigned char edgeSelect,
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unsigned char busSelect,
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unsigned char dualEdgeClkSelect,
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unsigned char hsyncEnable,
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unsigned char vsyncEnable,
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unsigned char deskewEnable,
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unsigned char deskewSetting,
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unsigned char continuousSyncEnable,
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unsigned char pllFilterEnable,
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unsigned char pllFilterValue)
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int dviInit(unsigned char edge_select,
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unsigned char bus_select,
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unsigned char dual_edge_clk_select,
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unsigned char hsync_enable,
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unsigned char vsync_enable,
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unsigned char deskew_enable,
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unsigned char deskew_setting,
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unsigned char continuous_sync_enable,
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unsigned char pll_filter_enable,
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unsigned char pll_filter_value)
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{
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struct dvi_ctrl_device *pCurrentDviCtrl;
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pCurrentDviCtrl = g_dcftSupportedDviController;
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if (pCurrentDviCtrl->pfnInit) {
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return pCurrentDviCtrl->pfnInit(edgeSelect,
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busSelect,
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dualEdgeClkSelect,
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hsyncEnable,
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vsyncEnable,
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deskewEnable,
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deskewSetting,
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continuousSyncEnable,
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pllFilterEnable,
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pllFilterValue);
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return pCurrentDviCtrl->pfnInit(edge_select,
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bus_select,
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dual_edge_clk_select,
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hsync_enable,
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vsync_enable,
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deskew_enable,
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deskew_setting,
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continuous_sync_enable,
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pll_filter_enable,
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pll_filter_value);
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}
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return -1; /* error */
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}
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@ -69,58 +69,58 @@ unsigned short sii164GetDeviceID(void)
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* This function initialize and detect the DVI controller chip.
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*
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* Input:
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* edgeSelect - Edge Select:
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* 0 = Input data is falling edge latched (falling edge
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* latched first in dual edge mode)
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* 1 = Input data is rising edge latched (rising edge
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* latched first in dual edge mode)
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* busSelect - Input Bus Select:
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* 0 = Input data bus is 12-bits wide
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* 1 = Input data bus is 24-bits wide
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* dualEdgeClkSelect - Dual Edge Clock Select
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* 0 = Input data is single edge latched
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* 1 = Input data is dual edge latched
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* hsyncEnable - Horizontal Sync Enable:
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* 0 = HSYNC input is transmitted as fixed LOW
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* 1 = HSYNC input is transmitted as is
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* vsyncEnable - Vertical Sync Enable:
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* 0 = VSYNC input is transmitted as fixed LOW
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* 1 = VSYNC input is transmitted as is
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* deskewEnable - De-skewing Enable:
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* 0 = De-skew disabled
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* 1 = De-skew enabled
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* deskewSetting - De-skewing Setting (increment of 260psec)
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* 0 = 1 step --> minimum setup / maximum hold
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* 1 = 2 step
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* 2 = 3 step
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* 3 = 4 step
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* 4 = 5 step
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* 5 = 6 step
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* 6 = 7 step
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* 7 = 8 step --> maximum setup / minimum hold
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* continuousSyncEnable- SYNC Continuous:
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* 0 = Disable
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* 1 = Enable
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* pllFilterEnable - PLL Filter Enable
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* 0 = Disable PLL Filter
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* 1 = Enable PLL Filter
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* pllFilterValue - PLL Filter characteristics:
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* 0~7 (recommended value is 4)
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* edge_select - Edge Select:
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* 0 = Input data is falling edge latched (falling
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* edge latched first in dual edge mode)
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* 1 = Input data is rising edge latched (rising
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* edge latched first in dual edge mode)
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* bus_select - Input Bus Select:
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* 0 = Input data bus is 12-bits wide
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* 1 = Input data bus is 24-bits wide
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* dual_edge_clk_select - Dual Edge Clock Select
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* 0 = Input data is single edge latched
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* 1 = Input data is dual edge latched
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* hsync_enable - Horizontal Sync Enable:
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* 0 = HSYNC input is transmitted as fixed LOW
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* 1 = HSYNC input is transmitted as is
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* vsync_enable - Vertical Sync Enable:
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* 0 = VSYNC input is transmitted as fixed LOW
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* 1 = VSYNC input is transmitted as is
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* deskew_enable - De-skewing Enable:
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* 0 = De-skew disabled
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* 1 = De-skew enabled
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* deskew_setting - De-skewing Setting (increment of 260psec)
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* 0 = 1 step --> minimum setup / maximum hold
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* 1 = 2 step
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* 2 = 3 step
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* 3 = 4 step
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* 4 = 5 step
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* 5 = 6 step
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* 6 = 7 step
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* 7 = 8 step --> maximum setup / minimum hold
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* continuous_sync_enable- SYNC Continuous:
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* 0 = Disable
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* 1 = Enable
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* pll_filter_enable - PLL Filter Enable
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* 0 = Disable PLL Filter
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* 1 = Enable PLL Filter
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* pll_filter_value - PLL Filter characteristics:
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* 0~7 (recommended value is 4)
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*
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* Output:
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* 0 - Success
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* -1 - Fail.
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*/
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long sii164InitChip(unsigned char edgeSelect,
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unsigned char busSelect,
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unsigned char dualEdgeClkSelect,
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unsigned char hsyncEnable,
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unsigned char vsyncEnable,
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unsigned char deskewEnable,
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unsigned char deskewSetting,
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unsigned char continuousSyncEnable,
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unsigned char pllFilterEnable,
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unsigned char pllFilterValue)
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long sii164InitChip(unsigned char edge_select,
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unsigned char bus_select,
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unsigned char dual_edge_clk_select,
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unsigned char hsync_enable,
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unsigned char vsync_enable,
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unsigned char deskew_enable,
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unsigned char deskew_setting,
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unsigned char continuous_sync_enable,
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unsigned char pll_filter_enable,
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unsigned char pll_filter_value)
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{
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unsigned char config;
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@ -139,31 +139,31 @@ long sii164InitChip(unsigned char edgeSelect,
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*/
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/* Select the edge */
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if (edgeSelect == 0)
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if (edge_select == 0)
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config = SII164_CONFIGURATION_LATCH_FALLING;
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else
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config = SII164_CONFIGURATION_LATCH_RISING;
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/* Select bus wide */
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if (busSelect == 0)
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if (bus_select == 0)
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config |= SII164_CONFIGURATION_BUS_12BITS;
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else
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config |= SII164_CONFIGURATION_BUS_24BITS;
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/* Select Dual/Single Edge Clock */
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if (dualEdgeClkSelect == 0)
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if (dual_edge_clk_select == 0)
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config |= SII164_CONFIGURATION_CLOCK_SINGLE;
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else
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config |= SII164_CONFIGURATION_CLOCK_DUAL;
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/* Select HSync Enable */
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if (hsyncEnable == 0)
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if (hsync_enable == 0)
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config |= SII164_CONFIGURATION_HSYNC_FORCE_LOW;
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else
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config |= SII164_CONFIGURATION_HSYNC_AS_IS;
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/* Select VSync Enable */
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if (vsyncEnable == 0)
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if (vsync_enable == 0)
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config |= SII164_CONFIGURATION_VSYNC_FORCE_LOW;
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else
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config |= SII164_CONFIGURATION_VSYNC_AS_IS;
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@ -175,12 +175,12 @@ long sii164InitChip(unsigned char edgeSelect,
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* This fixes some artifacts problem in some mode on board 2.2.
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* Somehow this fix does not affect board 2.1.
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*/
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if (deskewEnable == 0)
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if (deskew_enable == 0)
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config = SII164_DESKEW_DISABLE;
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else
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config = SII164_DESKEW_ENABLE;
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switch (deskewSetting) {
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switch (deskew_setting) {
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case 0:
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config |= SII164_DESKEW_1_STEP;
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break;
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@ -209,19 +209,19 @@ long sii164InitChip(unsigned char edgeSelect,
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i2cWriteReg(SII164_I2C_ADDRESS, SII164_DESKEW, config);
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/* Enable/Disable Continuous Sync. */
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if (continuousSyncEnable == 0)
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if (continuous_sync_enable == 0)
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config = SII164_PLL_FILTER_SYNC_CONTINUOUS_DISABLE;
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else
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config = SII164_PLL_FILTER_SYNC_CONTINUOUS_ENABLE;
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/* Enable/Disable PLL Filter */
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if (pllFilterEnable == 0)
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if (pll_filter_enable == 0)
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config |= SII164_PLL_FILTER_DISABLE;
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else
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config |= SII164_PLL_FILTER_ENABLE;
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/* Set the PLL Filter value */
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config |= ((pllFilterValue & 0x07) << 1);
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config |= ((pll_filter_value & 0x07) << 1);
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i2cWriteReg(SII164_I2C_ADDRESS, SII164_PLL, config);
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