mfd: Add Cherry Trail Whiskey Cove PMIC driver
Add mfd driver for Intel CHT Whiskey Cove PMIC, based on various non upstreamed CHT Whiskey Cove PMIC patches. This is a somewhat minimal version which adds irqchip support and cells for: ACPI PMIC opregion support, the i2c-controller driving the external charger irc and the pwrsrc/extcon block. Further cells can be added in the future if/when drivers are upstreamed for them. [The above patch caused a build error on some archetectures] From: Arnd Bergmann <arnd@arndb.de> I ran into a build error on ARM with a platform that has a non-standard clk implementation: drivers/clk/clk.o: In function `clk_disable': clk.c:(.text.clk_disable+0x0): multiple definition of `clk_disable' arch/arm/mach-omap1/clock.o:clock.c:(.text.clk_disable+0x0): first defined here drivers/clk/clk.o: In function `clk_enable': clk.c:(.text.clk_enable+0x0): multiple definition of `clk_enable' arch/arm/mach-omap1/clock.o:clock.c:(.text.clk_enable+0x0): first defined here The problem is a device driver that uses 'select COMMON_CLK', which is generally a bad idea: selecting a subsystem should only be done from a platform, otherwise we run into circular dependencies. The same driver also selects 'GPIOLIB' and 'I2C', which has a similar effect. This turns all three into 'depends on', as it should be. Finally, we can limit the build to x86, unless we are compile testing. First patch: Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Fix for first patch (squashed): Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
This commit is contained in:
Hans de Goede
Lee Jones
Родитель
b6678050a1
Коммит
de85d79f4a
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@ -475,6 +475,22 @@ config INTEL_SOC_PMIC_BXTWC
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thermal, charger and related power management functions
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on these systems.
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config INTEL_SOC_PMIC_CHTWC
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tristate "Support for Intel Cherry Trail Whiskey Cove PMIC"
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depends on ACPI && HAS_IOMEM && I2C=y && COMMON_CLK
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depends on X86 || COMPILE_TEST
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select MFD_CORE
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select REGMAP_I2C
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select REGMAP_IRQ
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select I2C_DESIGNWARE_PLATFORM
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help
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Select this option to enable support for the Intel Cherry Trail
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Whiskey Cove PMIC found on some Intel Cherry Trail systems.
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This option is a bool as it provides an ACPI OpRegion which must be
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available before any devices using it are probed. This option also
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causes the designware-i2c driver to be builtin for the same reason.
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config MFD_INTEL_LPSS
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tristate
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select COMMON_CLK
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@ -214,6 +214,7 @@ obj-$(CONFIG_MFD_SKY81452) += sky81452.o
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intel-soc-pmic-objs := intel_soc_pmic_core.o intel_soc_pmic_crc.o
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obj-$(CONFIG_INTEL_SOC_PMIC) += intel-soc-pmic.o
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obj-$(CONFIG_INTEL_SOC_PMIC_BXTWC) += intel_soc_pmic_bxtwc.o
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obj-$(CONFIG_INTEL_SOC_PMIC_CHTWC) += intel_soc_pmic_chtwc.o
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obj-$(CONFIG_MFD_MT6397) += mt6397-core.o
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obj-$(CONFIG_MFD_ALTERA_A10SR) += altera-a10sr.o
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@ -0,0 +1,230 @@
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/*
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* MFD core driver for Intel Cherrytrail Whiskey Cove PMIC
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*
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* Copyright (C) 2017 Hans de Goede <hdegoede@redhat.com>
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*
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* Based on various non upstream patches to support the CHT Whiskey Cove PMIC:
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* Copyright (C) 2013-2015 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/acpi.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/i2c.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/mfd/core.h>
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#include <linux/mfd/intel_soc_pmic.h>
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#include <linux/regmap.h>
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/* PMIC device registers */
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#define REG_OFFSET_MASK GENMASK(7, 0)
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#define REG_ADDR_MASK GENMASK(15, 8)
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#define REG_ADDR_SHIFT 8
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#define CHT_WC_IRQLVL1 0x6e02
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#define CHT_WC_IRQLVL1_MASK 0x6e0e
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/* Whiskey Cove PMIC share same ACPI ID between different platforms */
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#define CHT_WC_HRV 3
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/* Level 1 IRQs (level 2 IRQs are handled in the child device drivers) */
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enum {
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CHT_WC_PWRSRC_IRQ = 0,
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CHT_WC_THRM_IRQ,
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CHT_WC_BCU_IRQ,
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CHT_WC_ADC_IRQ,
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CHT_WC_EXT_CHGR_IRQ,
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CHT_WC_GPIO_IRQ,
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/* There is no irq 6 */
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CHT_WC_CRIT_IRQ = 7,
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};
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static struct resource cht_wc_pwrsrc_resources[] = {
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DEFINE_RES_IRQ(CHT_WC_PWRSRC_IRQ),
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};
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static struct resource cht_wc_ext_charger_resources[] = {
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DEFINE_RES_IRQ(CHT_WC_EXT_CHGR_IRQ),
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};
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static struct mfd_cell cht_wc_dev[] = {
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{
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.name = "cht_wcove_pwrsrc",
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.num_resources = ARRAY_SIZE(cht_wc_pwrsrc_resources),
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.resources = cht_wc_pwrsrc_resources,
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}, {
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.name = "cht_wcove_ext_chgr",
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.num_resources = ARRAY_SIZE(cht_wc_ext_charger_resources),
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.resources = cht_wc_ext_charger_resources,
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},
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{ .name = "cht_wcove_region", },
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};
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/*
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* The CHT Whiskey Cove covers multiple I2C addresses, with a 1 Byte
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* register address space per I2C address, so we use 16 bit register
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* addresses where the high 8 bits contain the I2C client address.
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*/
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static int cht_wc_byte_reg_read(void *context, unsigned int reg,
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unsigned int *val)
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{
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struct i2c_client *client = context;
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int ret, orig_addr = client->addr;
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if (!(reg & REG_ADDR_MASK)) {
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dev_err(&client->dev, "Error I2C address not specified\n");
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return -EINVAL;
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}
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client->addr = (reg & REG_ADDR_MASK) >> REG_ADDR_SHIFT;
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ret = i2c_smbus_read_byte_data(client, reg & REG_OFFSET_MASK);
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client->addr = orig_addr;
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if (ret < 0)
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return ret;
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*val = ret;
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return 0;
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}
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static int cht_wc_byte_reg_write(void *context, unsigned int reg,
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unsigned int val)
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{
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struct i2c_client *client = context;
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int ret, orig_addr = client->addr;
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if (!(reg & REG_ADDR_MASK)) {
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dev_err(&client->dev, "Error I2C address not specified\n");
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return -EINVAL;
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}
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client->addr = (reg & REG_ADDR_MASK) >> REG_ADDR_SHIFT;
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ret = i2c_smbus_write_byte_data(client, reg & REG_OFFSET_MASK, val);
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client->addr = orig_addr;
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return ret;
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}
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static const struct regmap_config cht_wc_regmap_cfg = {
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.reg_bits = 16,
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.val_bits = 8,
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.reg_write = cht_wc_byte_reg_write,
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.reg_read = cht_wc_byte_reg_read,
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};
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static const struct regmap_irq cht_wc_regmap_irqs[] = {
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REGMAP_IRQ_REG(CHT_WC_PWRSRC_IRQ, 0, BIT(CHT_WC_PWRSRC_IRQ)),
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REGMAP_IRQ_REG(CHT_WC_THRM_IRQ, 0, BIT(CHT_WC_THRM_IRQ)),
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REGMAP_IRQ_REG(CHT_WC_BCU_IRQ, 0, BIT(CHT_WC_BCU_IRQ)),
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REGMAP_IRQ_REG(CHT_WC_ADC_IRQ, 0, BIT(CHT_WC_ADC_IRQ)),
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REGMAP_IRQ_REG(CHT_WC_EXT_CHGR_IRQ, 0, BIT(CHT_WC_EXT_CHGR_IRQ)),
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REGMAP_IRQ_REG(CHT_WC_GPIO_IRQ, 0, BIT(CHT_WC_GPIO_IRQ)),
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REGMAP_IRQ_REG(CHT_WC_CRIT_IRQ, 0, BIT(CHT_WC_CRIT_IRQ)),
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};
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static const struct regmap_irq_chip cht_wc_regmap_irq_chip = {
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.name = "cht_wc_irq_chip",
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.status_base = CHT_WC_IRQLVL1,
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.mask_base = CHT_WC_IRQLVL1_MASK,
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.irqs = cht_wc_regmap_irqs,
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.num_irqs = ARRAY_SIZE(cht_wc_regmap_irqs),
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.num_regs = 1,
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};
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static int cht_wc_probe(struct i2c_client *client)
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{
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struct device *dev = &client->dev;
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struct intel_soc_pmic *pmic;
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acpi_status status;
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unsigned long long hrv;
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int ret;
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status = acpi_evaluate_integer(ACPI_HANDLE(dev), "_HRV", NULL, &hrv);
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if (ACPI_FAILURE(status)) {
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dev_err(dev, "Failed to get PMIC hardware revision\n");
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return -ENODEV;
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}
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if (hrv != CHT_WC_HRV) {
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dev_err(dev, "Invalid PMIC hardware revision: %llu\n", hrv);
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return -ENODEV;
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}
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if (client->irq < 0) {
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dev_err(dev, "Invalid IRQ\n");
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return -EINVAL;
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}
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pmic = devm_kzalloc(dev, sizeof(*pmic), GFP_KERNEL);
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if (!pmic)
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return -ENOMEM;
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pmic->irq = client->irq;
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pmic->dev = dev;
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i2c_set_clientdata(client, pmic);
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pmic->regmap = devm_regmap_init(dev, NULL, client, &cht_wc_regmap_cfg);
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if (IS_ERR(pmic->regmap))
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return PTR_ERR(pmic->regmap);
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ret = devm_regmap_add_irq_chip(dev, pmic->regmap, pmic->irq,
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IRQF_ONESHOT | IRQF_SHARED, 0,
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&cht_wc_regmap_irq_chip,
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&pmic->irq_chip_data);
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if (ret)
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return ret;
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return devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE,
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cht_wc_dev, ARRAY_SIZE(cht_wc_dev), NULL, 0,
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regmap_irq_get_domain(pmic->irq_chip_data));
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}
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static void cht_wc_shutdown(struct i2c_client *client)
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{
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struct intel_soc_pmic *pmic = i2c_get_clientdata(client);
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disable_irq(pmic->irq);
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}
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static int __maybe_unused cht_wc_suspend(struct device *dev)
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{
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struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
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disable_irq(pmic->irq);
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return 0;
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}
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static int __maybe_unused cht_wc_resume(struct device *dev)
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{
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struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
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enable_irq(pmic->irq);
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return 0;
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}
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static SIMPLE_DEV_PM_OPS(cht_wc_pm_ops, cht_wc_suspend, cht_wc_resume);
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static const struct i2c_device_id cht_wc_i2c_id[] = {
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{ }
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};
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static const struct acpi_device_id cht_wc_acpi_ids[] = {
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{ "INT34D3", },
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{ }
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};
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static struct i2c_driver cht_wc_driver = {
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.driver = {
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.name = "CHT Whiskey Cove PMIC",
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.pm = &cht_wc_pm_ops,
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.acpi_match_table = cht_wc_acpi_ids,
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},
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.probe_new = cht_wc_probe,
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.shutdown = cht_wc_shutdown,
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.id_table = cht_wc_i2c_id,
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};
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builtin_i2c_driver(cht_wc_driver);
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