staging: sm750fb: Fixed no space and indent warns
This patch fixes the no spaces and indent warnings identified by the checkpath.pl script for the entire ddk750_chip.c file by using appropriate tab spaces and indents accordingly. Signed-off-by: Ragavendra Nagraj <ragavendra.bn@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Ragavendra Nagraj
Greg Kroah-Hartman
Родитель
6a9df4303b
Коммит
de99befd18
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@ -20,22 +20,22 @@ logical_chip_type_t getChipType(void)
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physicalID = devId750;//either 0x718 or 0x750
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physicalRev = revId750;
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if (physicalID == 0x718)
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{
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chip = SM718;
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}
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else if (physicalID == 0x750)
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{
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chip = SM750;
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if (physicalID == 0x718)
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{
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chip = SM718;
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}
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else if (physicalID == 0x750)
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{
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chip = SM750;
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/* SM750 and SM750LE are different in their revision ID only. */
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if (physicalRev == SM750LE_REVISION_ID){
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chip = SM750LE;
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}
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}
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else
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{
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chip = SM_UNKNOWN;
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}
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}
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else
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{
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chip = SM_UNKNOWN;
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}
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return chip;
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}
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@ -43,63 +43,63 @@ logical_chip_type_t getChipType(void)
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inline unsigned int twoToPowerOfx(unsigned long x)
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{
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unsigned long i;
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unsigned long result = 1;
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unsigned long i;
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unsigned long result = 1;
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for (i=1; i<=x; i++)
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result *= 2;
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return result;
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for (i=1; i<=x; i++)
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result *= 2;
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return result;
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}
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inline unsigned int calcPLL(pll_value_t *pPLL)
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{
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return (pPLL->inputFreq * pPLL->M / pPLL->N / twoToPowerOfx(pPLL->OD) / twoToPowerOfx(pPLL->POD));
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return (pPLL->inputFreq * pPLL->M / pPLL->N / twoToPowerOfx(pPLL->OD) / twoToPowerOfx(pPLL->POD));
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}
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unsigned int getPllValue(clock_type_t clockType, pll_value_t *pPLL)
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{
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unsigned int ulPllReg = 0;
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unsigned int ulPllReg = 0;
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pPLL->inputFreq = DEFAULT_INPUT_CLOCK;
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pPLL->clockType = clockType;
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pPLL->inputFreq = DEFAULT_INPUT_CLOCK;
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pPLL->clockType = clockType;
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switch (clockType)
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{
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case MXCLK_PLL:
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ulPllReg = PEEK32(MXCLK_PLL_CTRL);
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break;
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case PRIMARY_PLL:
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ulPllReg = PEEK32(PANEL_PLL_CTRL);
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break;
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case SECONDARY_PLL:
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ulPllReg = PEEK32(CRT_PLL_CTRL);
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break;
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case VGA0_PLL:
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ulPllReg = PEEK32(VGA_PLL0_CTRL);
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break;
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case VGA1_PLL:
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ulPllReg = PEEK32(VGA_PLL1_CTRL);
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break;
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}
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switch (clockType)
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{
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case MXCLK_PLL:
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ulPllReg = PEEK32(MXCLK_PLL_CTRL);
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break;
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case PRIMARY_PLL:
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ulPllReg = PEEK32(PANEL_PLL_CTRL);
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break;
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case SECONDARY_PLL:
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ulPllReg = PEEK32(CRT_PLL_CTRL);
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break;
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case VGA0_PLL:
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ulPllReg = PEEK32(VGA_PLL0_CTRL);
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break;
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case VGA1_PLL:
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ulPllReg = PEEK32(VGA_PLL1_CTRL);
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break;
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}
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pPLL->M = FIELD_GET(ulPllReg, PANEL_PLL_CTRL, M);
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pPLL->N = FIELD_GET(ulPllReg, PANEL_PLL_CTRL, N);
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pPLL->OD = FIELD_GET(ulPllReg, PANEL_PLL_CTRL, OD);
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pPLL->POD = FIELD_GET(ulPllReg, PANEL_PLL_CTRL, POD);
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pPLL->M = FIELD_GET(ulPllReg, PANEL_PLL_CTRL, M);
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pPLL->N = FIELD_GET(ulPllReg, PANEL_PLL_CTRL, N);
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pPLL->OD = FIELD_GET(ulPllReg, PANEL_PLL_CTRL, OD);
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pPLL->POD = FIELD_GET(ulPllReg, PANEL_PLL_CTRL, POD);
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return calcPLL(pPLL);
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return calcPLL(pPLL);
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}
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unsigned int getChipClock(void)
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{
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pll_value_t pll;
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pll_value_t pll;
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#if 1
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if(getChipType() == SM750LE)
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return MHz(130);
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#endif
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return getPllValue(MXCLK_PLL, &pll);
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return getPllValue(MXCLK_PLL, &pll);
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}
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@ -110,75 +110,75 @@ unsigned int getChipClock(void)
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*/
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void setChipClock(unsigned int frequency)
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{
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pll_value_t pll;
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unsigned int ulActualMxClk;
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pll_value_t pll;
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unsigned int ulActualMxClk;
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#if 1
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/* Cheok_0509: For SM750LE, the chip clock is fixed. Nothing to set. */
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if (getChipType() == SM750LE)
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return;
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/* Cheok_0509: For SM750LE, the chip clock is fixed. Nothing to set. */
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if (getChipType() == SM750LE)
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return;
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#endif
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if (frequency != 0)
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{
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/*
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* Set up PLL, a structure to hold the value to be set in clocks.
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*/
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pll.inputFreq = DEFAULT_INPUT_CLOCK; /* Defined in CLOCK.H */
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pll.clockType = MXCLK_PLL;
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if (frequency != 0)
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{
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/*
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* Set up PLL, a structure to hold the value to be set in clocks.
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*/
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pll.inputFreq = DEFAULT_INPUT_CLOCK; /* Defined in CLOCK.H */
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pll.clockType = MXCLK_PLL;
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/*
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* Call calcPllValue() to fill up the other fields for PLL structure.
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* Sometime, the chip cannot set up the exact clock required by User.
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* Return value from calcPllValue() gives the actual possible clock.
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*/
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ulActualMxClk = calcPllValue(frequency, &pll);
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/*
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* Call calcPllValue() to fill up the other fields for PLL structure.
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* Sometime, the chip cannot set up the exact clock required by User.
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* Return value from calcPllValue() gives the actual possible clock.
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*/
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ulActualMxClk = calcPllValue(frequency, &pll);
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/* Master Clock Control: MXCLK_PLL */
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POKE32(MXCLK_PLL_CTRL, formatPllReg(&pll));
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}
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/* Master Clock Control: MXCLK_PLL */
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POKE32(MXCLK_PLL_CTRL, formatPllReg(&pll));
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}
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}
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void setMemoryClock(unsigned int frequency)
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{
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unsigned int ulReg, divisor;
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unsigned int ulReg, divisor;
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#if 1
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/* Cheok_0509: For SM750LE, the memory clock is fixed. Nothing to set. */
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if (getChipType() == SM750LE)
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return;
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#endif
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if (frequency != 0)
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{
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/* Set the frequency to the maximum frequency that the DDR Memory can take
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which is 336MHz. */
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if (frequency > MHz(336))
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frequency = MHz(336);
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if (frequency != 0)
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{
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/* Set the frequency to the maximum frequency that the DDR Memory can take
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which is 336MHz. */
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if (frequency > MHz(336))
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frequency = MHz(336);
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/* Calculate the divisor */
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divisor = (unsigned int) roundedDiv(getChipClock(), frequency);
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/* Calculate the divisor */
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divisor = (unsigned int) roundedDiv(getChipClock(), frequency);
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/* Set the corresponding divisor in the register. */
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ulReg = PEEK32(CURRENT_GATE);
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switch(divisor)
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{
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default:
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case 1:
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ulReg = FIELD_SET(ulReg, CURRENT_GATE, M2XCLK, DIV_1);
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break;
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case 2:
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ulReg = FIELD_SET(ulReg, CURRENT_GATE, M2XCLK, DIV_2);
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break;
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case 3:
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ulReg = FIELD_SET(ulReg, CURRENT_GATE, M2XCLK, DIV_3);
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break;
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case 4:
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ulReg = FIELD_SET(ulReg, CURRENT_GATE, M2XCLK, DIV_4);
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break;
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}
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/* Set the corresponding divisor in the register. */
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ulReg = PEEK32(CURRENT_GATE);
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switch(divisor)
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{
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default:
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case 1:
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ulReg = FIELD_SET(ulReg, CURRENT_GATE, M2XCLK, DIV_1);
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break;
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case 2:
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ulReg = FIELD_SET(ulReg, CURRENT_GATE, M2XCLK, DIV_2);
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break;
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case 3:
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ulReg = FIELD_SET(ulReg, CURRENT_GATE, M2XCLK, DIV_3);
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break;
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case 4:
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ulReg = FIELD_SET(ulReg, CURRENT_GATE, M2XCLK, DIV_4);
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break;
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}
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setCurrentGate(ulReg);
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}
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setCurrentGate(ulReg);
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}
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}
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@ -192,43 +192,43 @@ void setMemoryClock(unsigned int frequency)
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*/
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void setMasterClock(unsigned int frequency)
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{
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unsigned int ulReg, divisor;
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#if 1
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unsigned int ulReg, divisor;
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#if 1
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/* Cheok_0509: For SM750LE, the memory clock is fixed. Nothing to set. */
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if (getChipType() == SM750LE)
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return;
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#endif
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if (frequency != 0)
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{
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/* Set the frequency to the maximum frequency that the SM750 engine can
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run, which is about 190 MHz. */
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if (frequency > MHz(190))
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frequency = MHz(190);
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if (frequency != 0)
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{
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/* Set the frequency to the maximum frequency that the SM750 engine can
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run, which is about 190 MHz. */
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if (frequency > MHz(190))
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frequency = MHz(190);
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/* Calculate the divisor */
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divisor = (unsigned int) roundedDiv(getChipClock(), frequency);
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/* Calculate the divisor */
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divisor = (unsigned int) roundedDiv(getChipClock(), frequency);
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/* Set the corresponding divisor in the register. */
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ulReg = PEEK32(CURRENT_GATE);
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switch(divisor)
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{
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default:
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case 3:
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ulReg = FIELD_SET(ulReg, CURRENT_GATE, MCLK, DIV_3);
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break;
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case 4:
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ulReg = FIELD_SET(ulReg, CURRENT_GATE, MCLK, DIV_4);
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break;
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case 6:
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ulReg = FIELD_SET(ulReg, CURRENT_GATE, MCLK, DIV_6);
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break;
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case 8:
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ulReg = FIELD_SET(ulReg, CURRENT_GATE, MCLK, DIV_8);
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break;
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}
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/* Set the corresponding divisor in the register. */
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ulReg = PEEK32(CURRENT_GATE);
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switch(divisor)
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{
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default:
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case 3:
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ulReg = FIELD_SET(ulReg, CURRENT_GATE, MCLK, DIV_3);
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break;
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case 4:
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ulReg = FIELD_SET(ulReg, CURRENT_GATE, MCLK, DIV_4);
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break;
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case 6:
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ulReg = FIELD_SET(ulReg, CURRENT_GATE, MCLK, DIV_6);
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break;
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case 8:
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ulReg = FIELD_SET(ulReg, CURRENT_GATE, MCLK, DIV_8);
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break;
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}
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setCurrentGate(ulReg);
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}
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setCurrentGate(ulReg);
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}
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}
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@ -249,11 +249,11 @@ unsigned int ddk750_getVMSize(void)
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/* get frame buffer size from GPIO */
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reg = FIELD_GET(PEEK32(MISC_CTRL),MISC_CTRL,LOCALMEM_SIZE);
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switch(reg){
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case MISC_CTRL_LOCALMEM_SIZE_8M: data = MB(8); break; /* 8 Mega byte */
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case MISC_CTRL_LOCALMEM_SIZE_16M: data = MB(16); break; /* 16 Mega byte */
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case MISC_CTRL_LOCALMEM_SIZE_32M: data = MB(32); break; /* 32 Mega byte */
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case MISC_CTRL_LOCALMEM_SIZE_64M: data = MB(64); break; /* 64 Mega byte */
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default: data = 0;break;
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case MISC_CTRL_LOCALMEM_SIZE_8M: data = MB(8); break; /* 8 Mega byte */
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case MISC_CTRL_LOCALMEM_SIZE_16M: data = MB(16); break; /* 16 Mega byte */
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case MISC_CTRL_LOCALMEM_SIZE_32M: data = MB(32); break; /* 32 Mega byte */
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case MISC_CTRL_LOCALMEM_SIZE_64M: data = MB(64); break; /* 64 Mega byte */
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default: data = 0;break;
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}
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return data;
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@ -391,10 +391,10 @@ int ddk750_initHw(initchip_param_t * pInitParam)
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unsigned int absDiff(unsigned int a, unsigned int b)
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{
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if ( a > b )
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return(a - b);
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else
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return(b - a);
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if ( a > b )
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return(a - b);
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else
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return(b - a);
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}
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#endif
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@ -435,7 +435,7 @@ unsigned int calcPllValue(unsigned int request_orig,pll_value_t *pll)
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{3,0,3,8},
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};
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/* as sm750 register definition, N located in 2,15 and M located in 1,255 */
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/* as sm750 register definition, N located in 2,15 and M located in 1,255 */
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int N,M,X,d;
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int xcnt;
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int miniDiff;
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@ -446,11 +446,11 @@ unsigned int calcPllValue(unsigned int request_orig,pll_value_t *pll)
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#if 1
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if (getChipType() == SM750LE)
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{
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/* SM750LE don't have prgrammable PLL and M/N values to work on.
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Just return the requested clock. */
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return request_orig;
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}
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{
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/* SM750LE don't have prgrammable PLL and M/N values to work on.
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Just return the requested clock. */
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return request_orig;
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}
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#endif
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ret = 0;
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@ -487,7 +487,7 @@ unsigned int calcPllValue(unsigned int request_orig,pll_value_t *pll)
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{
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unsigned int diff;
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tmpClock = pll->inputFreq *M / N / X;
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diff = absDiff(tmpClock,request_orig);
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diff = absDiff(tmpClock,request_orig);
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if(diff < miniDiff)
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{
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pll->M = M;
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@ -510,104 +510,104 @@ unsigned int ulRequestClk, /* Required pixel clock in Hz unit */
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pll_value_t *pPLL /* Structure to hold the value to be set in PLL */
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)
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{
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unsigned int M, N, OD, POD = 0, diff, pllClk, odPower, podPower;
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unsigned int bestDiff = 0xffffffff; /* biggest 32 bit unsigned number */
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unsigned int M, N, OD, POD = 0, diff, pllClk, odPower, podPower;
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unsigned int bestDiff = 0xffffffff; /* biggest 32 bit unsigned number */
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unsigned int ret;
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/* Init PLL structure to know states */
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pPLL->M = 0;
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pPLL->N = 0;
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pPLL->OD = 0;
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pPLL->POD = 0;
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pPLL->M = 0;
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pPLL->N = 0;
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pPLL->OD = 0;
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pPLL->POD = 0;
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/* Sanity check: None at the moment */
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|
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/* Convert everything in Khz range in order to avoid calculation overflow */
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pPLL->inputFreq /= 1000;
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ulRequestClk /= 1000;
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||||
pPLL->inputFreq /= 1000;
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ulRequestClk /= 1000;
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#ifndef VALIDATION_CHIP
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/* The maximum of post divider is 8. */
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for (POD=0; POD<=3; POD++)
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for (POD=0; POD<=3; POD++)
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#endif
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{
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{
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#ifndef VALIDATION_CHIP
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/* MXCLK_PLL does not have post divider. */
|
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if ((POD > 0) && (pPLL->clockType == MXCLK_PLL))
|
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break;
|
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/* MXCLK_PLL does not have post divider. */
|
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if ((POD > 0) && (pPLL->clockType == MXCLK_PLL))
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break;
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||||
#endif
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/* Work out 2 to the power of POD */
|
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podPower = twoToPowerOfx(POD);
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/* Work out 2 to the power of POD */
|
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podPower = twoToPowerOfx(POD);
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||||
|
||||
/* OD has only 2 bits [15:14] and its value must between 0 to 3 */
|
||||
for (OD=0; OD<=3; OD++)
|
||||
{
|
||||
/* Work out 2 to the power of OD */
|
||||
odPower = twoToPowerOfx(OD);
|
||||
/* OD has only 2 bits [15:14] and its value must between 0 to 3 */
|
||||
for (OD=0; OD<=3; OD++)
|
||||
{
|
||||
/* Work out 2 to the power of OD */
|
||||
odPower = twoToPowerOfx(OD);
|
||||
|
||||
#ifdef VALIDATION_CHIP
|
||||
if (odPower > 4)
|
||||
podPower = 4;
|
||||
else
|
||||
podPower = odPower;
|
||||
if (odPower > 4)
|
||||
podPower = 4;
|
||||
else
|
||||
podPower = odPower;
|
||||
#endif
|
||||
|
||||
/* N has 4 bits [11:8] and its value must between 2 and 15.
|
||||
The N == 1 will behave differently --> Result is not correct. */
|
||||
for (N=2; N<=15; N++)
|
||||
{
|
||||
/* The formula for PLL is ulRequestClk = inputFreq * M / N / (2^OD)
|
||||
In the following steps, we try to work out a best M value given the others are known.
|
||||
To avoid decimal calculation, we use 1000 as multiplier for up to 3 decimal places of accuracy.
|
||||
*/
|
||||
M = ulRequestClk * N * odPower * 1000 / pPLL->inputFreq;
|
||||
M = roundedDiv(M, 1000);
|
||||
/* N has 4 bits [11:8] and its value must between 2 and 15.
|
||||
The N == 1 will behave differently --> Result is not correct. */
|
||||
for (N=2; N<=15; N++)
|
||||
{
|
||||
/* The formula for PLL is ulRequestClk = inputFreq * M / N / (2^OD)
|
||||
In the following steps, we try to work out a best M value given the others are known.
|
||||
To avoid decimal calculation, we use 1000 as multiplier for up to 3 decimal places of accuracy.
|
||||
*/
|
||||
M = ulRequestClk * N * odPower * 1000 / pPLL->inputFreq;
|
||||
M = roundedDiv(M, 1000);
|
||||
|
||||
/* M field has only 8 bits, reject value bigger than 8 bits */
|
||||
if (M < 256)
|
||||
{
|
||||
/* Calculate the actual clock for a given M & N */
|
||||
pllClk = pPLL->inputFreq * M / N / odPower / podPower;
|
||||
/* M field has only 8 bits, reject value bigger than 8 bits */
|
||||
if (M < 256)
|
||||
{
|
||||
/* Calculate the actual clock for a given M & N */
|
||||
pllClk = pPLL->inputFreq * M / N / odPower / podPower;
|
||||
|
||||
/* How much are we different from the requirement */
|
||||
diff = absDiff(pllClk, ulRequestClk);
|
||||
/* How much are we different from the requirement */
|
||||
diff = absDiff(pllClk, ulRequestClk);
|
||||
|
||||
if (diff < bestDiff)
|
||||
{
|
||||
bestDiff = diff;
|
||||
if (diff < bestDiff)
|
||||
{
|
||||
bestDiff = diff;
|
||||
|
||||
/* Store M and N values */
|
||||
pPLL->M = M;
|
||||
pPLL->N = N;
|
||||
pPLL->OD = OD;
|
||||
/* Store M and N values */
|
||||
pPLL->M = M;
|
||||
pPLL->N = N;
|
||||
pPLL->OD = OD;
|
||||
|
||||
#ifdef VALIDATION_CHIP
|
||||
if (OD > 2)
|
||||
POD = 2;
|
||||
else
|
||||
POD = OD;
|
||||
if (OD > 2)
|
||||
POD = 2;
|
||||
else
|
||||
POD = OD;
|
||||
#endif
|
||||
|
||||
pPLL->POD = POD;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
pPLL->POD = POD;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Restore input frequency from Khz to hz unit */
|
||||
// pPLL->inputFreq *= 1000;
|
||||
ulRequestClk *= 1000;
|
||||
pPLL->inputFreq = DEFAULT_INPUT_CLOCK; /* Default reference clock */
|
||||
ulRequestClk *= 1000;
|
||||
pPLL->inputFreq = DEFAULT_INPUT_CLOCK; /* Default reference clock */
|
||||
|
||||
/* Output debug information */
|
||||
//DDKDEBUGPRINT((DISPLAY_LEVEL, "calcPllValue: Requested Frequency = %d\n", ulRequestClk));
|
||||
//DDKDEBUGPRINT((DISPLAY_LEVEL, "calcPllValue: Input CLK = %dHz, M=%d, N=%d, OD=%d, POD=%d\n", pPLL->inputFreq, pPLL->M, pPLL->N, pPLL->OD, pPLL->POD));
|
||||
//DDKDEBUGPRINT((DISPLAY_LEVEL, "calcPllValue: Requested Frequency = %d\n", ulRequestClk));
|
||||
//DDKDEBUGPRINT((DISPLAY_LEVEL, "calcPllValue: Input CLK = %dHz, M=%d, N=%d, OD=%d, POD=%d\n", pPLL->inputFreq, pPLL->M, pPLL->N, pPLL->OD, pPLL->POD));
|
||||
|
||||
/* Return actual frequency that the PLL can set */
|
||||
ret = calcPLL(pPLL);
|
||||
return ret;
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -616,22 +616,22 @@ pll_value_t *pPLL /* Structure to hold the value to be set in PLL */
|
|||
|
||||
unsigned int formatPllReg(pll_value_t *pPLL)
|
||||
{
|
||||
unsigned int ulPllReg = 0;
|
||||
unsigned int ulPllReg = 0;
|
||||
|
||||
/* Note that all PLL's have the same format. Here, we just use Panel PLL parameter
|
||||
to work out the bit fields in the register.
|
||||
On returning a 32 bit number, the value can be applied to any PLL in the calling function.
|
||||
*/
|
||||
ulPllReg =
|
||||
FIELD_SET( 0, PANEL_PLL_CTRL, BYPASS, OFF)
|
||||
| FIELD_SET( 0, PANEL_PLL_CTRL, POWER, ON)
|
||||
| FIELD_SET( 0, PANEL_PLL_CTRL, INPUT, OSC)
|
||||
ulPllReg =
|
||||
FIELD_SET( 0, PANEL_PLL_CTRL, BYPASS, OFF)
|
||||
| FIELD_SET( 0, PANEL_PLL_CTRL, POWER, ON)
|
||||
| FIELD_SET( 0, PANEL_PLL_CTRL, INPUT, OSC)
|
||||
#ifndef VALIDATION_CHIP
|
||||
| FIELD_VALUE(0, PANEL_PLL_CTRL, POD, pPLL->POD)
|
||||
| FIELD_VALUE(0, PANEL_PLL_CTRL, POD, pPLL->POD)
|
||||
#endif
|
||||
| FIELD_VALUE(0, PANEL_PLL_CTRL, OD, pPLL->OD)
|
||||
| FIELD_VALUE(0, PANEL_PLL_CTRL, N, pPLL->N)
|
||||
| FIELD_VALUE(0, PANEL_PLL_CTRL, M, pPLL->M);
|
||||
| FIELD_VALUE(0, PANEL_PLL_CTRL, OD, pPLL->OD)
|
||||
| FIELD_VALUE(0, PANEL_PLL_CTRL, N, pPLL->N)
|
||||
| FIELD_VALUE(0, PANEL_PLL_CTRL, M, pPLL->M);
|
||||
|
||||
return ulPllReg;
|
||||
}
|
||||
|
|
|
|||
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