tg3: Cleanup extended rx ring size code
Hardcoded values are used in multiple places to describe the maximum rx ring sizes. This patch replaces those values with preprocessor constants. This patch also introduces a new TG3_FLG3_LRG_PROD_RING_CAP to determine if the device is capable of supporting larger ring sizes. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Matt Carlson
David S. Miller
Родитель
c6e1a0d12c
Коммит
de9f52300d
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@ -97,14 +97,12 @@
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* them in the NIC onboard memory.
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*/
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#define TG3_RX_STD_RING_SIZE(tp) \
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((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || \
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) ? \
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RX_STD_MAX_SIZE_5717 : 512)
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((tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP) ? \
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TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
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#define TG3_DEF_RX_RING_PENDING 200
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#define TG3_RX_JMB_RING_SIZE(tp) \
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((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || \
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) ? \
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1024 : 256)
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((tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP) ? \
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TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
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#define TG3_DEF_RX_JUMBO_RING_PENDING 100
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#define TG3_RSS_INDIR_TBL_SIZE 128
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@ -8115,9 +8113,10 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
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((u64) tpr->rx_jmb_mapping >> 32));
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tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
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((u64) tpr->rx_jmb_mapping & 0xffffffff));
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val = TG3_RX_JMB_RING_SIZE(tp) <<
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BDINFO_FLAGS_MAXLEN_SHIFT;
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tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
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(RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
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BDINFO_FLAGS_USE_EXT_RECV);
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val | BDINFO_FLAGS_USE_EXT_RECV);
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if (!(tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
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tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
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@ -8129,15 +8128,15 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
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if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
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val = RX_STD_MAX_SIZE_5705;
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val = TG3_RX_STD_MAX_SIZE_5700;
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else
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val = RX_STD_MAX_SIZE_5717;
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val = TG3_RX_STD_MAX_SIZE_5717;
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val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
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val |= (TG3_RX_STD_DMA_SZ << 2);
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} else
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val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
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} else
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val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
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val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT;
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tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
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@ -8421,8 +8420,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
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tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
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tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
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val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
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if (tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP)
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val |= RCVDBDI_MODE_LRG_RING_SZ;
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tw32(RCVDBDI_MODE, val);
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tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
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@ -13125,14 +13123,13 @@ static inline void vlan_features_add(struct net_device *dev, unsigned long flags
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static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
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{
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
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return 4096;
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if (tp->tg3_flags3 & TG3_FLG3_LRG_PROD_RING_CAP)
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return TG3_RX_RET_MAX_SIZE_5717;
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else if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
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!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
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return 1024;
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return TG3_RX_RET_MAX_SIZE_5700;
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else
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return 512;
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return TG3_RX_RET_MAX_SIZE_5705;
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}
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static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets) = {
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@ -13430,6 +13427,10 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
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}
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
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tp->tg3_flags3 |= TG3_FLG3_LRG_PROD_RING_CAP;
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if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
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GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
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tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
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@ -25,9 +25,13 @@
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#define TG3_RX_INTERNAL_RING_SZ_5906 32
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#define RX_STD_MAX_SIZE_5705 512
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#define RX_STD_MAX_SIZE_5717 2048
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#define RX_JUMBO_MAX_SIZE 0xdeadbeef /* XXX */
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#define TG3_RX_STD_MAX_SIZE_5700 512
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#define TG3_RX_STD_MAX_SIZE_5717 2048
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#define TG3_RX_JMB_MAX_SIZE_5700 256
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#define TG3_RX_JMB_MAX_SIZE_5717 1024
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#define TG3_RX_RET_MAX_SIZE_5700 1024
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#define TG3_RX_RET_MAX_SIZE_5705 512
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#define TG3_RX_RET_MAX_SIZE_5717 4096
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/* First 256 bytes are a mirror of PCI config space. */
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#define TG3PCI_VENDOR 0x00000000
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@ -2897,6 +2901,7 @@ struct tg3 {
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#define TG3_FLG3_5701_DMA_BUG 0x00000008
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#define TG3_FLG3_USE_PHYLIB 0x00000010
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#define TG3_FLG3_MDIOBUS_INITED 0x00000020
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#define TG3_FLG3_LRG_PROD_RING_CAP 0x00000080
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#define TG3_FLG3_RGMII_INBAND_DISABLE 0x00000100
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#define TG3_FLG3_RGMII_EXT_IBND_RX_EN 0x00000200
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#define TG3_FLG3_RGMII_EXT_IBND_TX_EN 0x00000400
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