[PATCH] m68knommu: fix timer register access on 523x ColdFire platforms
The 523x timer TRR register is a full 32bits, the older register (on other ColdFire parts) was only 16 bits. Use the right type of __raw_read when accessing it. Problem found by Yaroslav Vinogradov <yaroslav.vinogradov@freescale.com> Signed-off-by: Greg Ungerer <gerg@uclinux.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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dd93e857fc
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deb77c8501
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@ -3,7 +3,7 @@
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/*
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* timers.c -- generic ColdFire hardware timer support.
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*
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* Copyright (C) 1999-2003, Greg Ungerer (gerg@snapgear.com)
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* Copyright (C) 1999-2006, Greg Ungerer (gerg@snapgear.com)
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*/
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/***************************************************************************/
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@ -44,6 +44,14 @@ unsigned int mcf_timerlevel = 5;
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extern void mcf_settimericr(int timer, int level);
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extern int mcf_timerirqpending(int timer);
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#if defined(CONFIG_M532x)
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#define __raw_readtrr __raw_readl
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#define __raw_writetrr __raw_writel
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#else
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#define __raw_readtrr __raw_readw
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#define __raw_writetrr __raw_writew
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#endif
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/***************************************************************************/
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void coldfire_tick(void)
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@ -57,7 +65,7 @@ void coldfire_tick(void)
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void coldfire_timer_init(irqreturn_t (*handler)(int, void *, struct pt_regs *))
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{
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__raw_writew(MCFTIMER_TMR_DISABLE, TA(MCFTIMER_TMR));
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__raw_writew(((MCF_BUSCLK / 16) / HZ), TA(MCFTIMER_TRR));
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__raw_writetrr(((MCF_BUSCLK / 16) / HZ), TA(MCFTIMER_TRR));
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__raw_writew(MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 |
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MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE, TA(MCFTIMER_TMR));
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@ -76,7 +84,7 @@ unsigned long coldfire_timer_offset(void)
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unsigned long trr, tcn, offset;
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tcn = __raw_readw(TA(MCFTIMER_TCN));
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trr = __raw_readw(TA(MCFTIMER_TRR));
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trr = __raw_readtrr(TA(MCFTIMER_TRR));
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offset = (tcn * (1000000 / HZ)) / trr;
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/* Check if we just wrapped the counters and maybe missed a tick */
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@ -120,7 +128,7 @@ void coldfire_profile_init(void)
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/* Set up TIMER 2 as high speed profile clock */
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__raw_writew(MCFTIMER_TMR_DISABLE, PA(MCFTIMER_TMR));
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__raw_writew(((MCF_CLK / 16) / PROFILEHZ), PA(MCFTIMER_TRR));
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__raw_writetrr(((MCF_CLK / 16) / PROFILEHZ), PA(MCFTIMER_TRR));
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__raw_writew(MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 |
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MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE, PA(MCFTIMER_TMR));
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