Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/next-queue
Jeff Kirsher says: ==================== Intel Wired LAN Driver Updates 2015-08-18 This series contains updates to igb, e100, e1000e and ixgbe. Shota Suzuki provides a fix for a possible overflow in igb_set_interrupt_capability() which leads to an oops. When changing the number of queues by "ethtool -L", set IGB_FLAG_QUEUE_PAIRS in the same manner as when initializing the igb driver. Vasily Averin provides a fix for a missing rtnl_unlock() for when we error out due to not being able to allocate memory for our queues. Stefan Assman provides a couple of fixes for igb/igbvf. First changes the igb driver in probe to simply call igb_enable_sriov() instead of igb_sriov_reinit() since we are starting from scratch. Then in igbvf, fix the driver where it does not clear the buffer_info->dma in all cases after calling dma_unmap_single(), which was found by changing the MTU twice. Richard Cochran implements the periodic output function using the programmable clock outputs available in i210 when possible, falling back to the target time for longer periods. Todd adds support for the Marvell PHY 1512 which is required for i354 devices. Then updates igb to make sure SR-IOV init uses the correct number of queues, since recent changes could result in the PF holding onto all of the queues. Alex Williamson provides a fix in the case where a guest OS does not support hot-unplug, so disable SR-IOV prior to unregister_netdev() to avoid the problem. Jia-Ju Bai provides several patches, first knocks some collecting dust off an old e100 driver to add a check to avoid a null pointer dereference. Then cleans up a possible resource leak by releasing the skb buffer allocated when the e100_xmit_prepare() runs into an issue in the DMA mapping. In igb, add a missing rtnl_unlock() for when we error out due to igb_sriov_reinit() in the igb_init_interrupt_scheme(). Provides a e1000e fix, based on suggestions from Alex Duyck to move head/tail register writing to e1000_configure_tx/rx() to avoid a possible null pointer dereference (similar to igb driver). Lastly, fix a possible memory leak in igb_probe(), where the memory shadow_vfta allocated by kcalloc in igb_sw_init() is not freed. Mark simplifies port-specific macros for ixgbe by eliminating explicit comparisons with 0 and enclose formal parameters in parens to eliminate the risk of an operator precedence issue. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
Коммит
def63be85f
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@ -1770,8 +1770,11 @@ static int e100_xmit_prepare(struct nic *nic, struct cb *cb,
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dma_addr = pci_map_single(nic->pdev,
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skb->data, skb->len, PCI_DMA_TODEVICE);
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/* If we can't map the skb, have the upper layer try later */
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if (pci_dma_mapping_error(nic->pdev, dma_addr))
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if (pci_dma_mapping_error(nic->pdev, dma_addr)) {
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dev_kfree_skb_any(skb);
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skb = NULL;
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return -ENOMEM;
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}
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/*
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* Use the last 4 bytes of the SKB payload packet as the CRC, used for
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@ -2967,6 +2970,11 @@ static int e100_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
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nic->params.cbs.max * sizeof(struct cb),
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sizeof(u32),
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0);
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if (!nic->cbs_pool) {
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netif_err(nic, probe, nic->netdev, "Cannot create DMA pool, aborting\n");
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err = -ENOMEM;
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goto err_out_pool;
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}
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netif_info(nic, probe, nic->netdev,
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"addr 0x%llx, irq %d, MAC addr %pM\n",
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(unsigned long long)pci_resource_start(pdev, use_io ? 1 : 0),
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@ -2974,6 +2982,8 @@ static int e100_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
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return 0;
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err_out_pool:
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unregister_netdev(netdev);
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err_out_free:
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e100_free(nic);
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err_out_iounmap:
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@ -1737,12 +1737,6 @@ static void e1000_clean_rx_ring(struct e1000_ring *rx_ring)
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rx_ring->next_to_clean = 0;
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rx_ring->next_to_use = 0;
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adapter->flags2 &= ~FLAG2_IS_DISCARDING;
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writel(0, rx_ring->head);
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if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
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e1000e_update_rdt_wa(rx_ring, 0);
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else
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writel(0, rx_ring->tail);
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}
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static void e1000e_downshift_workaround(struct work_struct *work)
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@ -2447,12 +2441,6 @@ static void e1000_clean_tx_ring(struct e1000_ring *tx_ring)
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tx_ring->next_to_use = 0;
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tx_ring->next_to_clean = 0;
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writel(0, tx_ring->head);
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if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
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e1000e_update_tdt_wa(tx_ring, 0);
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else
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writel(0, tx_ring->tail);
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}
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/**
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@ -2954,6 +2942,12 @@ static void e1000_configure_tx(struct e1000_adapter *adapter)
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tx_ring->head = adapter->hw.hw_addr + E1000_TDH(0);
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tx_ring->tail = adapter->hw.hw_addr + E1000_TDT(0);
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writel(0, tx_ring->head);
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if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
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e1000e_update_tdt_wa(tx_ring, 0);
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else
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writel(0, tx_ring->tail);
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/* Set the Tx Interrupt Delay register */
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ew32(TIDV, adapter->tx_int_delay);
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/* Tx irq moderation */
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@ -3275,6 +3269,12 @@ static void e1000_configure_rx(struct e1000_adapter *adapter)
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rx_ring->head = adapter->hw.hw_addr + E1000_RDH(0);
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rx_ring->tail = adapter->hw.hw_addr + E1000_RDT(0);
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writel(0, rx_ring->head);
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if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
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e1000e_update_rdt_wa(rx_ring, 0);
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else
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writel(0, rx_ring->tail);
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/* Enable Receive Checksum Offload for TCP and UDP */
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rxcsum = er32(RXCSUM);
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if (adapter->netdev->features & NETIF_F_RXCSUM)
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@ -231,6 +231,7 @@ static s32 igb_init_phy_params_82575(struct e1000_hw *hw)
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/* Verify phy id and set remaining function pointers */
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switch (phy->id) {
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case M88E1543_E_PHY_ID:
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case M88E1512_E_PHY_ID:
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case I347AT4_E_PHY_ID:
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case M88E1112_E_PHY_ID:
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case M88E1111_I_PHY_ID:
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@ -243,7 +244,7 @@ static s32 igb_init_phy_params_82575(struct e1000_hw *hw)
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else
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phy->ops.get_cable_length = igb_get_cable_length_m88;
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phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
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/* Check if this PHY is confgured for media swap. */
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/* Check if this PHY is configured for media swap. */
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if (phy->id == M88E1112_E_PHY_ID) {
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u16 data;
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@ -266,6 +267,11 @@ static s32 igb_init_phy_params_82575(struct e1000_hw *hw)
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hw->mac.ops.check_for_link =
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igb_check_for_link_media_swap;
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}
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if (phy->id == M88E1512_E_PHY_ID) {
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ret_val = igb_initialize_M88E1512_phy(hw);
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if (ret_val)
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goto out;
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}
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break;
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case IGP03E1000_E_PHY_ID:
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phy->type = e1000_phy_igp_3;
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@ -897,6 +903,7 @@ out:
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**/
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static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
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{
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struct e1000_phy_info *phy = &hw->phy;
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s32 ret_val;
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/* This isn't a true "hard" reset, but is the only reset
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@ -913,7 +920,11 @@ static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
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goto out;
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ret_val = igb_phy_sw_reset(hw);
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if (ret_val)
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goto out;
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if (phy->id == M88E1512_E_PHY_ID)
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ret_val = igb_initialize_M88E1512_phy(hw);
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out:
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return ret_val;
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}
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@ -1587,6 +1598,7 @@ static s32 igb_setup_copper_link_82575(struct e1000_hw *hw)
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case I347AT4_E_PHY_ID:
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case M88E1112_E_PHY_ID:
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case M88E1543_E_PHY_ID:
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case M88E1512_E_PHY_ID:
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case I210_I_PHY_ID:
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ret_val = igb_copper_link_setup_m88_gen2(hw);
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break;
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@ -2629,7 +2641,8 @@ s32 igb_set_eee_i354(struct e1000_hw *hw, bool adv1G, bool adv100M)
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u16 phy_data;
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if ((hw->phy.media_type != e1000_media_type_copper) ||
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(phy->id != M88E1543_E_PHY_ID))
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((phy->id != M88E1543_E_PHY_ID) &&
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(phy->id != M88E1512_E_PHY_ID)))
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goto out;
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if (!hw->dev_spec._82575.eee_disable) {
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@ -2709,7 +2722,8 @@ s32 igb_get_eee_status_i354(struct e1000_hw *hw, bool *status)
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/* Check if EEE is supported on this device. */
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if ((hw->phy.media_type != e1000_media_type_copper) ||
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(phy->id != M88E1543_E_PHY_ID))
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((phy->id != M88E1543_E_PHY_ID) &&
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(phy->id != M88E1512_E_PHY_ID)))
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goto out;
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ret_val = igb_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354,
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@ -604,6 +604,10 @@
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#define E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT 7
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#define E1000_M88E1112_PAGE_ADDR 0x16
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#define E1000_M88E1112_STATUS 0x01
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#define E1000_M88E1512_CFG_REG_1 0x0010
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#define E1000_M88E1512_CFG_REG_2 0x0011
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#define E1000_M88E1512_CFG_REG_3 0x0007
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#define E1000_M88E1512_MODE 0x0014
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/* PCI Express Control */
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#define E1000_GCR_CMPL_TMOUT_MASK 0x0000F000
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@ -861,6 +865,7 @@
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#define M88_VENDOR 0x0141
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#define I210_I_PHY_ID 0x01410C00
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#define M88E1543_E_PHY_ID 0x01410EA0
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#define M88E1512_E_PHY_ID 0x01410DD0
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/* M88E1000 Specific Registers */
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#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */
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@ -1262,6 +1262,8 @@ s32 igb_phy_force_speed_duplex_m88(struct e1000_hw *hw)
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switch (hw->phy.id) {
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case I347AT4_E_PHY_ID:
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case M88E1112_E_PHY_ID:
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case M88E1543_E_PHY_ID:
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case M88E1512_E_PHY_ID:
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case I210_I_PHY_ID:
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reset_dsp = false;
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break;
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@ -1270,9 +1272,9 @@ s32 igb_phy_force_speed_duplex_m88(struct e1000_hw *hw)
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reset_dsp = false;
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break;
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}
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if (!reset_dsp)
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if (!reset_dsp) {
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hw_dbg("Link taking longer than expected.\n");
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else {
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} else {
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/* We didn't get link.
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* Reset the DSP and cross our fingers.
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*/
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@ -1297,6 +1299,8 @@ s32 igb_phy_force_speed_duplex_m88(struct e1000_hw *hw)
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if (hw->phy.type != e1000_phy_m88 ||
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hw->phy.id == I347AT4_E_PHY_ID ||
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hw->phy.id == M88E1112_E_PHY_ID ||
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hw->phy.id == M88E1543_E_PHY_ID ||
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hw->phy.id == M88E1512_E_PHY_ID ||
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hw->phy.id == I210_I_PHY_ID)
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goto out;
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@ -1737,6 +1741,7 @@ s32 igb_get_cable_length_m88_gen2(struct e1000_hw *hw)
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phy->cable_length = phy_data / (is_cm ? 100 : 1);
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break;
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case M88E1543_E_PHY_ID:
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case M88E1512_E_PHY_ID:
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case I347AT4_E_PHY_ID:
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/* Remember the original page select and set it to 7 */
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ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
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@ -2188,6 +2193,90 @@ s32 igb_phy_init_script_igp3(struct e1000_hw *hw)
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return 0;
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}
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/**
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* igb_initialize_M88E1512_phy - Initialize M88E1512 PHY
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* @hw: pointer to the HW structure
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*
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* Initialize Marvel 1512 to work correctly with Avoton.
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**/
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s32 igb_initialize_M88E1512_phy(struct e1000_hw *hw)
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{
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struct e1000_phy_info *phy = &hw->phy;
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s32 ret_val = 0;
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|
||||
/* Switch to PHY page 0xFF. */
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ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);
|
||||
if (ret_val)
|
||||
goto out;
|
||||
|
||||
ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);
|
||||
if (ret_val)
|
||||
goto out;
|
||||
|
||||
ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);
|
||||
if (ret_val)
|
||||
goto out;
|
||||
|
||||
ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);
|
||||
if (ret_val)
|
||||
goto out;
|
||||
|
||||
ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);
|
||||
if (ret_val)
|
||||
goto out;
|
||||
|
||||
ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);
|
||||
if (ret_val)
|
||||
goto out;
|
||||
|
||||
ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);
|
||||
if (ret_val)
|
||||
goto out;
|
||||
|
||||
ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xCC0C);
|
||||
if (ret_val)
|
||||
goto out;
|
||||
|
||||
ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);
|
||||
if (ret_val)
|
||||
goto out;
|
||||
|
||||
/* Switch to PHY page 0xFB. */
|
||||
ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);
|
||||
if (ret_val)
|
||||
goto out;
|
||||
|
||||
ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0x000D);
|
||||
if (ret_val)
|
||||
goto out;
|
||||
|
||||
/* Switch to PHY page 0x12. */
|
||||
ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);
|
||||
if (ret_val)
|
||||
goto out;
|
||||
|
||||
/* Change mode to SGMII-to-Copper */
|
||||
ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);
|
||||
if (ret_val)
|
||||
goto out;
|
||||
|
||||
/* Return the PHY to page 0. */
|
||||
ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
|
||||
if (ret_val)
|
||||
goto out;
|
||||
|
||||
ret_val = igb_phy_sw_reset(hw);
|
||||
if (ret_val) {
|
||||
hw_dbg("Error committing the PHY changes\n");
|
||||
return ret_val;
|
||||
}
|
||||
|
||||
/* msec_delay(1000); */
|
||||
usleep_range(1000, 2000);
|
||||
out:
|
||||
return ret_val;
|
||||
}
|
||||
|
||||
/**
|
||||
* igb_power_up_phy_copper - Restore copper link in case of PHY power down
|
||||
* @hw: pointer to the HW structure
|
||||
|
|
|
|||
|
|
@ -61,6 +61,7 @@ s32 igb_phy_has_link(struct e1000_hw *hw, u32 iterations,
|
|||
void igb_power_up_phy_copper(struct e1000_hw *hw);
|
||||
void igb_power_down_phy_copper(struct e1000_hw *hw);
|
||||
s32 igb_phy_init_script_igp3(struct e1000_hw *hw);
|
||||
s32 igb_initialize_M88E1512_phy(struct e1000_hw *hw);
|
||||
s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
|
||||
s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
|
||||
s32 igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data);
|
||||
|
|
|
|||
|
|
@ -104,6 +104,8 @@
|
|||
#define E1000_TRGTTIMH0 0x0B648 /* Target Time Register 0 High - RW */
|
||||
#define E1000_TRGTTIML1 0x0B64C /* Target Time Register 1 Low - RW */
|
||||
#define E1000_TRGTTIMH1 0x0B650 /* Target Time Register 1 High - RW */
|
||||
#define E1000_FREQOUT0 0x0B654 /* Frequency Out 0 Control Register - RW */
|
||||
#define E1000_FREQOUT1 0x0B658 /* Frequency Out 1 Control Register - RW */
|
||||
#define E1000_AUXSTMPL0 0x0B65C /* Auxiliary Time Stamp 0 Register Low - RO */
|
||||
#define E1000_AUXSTMPH0 0x0B660 /* Auxiliary Time Stamp 0 Register High - RO */
|
||||
#define E1000_AUXSTMPL1 0x0B664 /* Auxiliary Time Stamp 1 Register Low - RO */
|
||||
|
|
|
|||
|
|
@ -540,6 +540,7 @@ void igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector, unsigned char *va,
|
|||
struct sk_buff *skb);
|
||||
int igb_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr);
|
||||
int igb_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr);
|
||||
void igb_set_flag_queue_pairs(struct igb_adapter *, const u32);
|
||||
#ifdef CONFIG_IGB_HWMON
|
||||
void igb_sysfs_exit(struct igb_adapter *adapter);
|
||||
int igb_sysfs_init(struct igb_adapter *adapter);
|
||||
|
|
|
|||
|
|
@ -3008,6 +3008,7 @@ static int igb_set_channels(struct net_device *netdev,
|
|||
{
|
||||
struct igb_adapter *adapter = netdev_priv(netdev);
|
||||
unsigned int count = ch->combined_count;
|
||||
unsigned int max_combined = 0;
|
||||
|
||||
/* Verify they are not requesting separate vectors */
|
||||
if (!count || ch->rx_count || ch->tx_count)
|
||||
|
|
@ -3018,11 +3019,13 @@ static int igb_set_channels(struct net_device *netdev,
|
|||
return -EINVAL;
|
||||
|
||||
/* Verify the number of channels doesn't exceed hw limits */
|
||||
if (count > igb_max_channels(adapter))
|
||||
max_combined = igb_max_channels(adapter);
|
||||
if (count > max_combined)
|
||||
return -EINVAL;
|
||||
|
||||
if (count != adapter->rss_queues) {
|
||||
adapter->rss_queues = count;
|
||||
igb_set_flag_queue_pairs(adapter, max_combined);
|
||||
|
||||
/* Hardware has to reinitialize queues and interrupts to
|
||||
* match the new configuration.
|
||||
|
|
|
|||
|
|
@ -179,6 +179,8 @@ static void igb_check_vf_rate_limit(struct igb_adapter *);
|
|||
#ifdef CONFIG_PCI_IOV
|
||||
static int igb_vf_configure(struct igb_adapter *adapter, int vf);
|
||||
static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs);
|
||||
static int igb_disable_sriov(struct pci_dev *dev);
|
||||
static int igb_pci_disable_sriov(struct pci_dev *dev);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
|
|
@ -1205,10 +1207,14 @@ static int igb_alloc_q_vector(struct igb_adapter *adapter,
|
|||
|
||||
/* allocate q_vector and rings */
|
||||
q_vector = adapter->q_vector[v_idx];
|
||||
if (!q_vector)
|
||||
if (!q_vector) {
|
||||
q_vector = kzalloc(size, GFP_KERNEL);
|
||||
else
|
||||
} else if (size > ksize(q_vector)) {
|
||||
kfree_rcu(q_vector, rcu);
|
||||
q_vector = kzalloc(size, GFP_KERNEL);
|
||||
} else {
|
||||
memset(q_vector, 0, size);
|
||||
}
|
||||
if (!q_vector)
|
||||
return -ENOMEM;
|
||||
|
||||
|
|
@ -2645,7 +2651,11 @@ err_eeprom:
|
|||
if (hw->flash_address)
|
||||
iounmap(hw->flash_address);
|
||||
err_sw_init:
|
||||
kfree(adapter->shadow_vfta);
|
||||
igb_clear_interrupt_scheme(adapter);
|
||||
#ifdef CONFIG_PCI_IOV
|
||||
igb_disable_sriov(pdev);
|
||||
#endif
|
||||
pci_iounmap(pdev, hw->hw_addr);
|
||||
err_ioremap:
|
||||
free_netdev(netdev);
|
||||
|
|
@ -2805,14 +2815,14 @@ static void igb_remove(struct pci_dev *pdev)
|
|||
*/
|
||||
igb_release_hw_control(adapter);
|
||||
|
||||
unregister_netdev(netdev);
|
||||
|
||||
igb_clear_interrupt_scheme(adapter);
|
||||
|
||||
#ifdef CONFIG_PCI_IOV
|
||||
igb_disable_sriov(pdev);
|
||||
#endif
|
||||
|
||||
unregister_netdev(netdev);
|
||||
|
||||
igb_clear_interrupt_scheme(adapter);
|
||||
|
||||
pci_iounmap(pdev, hw->hw_addr);
|
||||
if (hw->flash_address)
|
||||
iounmap(hw->flash_address);
|
||||
|
|
@ -2847,7 +2857,7 @@ static void igb_probe_vfs(struct igb_adapter *adapter)
|
|||
return;
|
||||
|
||||
pci_sriov_set_totalvfs(pdev, 7);
|
||||
igb_pci_enable_sriov(pdev, max_vfs);
|
||||
igb_enable_sriov(pdev, max_vfs);
|
||||
|
||||
#endif /* CONFIG_PCI_IOV */
|
||||
}
|
||||
|
|
@ -2888,6 +2898,14 @@ static void igb_init_queue_configuration(struct igb_adapter *adapter)
|
|||
|
||||
adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
|
||||
|
||||
igb_set_flag_queue_pairs(adapter, max_rss_queues);
|
||||
}
|
||||
|
||||
void igb_set_flag_queue_pairs(struct igb_adapter *adapter,
|
||||
const u32 max_rss_queues)
|
||||
{
|
||||
struct e1000_hw *hw = &adapter->hw;
|
||||
|
||||
/* Determine if we need to pair queues. */
|
||||
switch (hw->mac.type) {
|
||||
case e1000_82575:
|
||||
|
|
@ -2968,6 +2986,8 @@ static int igb_sw_init(struct igb_adapter *adapter)
|
|||
}
|
||||
#endif /* CONFIG_PCI_IOV */
|
||||
|
||||
igb_probe_vfs(adapter);
|
||||
|
||||
igb_init_queue_configuration(adapter);
|
||||
|
||||
/* Setup and initialize a copy of the hw vlan table array */
|
||||
|
|
@ -2980,8 +3000,6 @@ static int igb_sw_init(struct igb_adapter *adapter)
|
|||
return -ENOMEM;
|
||||
}
|
||||
|
||||
igb_probe_vfs(adapter);
|
||||
|
||||
/* Explicitly disable IRQ since the NIC can be in any state. */
|
||||
igb_irq_disable(adapter);
|
||||
|
||||
|
|
@ -7401,6 +7419,7 @@ static int igb_resume(struct device *dev)
|
|||
|
||||
if (igb_init_interrupt_scheme(adapter, true)) {
|
||||
dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
|
||||
rtnl_unlock();
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
|
|
@ -7494,6 +7513,7 @@ static int igb_sriov_reinit(struct pci_dev *dev)
|
|||
igb_init_queue_configuration(adapter);
|
||||
|
||||
if (igb_init_interrupt_scheme(adapter, true)) {
|
||||
rtnl_unlock();
|
||||
dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -405,7 +405,7 @@ static void igb_pin_extts(struct igb_adapter *igb, int chan, int pin)
|
|||
wr32(E1000_CTRL_EXT, ctrl_ext);
|
||||
}
|
||||
|
||||
static void igb_pin_perout(struct igb_adapter *igb, int chan, int pin)
|
||||
static void igb_pin_perout(struct igb_adapter *igb, int chan, int pin, int freq)
|
||||
{
|
||||
static const u32 aux0_sel_sdp[IGB_N_SDP] = {
|
||||
AUX0_SEL_SDP0, AUX0_SEL_SDP1, AUX0_SEL_SDP2, AUX0_SEL_SDP3,
|
||||
|
|
@ -424,6 +424,14 @@ static void igb_pin_perout(struct igb_adapter *igb, int chan, int pin)
|
|||
TS_SDP0_SEL_TT1, TS_SDP1_SEL_TT1,
|
||||
TS_SDP2_SEL_TT1, TS_SDP3_SEL_TT1,
|
||||
};
|
||||
static const u32 ts_sdp_sel_fc0[IGB_N_SDP] = {
|
||||
TS_SDP0_SEL_FC0, TS_SDP1_SEL_FC0,
|
||||
TS_SDP2_SEL_FC0, TS_SDP3_SEL_FC0,
|
||||
};
|
||||
static const u32 ts_sdp_sel_fc1[IGB_N_SDP] = {
|
||||
TS_SDP0_SEL_FC1, TS_SDP1_SEL_FC1,
|
||||
TS_SDP2_SEL_FC1, TS_SDP3_SEL_FC1,
|
||||
};
|
||||
static const u32 ts_sdp_sel_clr[IGB_N_SDP] = {
|
||||
TS_SDP0_SEL_FC1, TS_SDP1_SEL_FC1,
|
||||
TS_SDP2_SEL_FC1, TS_SDP3_SEL_FC1,
|
||||
|
|
@ -445,11 +453,17 @@ static void igb_pin_perout(struct igb_adapter *igb, int chan, int pin)
|
|||
tssdp &= ~AUX1_TS_SDP_EN;
|
||||
|
||||
tssdp &= ~ts_sdp_sel_clr[pin];
|
||||
if (chan == 1)
|
||||
tssdp |= ts_sdp_sel_tt1[pin];
|
||||
else
|
||||
tssdp |= ts_sdp_sel_tt0[pin];
|
||||
|
||||
if (freq) {
|
||||
if (chan == 1)
|
||||
tssdp |= ts_sdp_sel_fc1[pin];
|
||||
else
|
||||
tssdp |= ts_sdp_sel_fc0[pin];
|
||||
} else {
|
||||
if (chan == 1)
|
||||
tssdp |= ts_sdp_sel_tt1[pin];
|
||||
else
|
||||
tssdp |= ts_sdp_sel_tt0[pin];
|
||||
}
|
||||
tssdp |= ts_sdp_en[pin];
|
||||
|
||||
wr32(E1000_TSSDP, tssdp);
|
||||
|
|
@ -463,10 +477,10 @@ static int igb_ptp_feature_enable_i210(struct ptp_clock_info *ptp,
|
|||
struct igb_adapter *igb =
|
||||
container_of(ptp, struct igb_adapter, ptp_caps);
|
||||
struct e1000_hw *hw = &igb->hw;
|
||||
u32 tsauxc, tsim, tsauxc_mask, tsim_mask, trgttiml, trgttimh;
|
||||
u32 tsauxc, tsim, tsauxc_mask, tsim_mask, trgttiml, trgttimh, freqout;
|
||||
unsigned long flags;
|
||||
struct timespec ts;
|
||||
int pin = -1;
|
||||
int use_freq = 0, pin = -1;
|
||||
s64 ns;
|
||||
|
||||
switch (rq->type) {
|
||||
|
|
@ -511,40 +525,58 @@ static int igb_ptp_feature_enable_i210(struct ptp_clock_info *ptp,
|
|||
ts.tv_nsec = rq->perout.period.nsec;
|
||||
ns = timespec_to_ns(&ts);
|
||||
ns = ns >> 1;
|
||||
if (on && ns < 500000LL) {
|
||||
/* 2k interrupts per second is an awful lot. */
|
||||
return -EINVAL;
|
||||
if (on && ns <= 70000000LL) {
|
||||
if (ns < 8LL)
|
||||
return -EINVAL;
|
||||
use_freq = 1;
|
||||
}
|
||||
ts = ns_to_timespec(ns);
|
||||
if (rq->perout.index == 1) {
|
||||
tsauxc_mask = TSAUXC_EN_TT1;
|
||||
tsim_mask = TSINTR_TT1;
|
||||
if (use_freq) {
|
||||
tsauxc_mask = TSAUXC_EN_CLK1 | TSAUXC_ST1;
|
||||
tsim_mask = 0;
|
||||
} else {
|
||||
tsauxc_mask = TSAUXC_EN_TT1;
|
||||
tsim_mask = TSINTR_TT1;
|
||||
}
|
||||
trgttiml = E1000_TRGTTIML1;
|
||||
trgttimh = E1000_TRGTTIMH1;
|
||||
freqout = E1000_FREQOUT1;
|
||||
} else {
|
||||
tsauxc_mask = TSAUXC_EN_TT0;
|
||||
tsim_mask = TSINTR_TT0;
|
||||
if (use_freq) {
|
||||
tsauxc_mask = TSAUXC_EN_CLK0 | TSAUXC_ST0;
|
||||
tsim_mask = 0;
|
||||
} else {
|
||||
tsauxc_mask = TSAUXC_EN_TT0;
|
||||
tsim_mask = TSINTR_TT0;
|
||||
}
|
||||
trgttiml = E1000_TRGTTIML0;
|
||||
trgttimh = E1000_TRGTTIMH0;
|
||||
freqout = E1000_FREQOUT0;
|
||||
}
|
||||
spin_lock_irqsave(&igb->tmreg_lock, flags);
|
||||
tsauxc = rd32(E1000_TSAUXC);
|
||||
tsim = rd32(E1000_TSIM);
|
||||
if (rq->perout.index == 1) {
|
||||
tsauxc &= ~(TSAUXC_EN_TT1 | TSAUXC_EN_CLK1 | TSAUXC_ST1);
|
||||
tsim &= ~TSINTR_TT1;
|
||||
} else {
|
||||
tsauxc &= ~(TSAUXC_EN_TT0 | TSAUXC_EN_CLK0 | TSAUXC_ST0);
|
||||
tsim &= ~TSINTR_TT0;
|
||||
}
|
||||
if (on) {
|
||||
int i = rq->perout.index;
|
||||
|
||||
igb_pin_perout(igb, i, pin);
|
||||
igb_pin_perout(igb, i, pin, use_freq);
|
||||
igb->perout[i].start.tv_sec = rq->perout.start.sec;
|
||||
igb->perout[i].start.tv_nsec = rq->perout.start.nsec;
|
||||
igb->perout[i].period.tv_sec = ts.tv_sec;
|
||||
igb->perout[i].period.tv_nsec = ts.tv_nsec;
|
||||
wr32(trgttimh, rq->perout.start.sec);
|
||||
wr32(trgttiml, rq->perout.start.nsec);
|
||||
if (use_freq)
|
||||
wr32(freqout, ns);
|
||||
tsauxc |= tsauxc_mask;
|
||||
tsim |= tsim_mask;
|
||||
} else {
|
||||
tsauxc &= ~tsauxc_mask;
|
||||
tsim &= ~tsim_mask;
|
||||
}
|
||||
wr32(E1000_TSAUXC, tsauxc);
|
||||
wr32(E1000_TSIM, tsim);
|
||||
|
|
|
|||
|
|
@ -319,6 +319,7 @@ static bool igbvf_clean_rx_irq(struct igbvf_adapter *adapter,
|
|||
dma_unmap_single(&pdev->dev, buffer_info->dma,
|
||||
adapter->rx_ps_hdr_size,
|
||||
DMA_FROM_DEVICE);
|
||||
buffer_info->dma = 0;
|
||||
skb_put(skb, hlen);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -248,8 +248,7 @@ static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter,
|
|||
enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
|
||||
struct pci_dev *pdev;
|
||||
|
||||
/* determine whether to use the the parent device
|
||||
*/
|
||||
/* determine whether to use the parent device */
|
||||
if (ixgbe_pcie_from_parent(&adapter->hw))
|
||||
pdev = adapter->pdev->bus->parent->self;
|
||||
else
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*******************************************************************************
|
||||
|
||||
Intel 10 Gigabit PCI Express Linux driver
|
||||
Copyright(c) 1999 - 2014 Intel Corporation.
|
||||
Copyright(c) 1999 - 2015 Intel Corporation.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify it
|
||||
under the terms and conditions of the GNU General Public License,
|
||||
|
|
@ -3462,14 +3462,14 @@ struct ixgbe_info {
|
|||
#define IXGBE_ERR_HOST_INTERFACE_COMMAND -33
|
||||
#define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF
|
||||
|
||||
#define IXGBE_KRM_PORT_CAR_GEN_CTRL(P) ((P == 0) ? (0x4010) : (0x8010))
|
||||
#define IXGBE_KRM_LINK_CTRL_1(P) ((P == 0) ? (0x420C) : (0x820C))
|
||||
#define IXGBE_KRM_DSP_TXFFE_STATE_4(P) ((P == 0) ? (0x4634) : (0x8634))
|
||||
#define IXGBE_KRM_DSP_TXFFE_STATE_5(P) ((P == 0) ? (0x4638) : (0x8638))
|
||||
#define IXGBE_KRM_RX_TRN_LINKUP_CTRL(P) ((P == 0) ? (0x4B00) : (0x8B00))
|
||||
#define IXGBE_KRM_PMD_DFX_BURNIN(P) ((P == 0) ? (0x4E00) : (0x8E00))
|
||||
#define IXGBE_KRM_TX_COEFF_CTRL_1(P) ((P == 0) ? (0x5520) : (0x9520))
|
||||
#define IXGBE_KRM_RX_ANA_CTL(P) ((P == 0) ? (0x5A00) : (0x9A00))
|
||||
#define IXGBE_KRM_PORT_CAR_GEN_CTRL(P) ((P) ? 0x8010 : 0x4010)
|
||||
#define IXGBE_KRM_LINK_CTRL_1(P) ((P) ? 0x820C : 0x420C)
|
||||
#define IXGBE_KRM_DSP_TXFFE_STATE_4(P) ((P) ? 0x8634 : 0x4634)
|
||||
#define IXGBE_KRM_DSP_TXFFE_STATE_5(P) ((P) ? 0x8638 : 0x4638)
|
||||
#define IXGBE_KRM_RX_TRN_LINKUP_CTRL(P) ((P) ? 0x8B00 : 0x4B00)
|
||||
#define IXGBE_KRM_PMD_DFX_BURNIN(P) ((P) ? 0x8E00 : 0x4E00)
|
||||
#define IXGBE_KRM_TX_COEFF_CTRL_1(P) ((P) ? 0x9520 : 0x5520)
|
||||
#define IXGBE_KRM_RX_ANA_CTL(P) ((P) ? 0x9A00 : 0x5A00)
|
||||
|
||||
#define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B (1 << 9)
|
||||
#define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS (1 << 11)
|
||||
|
|
|
|||
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