atmel_spi: don't always deselect chip between messages
Update chipselect handling for atmel_spi:
* Teach it how to leave chipselect active between messages; this
helps various drivers work better.
* Cope with at91rm0200 errata: nCS0 can't be managed with GPIOs.
The MR.PCS value is now updated whenever a chipselect changes.
(This requires SPI pinmux init for that controller to change,
and also testing on rm9200; doesn't break at91sam9 or avr32.)
* Fix minor glitches: spi_setup() must leave chipselects inactive,
as must removal of the spi_device.
Also tweak diagnostic messaging to be a bit more useful.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Acked-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
David Brownell
Linus Torvalds
Родитель
8da0859a24
Коммит
defbd3b4bb
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@ -46,6 +46,7 @@ struct atmel_spi {
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struct clk *clk;
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struct platform_device *pdev;
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unsigned new_1:1;
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struct spi_device *stay;
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u8 stopping;
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struct list_head queue;
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@ -62,29 +63,62 @@ struct atmel_spi {
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/*
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* Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
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* they assume that spi slave device state will not change on deselect, so
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* that automagic deselection is OK. Not so! Workaround uses nCSx pins
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* as GPIOs; or newer controllers have CSAAT and friends.
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* that automagic deselection is OK. ("NPCSx rises if no data is to be
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* transmitted") Not so! Workaround uses nCSx pins as GPIOs; or newer
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* controllers have CSAAT and friends.
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*
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* Since the CSAAT functionality is a bit weird on newer controllers
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* as well, we use GPIO to control nCSx pins on all controllers.
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* Since the CSAAT functionality is a bit weird on newer controllers as
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* well, we use GPIO to control nCSx pins on all controllers, updating
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* MR.PCS to avoid confusing the controller. Using GPIOs also lets us
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* support active-high chipselects despite the controller's belief that
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* only active-low devices/systems exists.
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*
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* However, at91rm9200 has a second erratum whereby nCS0 doesn't work
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* right when driven with GPIO. ("Mode Fault does not allow more than one
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* Master on Chip Select 0.") No workaround exists for that ... so for
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* nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH,
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* and (c) will trigger that first erratum in some cases.
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*/
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static inline void cs_activate(struct spi_device *spi)
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static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
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{
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unsigned gpio = (unsigned) spi->controller_data;
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unsigned active = spi->mode & SPI_CS_HIGH;
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u32 mr;
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dev_dbg(&spi->dev, "activate %u%s\n", gpio, active ? " (high)" : "");
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gpio_set_value(gpio, active);
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mr = spi_readl(as, MR);
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mr = SPI_BFINS(PCS, ~(1 << spi->chip_select), mr);
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dev_dbg(&spi->dev, "activate %u%s, mr %08x\n",
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gpio, active ? " (high)" : "",
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mr);
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if (!(cpu_is_at91rm9200() && spi->chip_select == 0))
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gpio_set_value(gpio, active);
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spi_writel(as, MR, mr);
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}
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static inline void cs_deactivate(struct spi_device *spi)
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static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)
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{
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unsigned gpio = (unsigned) spi->controller_data;
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unsigned active = spi->mode & SPI_CS_HIGH;
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u32 mr;
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dev_dbg(&spi->dev, "DEactivate %u%s\n", gpio, active ? " (low)" : "");
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gpio_set_value(gpio, !active);
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/* only deactivate *this* device; sometimes transfers to
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* another device may be active when this routine is called.
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*/
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mr = spi_readl(as, MR);
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if (~SPI_BFEXT(PCS, mr) & (1 << spi->chip_select)) {
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mr = SPI_BFINS(PCS, 0xf, mr);
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spi_writel(as, MR, mr);
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}
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dev_dbg(&spi->dev, "DEactivate %u%s, mr %08x\n",
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gpio, active ? " (low)" : "",
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mr);
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if (!(cpu_is_at91rm9200() && spi->chip_select == 0))
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gpio_set_value(gpio, !active);
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}
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/*
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@ -140,6 +174,7 @@ static void atmel_spi_next_xfer(struct spi_master *master,
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/* REVISIT: when xfer->delay_usecs == 0, the PDC "next transfer"
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* mechanism might help avoid the IRQ latency between transfers
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* (and improve the nCS0 errata handling on at91rm9200 chips)
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*
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* We're also waiting for ENDRX before we start the next
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* transfer because we need to handle some difficult timing
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@ -169,17 +204,25 @@ static void atmel_spi_next_message(struct spi_master *master)
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{
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struct atmel_spi *as = spi_master_get_devdata(master);
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struct spi_message *msg;
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u32 mr;
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struct spi_device *spi;
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BUG_ON(as->current_transfer);
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msg = list_entry(as->queue.next, struct spi_message, queue);
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spi = msg->spi;
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/* Select the chip */
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mr = spi_readl(as, MR);
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mr = SPI_BFINS(PCS, ~(1 << msg->spi->chip_select), mr);
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spi_writel(as, MR, mr);
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cs_activate(msg->spi);
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dev_dbg(master->cdev.dev, "start message %p for %s\n",
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msg, spi->dev.bus_id);
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/* select chip if it's not still active */
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if (as->stay) {
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if (as->stay != spi) {
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cs_deactivate(as, as->stay);
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cs_activate(as, spi);
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}
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as->stay = NULL;
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} else
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cs_activate(as, spi);
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atmel_spi_next_xfer(master, msg);
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}
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@ -232,9 +275,13 @@ static void atmel_spi_dma_unmap_xfer(struct spi_master *master,
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static void
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atmel_spi_msg_done(struct spi_master *master, struct atmel_spi *as,
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struct spi_message *msg, int status)
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struct spi_message *msg, int status, int stay)
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{
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cs_deactivate(msg->spi);
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if (!stay || status < 0)
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cs_deactivate(as, msg->spi);
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else
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as->stay = msg->spi;
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list_del(&msg->queue);
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msg->status = status;
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@ -324,7 +371,7 @@ atmel_spi_interrupt(int irq, void *dev_id)
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/* Clear any overrun happening while cleaning up */
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spi_readl(as, SR);
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atmel_spi_msg_done(master, as, msg, -EIO);
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atmel_spi_msg_done(master, as, msg, -EIO, 0);
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} else if (pending & SPI_BIT(ENDRX)) {
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ret = IRQ_HANDLED;
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@ -342,12 +389,13 @@ atmel_spi_interrupt(int irq, void *dev_id)
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if (msg->transfers.prev == &xfer->transfer_list) {
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/* report completed message */
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atmel_spi_msg_done(master, as, msg, 0);
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atmel_spi_msg_done(master, as, msg, 0,
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xfer->cs_change);
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} else {
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if (xfer->cs_change) {
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cs_deactivate(msg->spi);
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cs_deactivate(as, msg->spi);
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udelay(1);
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cs_activate(msg->spi);
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cs_activate(as, msg->spi);
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}
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/*
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@ -410,6 +458,14 @@ static int atmel_spi_setup(struct spi_device *spi)
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return -EINVAL;
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}
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/* see notes above re chipselect */
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if (cpu_is_at91rm9200()
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&& spi->chip_select == 0
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&& (spi->mode & SPI_CS_HIGH)) {
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dev_dbg(&spi->dev, "setup: can't be active-high\n");
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return -EINVAL;
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}
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/* speed zero convention is used by some upper layers */
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bus_hz = clk_get_rate(as->clk);
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if (spi->max_speed_hz) {
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@ -446,6 +502,14 @@ static int atmel_spi_setup(struct spi_device *spi)
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return ret;
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spi->controller_state = (void *)npcs_pin;
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gpio_direction_output(npcs_pin, !(spi->mode & SPI_CS_HIGH));
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} else {
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unsigned long flags;
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spin_lock_irqsave(&as->lock, flags);
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if (as->stay == spi)
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as->stay = NULL;
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cs_deactivate(as, spi);
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spin_unlock_irqrestore(&as->lock, flags);
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}
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dev_dbg(&spi->dev,
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@ -502,6 +566,7 @@ static int atmel_spi_transfer(struct spi_device *spi, struct spi_message *msg)
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}
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}
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#ifdef VERBOSE
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list_for_each_entry(xfer, &msg->transfers, transfer_list) {
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dev_dbg(controller,
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" xfer %p: len %u tx %p/%08x rx %p/%08x\n",
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@ -509,6 +574,7 @@ static int atmel_spi_transfer(struct spi_device *spi, struct spi_message *msg)
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xfer->tx_buf, xfer->tx_dma,
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xfer->rx_buf, xfer->rx_dma);
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}
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#endif
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msg->status = -EINPROGRESS;
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msg->actual_length = 0;
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@ -524,8 +590,21 @@ static int atmel_spi_transfer(struct spi_device *spi, struct spi_message *msg)
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static void atmel_spi_cleanup(struct spi_device *spi)
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{
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if (spi->controller_state)
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gpio_free((unsigned int)spi->controller_data);
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struct atmel_spi *as = spi_master_get_devdata(spi->master);
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unsigned gpio = (unsigned) spi->controller_data;
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unsigned long flags;
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if (!spi->controller_state)
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return;
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spin_lock_irqsave(&as->lock, flags);
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if (as->stay == spi) {
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as->stay = NULL;
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cs_deactivate(as, spi);
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}
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spin_unlock_irqrestore(&as->lock, flags);
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gpio_free(gpio);
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}
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/*-------------------------------------------------------------------------*/
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