parisc architecture fixes and updates for kernel v6.0-rc3:
* Fix emulation of fldw instruction on unaligned addresses * Fix "make ARCH=parisc64 randconfig" to return a 64-bit config * Prevent boot if trying to boot a 32-bit kernel compiled for PA8X00 CPUs on 32-bit only machines * ccio-dma: Handle kmalloc failure in ccio_init_resources() -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQS86RI+GtKfB8BJu973ErUQojoPXwUCYwSs6AAKCRD3ErUQojoP X4Q5AQCHIg0vlkbDD8ckaCLMzQDnTUOhXzWjcuYRWnxQHJGE7gEAoLBtynPMLi4M J80exkaguje8XoAcROSqxNMYbsIQDgU= =CZXx -----END PGP SIGNATURE----- Merge tag 'parisc-for-6.0-2' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux Pull parisc fixes from Helge Deller: "Some interesting background to the current patchset: It turned out that the fldw instruction (which loads a 32-bit word from memory into one half of a FP register) failed on unaligned addresses and even trashed some other random FP register instead. It's a trivial one-liner fix in the exception handler but this failure dates back to the very beginnings of the parisc-port. It's strange that it was never noticed before. Another patch fixes an annoyance noticed by Randy Dunlap. Running "make ARCH=parisc64 randconfig" always returned a 32-bit config, although one would expect a 64-bit config. Masahiro Yamada suggested to mimik sparc Kconfig code, which fixed the issue nicely. This allowed to drop some compiler build checks too. Third, it's possible to build an optimized 32-bit kernel for PA8X00 (64-bit) CPUs, which then wouldn't start on 32-bit-only (PA1.x) machines. I've added a bootup check which prevents that and which prints a message to the console. This can be tested with qemu, which currently only supports 32-bit emulation. The other patches are usual clean-up stuff like added return value checks and typo fixes in comments. Summary: - Fix emulation of fldw instruction on unaligned addresses - Fix "make ARCH=parisc64 randconfig" to return a 64-bit config - Prevent boot if trying to boot a 32-bit kernel compiled for PA8X00 CPUs on 32-bit only machines - ccio-dma: Handle kmalloc failure in ccio_init_resources()" * tag 'parisc-for-6.0-2' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux: parisc: Add runtime check to prevent PA2.0 kernels on PA1.x machines parisc: ccio-dma: Handle kmalloc failure in ccio_init_resources() parisc: led: Move from strlcpy with unused retval to strscpy parisc: ccio-dma: Fix typo in comment Revert "parisc: Show error if wrong 32/64-bit compiler is being used" parisc: Make CONFIG_64BIT available for ARCH=parisc64 only parisc: Fix exception handler for fldw and fstw instructions
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Коммит
df0219d11b
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@ -146,10 +146,10 @@ menu "Processor type and features"
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choice
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prompt "Processor type"
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default PA7000
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default PA7000 if "$(ARCH)" = "parisc"
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config PA7000
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bool "PA7000/PA7100"
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bool "PA7000/PA7100" if "$(ARCH)" = "parisc"
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help
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This is the processor type of your CPU. This information is
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used for optimizing purposes. In order to compile a kernel
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@ -160,21 +160,21 @@ config PA7000
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which is required on some machines.
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config PA7100LC
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bool "PA7100LC"
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bool "PA7100LC" if "$(ARCH)" = "parisc"
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help
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Select this option for the PCX-L processor, as used in the
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712, 715/64, 715/80, 715/100, 715/100XC, 725/100, 743, 748,
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D200, D210, D300, D310 and E-class
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config PA7200
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bool "PA7200"
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bool "PA7200" if "$(ARCH)" = "parisc"
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help
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Select this option for the PCX-T' processor, as used in the
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C100, C110, J100, J110, J210XC, D250, D260, D350, D360,
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K100, K200, K210, K220, K400, K410 and K420
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config PA7300LC
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bool "PA7300LC"
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bool "PA7300LC" if "$(ARCH)" = "parisc"
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help
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Select this option for the PCX-L2 processor, as used in the
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744, A180, B132L, B160L, B180L, C132L, C160L, C180L,
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@ -224,17 +224,8 @@ config MLONGCALLS
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Enabling this option will probably slow down your kernel.
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config 64BIT
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bool "64-bit kernel"
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def_bool "$(ARCH)" = "parisc64"
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depends on PA8X00
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help
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Enable this if you want to support 64bit kernel on PA-RISC platform.
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At the moment, only people willing to use more than 2GB of RAM,
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or having a 64bit-only capable PA-RISC machine should say Y here.
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Since there is no 64bit userland on PA-RISC, there is no point to
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enable this option otherwise. The 64bit kernel is significantly bigger
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and slower than the 32bit one.
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choice
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prompt "Kernel page size"
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@ -12,14 +12,6 @@
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#include <asm/barrier.h>
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#include <linux/atomic.h>
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/* compiler build environment sanity checks: */
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#if !defined(CONFIG_64BIT) && defined(__LP64__)
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#error "Please use 'ARCH=parisc' to build the 32-bit kernel."
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#endif
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#if defined(CONFIG_64BIT) && !defined(__LP64__)
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#error "Please use 'ARCH=parisc64' to build the 64-bit kernel."
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#endif
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/* See http://marc.theaimsgroup.com/?t=108826637900003 for discussion
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* on use of volatile and __*_bit() (set/clear/change):
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* *_bit() want use of volatile.
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@ -22,7 +22,7 @@
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#include <linux/init.h>
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#include <linux/pgtable.h>
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.level PA_ASM_LEVEL
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.level 1.1
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__INITDATA
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ENTRY(boot_args)
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@ -70,6 +70,47 @@ $bss_loop:
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stw,ma %arg2,4(%r1)
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stw,ma %arg3,4(%r1)
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#if !defined(CONFIG_64BIT) && defined(CONFIG_PA20)
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/* This 32-bit kernel was compiled for PA2.0 CPUs. Check current CPU
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* and halt kernel if we detect a PA1.x CPU. */
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ldi 32,%r10
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mtctl %r10,%cr11
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.level 2.0
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mfctl,w %cr11,%r10
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.level 1.1
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comib,<>,n 0,%r10,$cpu_ok
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load32 PA(msg1),%arg0
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ldi msg1_end-msg1,%arg1
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$iodc_panic:
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copy %arg0, %r10
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copy %arg1, %r11
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load32 PA(init_stack),%sp
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#define MEM_CONS 0x3A0
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ldw MEM_CONS+32(%r0),%arg0 // HPA
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ldi ENTRY_IO_COUT,%arg1
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ldw MEM_CONS+36(%r0),%arg2 // SPA
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ldw MEM_CONS+8(%r0),%arg3 // layers
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load32 PA(__bss_start),%r1
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stw %r1,-52(%sp) // arg4
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stw %r0,-56(%sp) // arg5
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stw %r10,-60(%sp) // arg6 = ptr to text
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stw %r11,-64(%sp) // arg7 = len
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stw %r0,-68(%sp) // arg8
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load32 PA(.iodc_panic_ret), %rp
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ldw MEM_CONS+40(%r0),%r1 // ENTRY_IODC
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bv,n (%r1)
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.iodc_panic_ret:
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b . /* wait endless with ... */
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or %r10,%r10,%r10 /* qemu idle sleep */
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msg1: .ascii "Can't boot kernel which was built for PA8x00 CPUs on this machine.\r\n"
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msg1_end:
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$cpu_ok:
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#endif
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.level PA_ASM_LEVEL
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/* Initialize startup VM. Just map first 16/32 MB of memory */
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load32 PA(swapper_pg_dir),%r4
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mtctl %r4,%cr24 /* Initialize kernel root pointer */
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@ -93,7 +93,7 @@
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#define R1(i) (((i)>>21)&0x1f)
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#define R2(i) (((i)>>16)&0x1f)
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#define R3(i) ((i)&0x1f)
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#define FR3(i) ((((i)<<1)&0x1f)|(((i)>>6)&1))
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#define FR3(i) ((((i)&0x1f)<<1)|(((i)>>6)&1))
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#define IM(i,n) (((i)>>1&((1<<(n-1))-1))|((i)&1?((0-1L)<<(n-1)):0))
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#define IM5_2(i) IM((i)>>16,5)
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#define IM5_3(i) IM((i),5)
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@ -268,7 +268,7 @@ static int ioc_count;
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* Each bit can represent a number of pages.
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* LSbs represent lower addresses (IOVA's).
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*
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* This was was copied from sba_iommu.c. Don't try to unify
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* This was copied from sba_iommu.c. Don't try to unify
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* the two resource managers unless a way to have different
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* allocation policies is also adjusted. We'd like to avoid
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* I/O TLB thrashing by having resource allocation policy
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@ -1380,15 +1380,17 @@ ccio_init_resource(struct resource *res, char *name, void __iomem *ioaddr)
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}
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}
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static void __init ccio_init_resources(struct ioc *ioc)
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static int __init ccio_init_resources(struct ioc *ioc)
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{
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struct resource *res = ioc->mmio_region;
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char *name = kmalloc(14, GFP_KERNEL);
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if (unlikely(!name))
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return -ENOMEM;
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snprintf(name, 14, "GSC Bus [%d/]", ioc->hw_path);
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ccio_init_resource(res, name, &ioc->ioc_regs->io_io_low);
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ccio_init_resource(res + 1, name, &ioc->ioc_regs->io_io_low_hv);
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return 0;
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}
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static int new_ioc_area(struct resource *res, unsigned long size,
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return -ENOMEM;
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}
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ccio_ioc_init(ioc);
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ccio_init_resources(ioc);
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if (ccio_init_resources(ioc)) {
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kfree(ioc);
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return -ENOMEM;
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}
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hppa_dma_ops = &ccio_ops;
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hba = kzalloc(sizeof(*hba), GFP_KERNEL);
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@ -646,7 +646,7 @@ int lcd_print( const char *str )
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cancel_delayed_work_sync(&led_task);
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/* copy display string to buffer for procfs */
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strlcpy(lcd_text, str, sizeof(lcd_text));
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strscpy(lcd_text, str, sizeof(lcd_text));
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/* Set LCD Cursor to 1st character */
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gsc_writeb(lcd_info.reset_cmd1, LCD_CMD_REG);
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