imxmmc: use readl/writel
Use readl/writel instead of direct pointer deref. Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Marc Kleine-Budde
Sascha Hauer
Родитель
2507b0a333
Коммит
df25f9da9f
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@ -43,6 +43,7 @@ struct imxmci_host {
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struct mmc_host *mmc;
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spinlock_t lock;
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struct resource *res;
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void __iomem *base;
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int irq;
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imx_dmach_t dma;
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volatile unsigned int imask;
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@ -98,14 +99,22 @@ struct imxmci_host {
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static void imxmci_stop_clock(struct imxmci_host *host)
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{
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int i = 0;
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MMC_STR_STP_CLK &= ~STR_STP_CLK_START_CLK;
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while (i < 0x1000) {
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if (!(i & 0x7f))
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MMC_STR_STP_CLK |= STR_STP_CLK_STOP_CLK;
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u16 reg;
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if (!(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN)) {
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reg = readw(host->base + MMC_REG_STR_STP_CLK);
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writew(reg & ~STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK);
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while (i < 0x1000) {
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if (!(i & 0x7f)) {
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reg = readw(host->base + MMC_REG_STR_STP_CLK);
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writew(reg | STR_STP_CLK_STOP_CLK,
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host->base + MMC_REG_STR_STP_CLK);
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}
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reg = readw(host->base + MMC_REG_STATUS);
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if (!(reg & STATUS_CARD_BUS_CLK_RUN)) {
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/* Check twice before cut */
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if (!(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN))
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reg = readw(host->base + MMC_REG_STATUS);
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if (!(reg & STATUS_CARD_BUS_CLK_RUN))
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return;
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}
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@ -119,8 +128,10 @@ static int imxmci_start_clock(struct imxmci_host *host)
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unsigned int trials = 0;
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unsigned int delay_limit = 128;
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unsigned long flags;
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u16 reg;
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MMC_STR_STP_CLK &= ~STR_STP_CLK_STOP_CLK;
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reg = readw(host->base + MMC_REG_STR_STP_CLK);
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writew(reg & ~STR_STP_CLK_STOP_CLK, host->base + MMC_REG_STR_STP_CLK);
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clear_bit(IMXMCI_PEND_STARTED_b, &host->pending_events);
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@ -129,15 +140,18 @@ static int imxmci_start_clock(struct imxmci_host *host)
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* then 6 delay loops, but during card detection (low clockrate)
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* it takes up to 5000 delay loops and sometimes fails for the first time
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*/
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MMC_STR_STP_CLK |= STR_STP_CLK_START_CLK;
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reg = readw(host->base + MMC_REG_STR_STP_CLK);
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writew(reg | STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK);
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do {
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unsigned int delay = delay_limit;
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while (delay--) {
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if (MMC_STATUS & STATUS_CARD_BUS_CLK_RUN)
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reg = readw(host->base + MMC_REG_STATUS);
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if (reg & STATUS_CARD_BUS_CLK_RUN)
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/* Check twice before cut */
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if (MMC_STATUS & STATUS_CARD_BUS_CLK_RUN)
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reg = readw(host->base + MMC_REG_STATUS);
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if (reg & STATUS_CARD_BUS_CLK_RUN)
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return 0;
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if (test_bit(IMXMCI_PEND_STARTED_b, &host->pending_events))
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@ -151,8 +165,11 @@ static int imxmci_start_clock(struct imxmci_host *host)
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* IRQ or schedule delays this function execution and the clocks has
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* been already stopped by other means (response processing, SDHC HW)
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*/
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if (!test_bit(IMXMCI_PEND_STARTED_b, &host->pending_events))
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MMC_STR_STP_CLK |= STR_STP_CLK_START_CLK;
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if (!test_bit(IMXMCI_PEND_STARTED_b, &host->pending_events)) {
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reg = readw(host->base + MMC_REG_STR_STP_CLK);
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writew(reg | STR_STP_CLK_START_CLK,
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host->base + MMC_REG_STR_STP_CLK);
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}
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local_irq_restore(flags);
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} while (++trials < 256);
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@ -162,23 +179,20 @@ static int imxmci_start_clock(struct imxmci_host *host)
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return -1;
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}
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static void imxmci_softreset(void)
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static void imxmci_softreset(struct imxmci_host *host)
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{
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/* reset sequence */
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MMC_STR_STP_CLK = 0x8;
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MMC_STR_STP_CLK = 0xD;
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MMC_STR_STP_CLK = 0x5;
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MMC_STR_STP_CLK = 0x5;
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MMC_STR_STP_CLK = 0x5;
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MMC_STR_STP_CLK = 0x5;
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MMC_STR_STP_CLK = 0x5;
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MMC_STR_STP_CLK = 0x5;
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MMC_STR_STP_CLK = 0x5;
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MMC_STR_STP_CLK = 0x5;
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int i;
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MMC_RES_TO = 0xff;
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MMC_BLK_LEN = 512;
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MMC_NOB = 1;
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/* reset sequence */
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writew(0x08, host->base + MMC_REG_STR_STP_CLK);
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writew(0x0D, host->base + MMC_REG_STR_STP_CLK);
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for (i = 0; i < 8; i++)
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writew(0x05, host->base + MMC_REG_STR_STP_CLK);
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writew(0xff, host->base + MMC_REG_RES_TO);
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writew(512, host->base + MMC_REG_BLK_LEN);
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writew(1, host->base + MMC_REG_NOB);
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}
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static int imxmci_busy_wait_for_status(struct imxmci_host *host,
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@ -195,7 +209,7 @@ static int imxmci_busy_wait_for_status(struct imxmci_host *host,
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return -1;
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}
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udelay(2);
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*pstat |= MMC_STATUS;
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*pstat |= readw(host->base + MMC_REG_STATUS);
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}
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if (!loops)
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return 0;
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@ -220,8 +234,8 @@ static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data)
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host->data = data;
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data->bytes_xfered = 0;
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MMC_NOB = nob;
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MMC_BLK_LEN = blksz;
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writew(nob, host->base + MMC_REG_NOB);
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writew(blksz, host->base + MMC_REG_BLK_LEN);
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/*
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* DMA cannot be used for small block sizes, we have to use CPU driven transfers otherwise.
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@ -237,8 +251,8 @@ static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data)
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host->dma_dir = DMA_FROM_DEVICE;
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/* Hack to enable read SCR */
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MMC_NOB = 1;
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MMC_BLK_LEN = 512;
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writew(1, host->base + MMC_REG_NOB);
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writew(512, host->base + MMC_REG_BLK_LEN);
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} else {
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host->dma_dir = DMA_TO_DEVICE;
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}
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@ -259,7 +273,8 @@ static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data)
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data->sg_len, host->dma_dir);
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imx_dma_setup_sg(host->dma, data->sg, data->sg_len, datasz,
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host->res->start + MMC_BUFFER_ACCESS_OFS, DMA_MODE_READ);
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host->res->start + MMC_REG_BUFFER_ACCESS,
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DMA_MODE_READ);
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/*imx_dma_setup_mem2dev_ccr(host->dma, DMA_MODE_READ, IMX_DMA_WIDTH_16, CCR_REN);*/
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CCR(host->dma) = CCR_DMOD_LINEAR | CCR_DSIZ_32 | CCR_SMOD_FIFO | CCR_SSIZ_16 | CCR_REN;
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@ -270,7 +285,8 @@ static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data)
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data->sg_len, host->dma_dir);
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imx_dma_setup_sg(host->dma, data->sg, data->sg_len, datasz,
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host->res->start + MMC_BUFFER_ACCESS_OFS, DMA_MODE_WRITE);
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host->res->start + MMC_REG_BUFFER_ACCESS,
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DMA_MODE_WRITE);
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/*imx_dma_setup_mem2dev_ccr(host->dma, DMA_MODE_WRITE, IMX_DMA_WIDTH_16, CCR_REN);*/
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CCR(host->dma) = CCR_SMOD_LINEAR | CCR_SSIZ_32 | CCR_DMOD_FIFO | CCR_DSIZ_16 | CCR_REN;
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@ -341,10 +357,10 @@ static void imxmci_start_cmd(struct imxmci_host *host, struct mmc_command *cmd,
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if (host->actual_bus_width == MMC_BUS_WIDTH_4)
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cmdat |= CMD_DAT_CONT_BUS_WIDTH_4;
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MMC_CMD = cmd->opcode;
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MMC_ARGH = cmd->arg >> 16;
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MMC_ARGL = cmd->arg & 0xffff;
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MMC_CMD_DAT_CONT = cmdat;
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writew(cmd->opcode, host->base + MMC_REG_CMD);
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writew(cmd->arg >> 16, host->base + MMC_REG_ARGH);
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writew(cmd->arg & 0xffff, host->base + MMC_REG_ARGL);
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writew(cmdat, host->base + MMC_REG_CMD_DAT_CONT);
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atomic_set(&host->stuck_timeout, 0);
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set_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events);
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@ -363,7 +379,7 @@ static void imxmci_start_cmd(struct imxmci_host *host, struct mmc_command *cmd,
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spin_lock_irqsave(&host->lock, flags);
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host->imask = imask;
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MMC_INT_MASK = host->imask;
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writew(host->imask, host->base + MMC_REG_INT_MASK);
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spin_unlock_irqrestore(&host->lock, flags);
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dev_dbg(mmc_dev(host->mmc), "CMD%02d (0x%02x) mask set to 0x%04x\n",
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@ -382,7 +398,7 @@ static void imxmci_finish_request(struct imxmci_host *host, struct mmc_request *
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IMXMCI_PEND_DMA_DATA_m | IMXMCI_PEND_CPU_DATA_m);
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host->imask = IMXMCI_INT_MASK_DEFAULT;
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MMC_INT_MASK = host->imask;
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writew(host->imask, host->base + MMC_REG_INT_MASK);
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spin_unlock_irqrestore(&host->lock, flags);
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@ -448,14 +464,14 @@ static int imxmci_cmd_done(struct imxmci_host *host, unsigned int stat)
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if (cmd->flags & MMC_RSP_PRESENT) {
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if (cmd->flags & MMC_RSP_136) {
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for (i = 0; i < 4; i++) {
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u32 d = MMC_RES_FIFO & 0xffff;
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u32 e = MMC_RES_FIFO & 0xffff;
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cmd->resp[i] = d << 16 | e;
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a = readw(host->base + MMC_REG_RES_FIFO);
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b = readw(host->base + MMC_REG_RES_FIFO);
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cmd->resp[i] = a << 16 | b;
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}
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} else {
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a = MMC_RES_FIFO & 0xffff;
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b = MMC_RES_FIFO & 0xffff;
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c = MMC_RES_FIFO & 0xffff;
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a = readw(host->base + MMC_REG_RES_FIFO);
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b = readw(host->base + MMC_REG_RES_FIFO);
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c = readw(host->base + MMC_REG_RES_FIFO);
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cmd->resp[0] = a << 24 | b << 8 | c >> 8;
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}
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}
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@ -468,7 +484,7 @@ static int imxmci_cmd_done(struct imxmci_host *host, unsigned int stat)
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/* Wait for FIFO to be empty before starting DMA write */
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stat = MMC_STATUS;
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stat = readw(host->base + MMC_REG_STATUS);
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if (imxmci_busy_wait_for_status(host, &stat,
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STATUS_APPL_BUFF_FE,
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40, "imxmci_cmd_done DMA WR") < 0) {
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@ -558,7 +574,7 @@ static int imxmci_cpu_driven_data(struct imxmci_host *host, unsigned int *pstat)
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for (i = burst_len; i >= 2 ; i -= 2) {
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u16 data;
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data = MMC_BUFFER_ACCESS;
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data = readw(host->base + MMC_REG_BUFFER_ACCESS);
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udelay(10); /* required for clocks < 8MHz*/
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if (host->data_cnt+2 <= host->dma_size) {
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*(host->data_ptr++) = data;
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@ -569,7 +585,7 @@ static int imxmci_cpu_driven_data(struct imxmci_host *host, unsigned int *pstat)
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host->data_cnt += 2;
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}
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stat = MMC_STATUS;
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stat = readw(host->base + MMC_REG_STATUS);
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dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data read %d burst %d STATUS = 0x%x\n",
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host->data_cnt, burst_len, stat);
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@ -603,9 +619,9 @@ static int imxmci_cpu_driven_data(struct imxmci_host *host, unsigned int *pstat)
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}
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for (i = burst_len; i > 0 ; i -= 2)
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MMC_BUFFER_ACCESS = *(host->data_ptr++);
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writew(*(host->data_ptr++), host->base + MMC_REG_BUFFER_ACCESS);
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stat = MMC_STATUS;
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stat = readw(host->base + MMC_REG_STATUS);
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dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data write burst %d STATUS = 0x%x\n",
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burst_len, stat);
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@ -620,7 +636,7 @@ static int imxmci_cpu_driven_data(struct imxmci_host *host, unsigned int *pstat)
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static void imxmci_dma_irq(int dma, void *devid)
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{
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struct imxmci_host *host = devid;
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uint32_t stat = MMC_STATUS;
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u32 stat = readw(host->base + MMC_REG_STATUS);
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atomic_set(&host->stuck_timeout, 0);
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host->status_reg = stat;
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@ -631,10 +647,11 @@ static void imxmci_dma_irq(int dma, void *devid)
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static irqreturn_t imxmci_irq(int irq, void *devid)
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{
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struct imxmci_host *host = devid;
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uint32_t stat = MMC_STATUS;
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u32 stat = readw(host->base + MMC_REG_STATUS);
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int handled = 1;
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MMC_INT_MASK = host->imask | INT_MASK_SDIO | INT_MASK_AUTO_CARD_DETECT;
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writew(host->imask | INT_MASK_SDIO | INT_MASK_AUTO_CARD_DETECT,
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host->base + MMC_REG_INT_MASK);
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atomic_set(&host->stuck_timeout, 0);
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host->status_reg = stat;
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@ -655,7 +672,7 @@ static void imxmci_tasklet_fnc(unsigned long data)
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if (atomic_read(&host->stuck_timeout) > 4) {
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char *what;
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timeout = 1;
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stat = MMC_STATUS;
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stat = readw(host->base + MMC_REG_STATUS);
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host->status_reg = stat;
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if (test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events))
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if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events))
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@ -671,12 +688,20 @@ static void imxmci_tasklet_fnc(unsigned long data)
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else
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what = "???";
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dev_err(mmc_dev(host->mmc), "%s TIMEOUT, hardware stucked STATUS = 0x%04x IMASK = 0x%04x\n",
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what, stat, MMC_INT_MASK);
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dev_err(mmc_dev(host->mmc), "CMD_DAT_CONT = 0x%04x, MMC_BLK_LEN = 0x%04x, MMC_NOB = 0x%04x, DMA_CCR = 0x%08x\n",
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MMC_CMD_DAT_CONT, MMC_BLK_LEN, MMC_NOB, CCR(host->dma));
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dev_err(mmc_dev(host->mmc),
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"%s TIMEOUT, hardware stucked STATUS = 0x%04x IMASK = 0x%04x\n",
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what, stat,
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readw(host->base + MMC_REG_INT_MASK));
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dev_err(mmc_dev(host->mmc),
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"CMD_DAT_CONT = 0x%04x, MMC_BLK_LEN = 0x%04x, MMC_NOB = 0x%04x, DMA_CCR = 0x%08x\n",
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readw(host->base + MMC_REG_CMD_DAT_CONT),
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readw(host->base + MMC_REG_BLK_LEN),
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readw(host->base + MMC_REG_NOB),
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CCR(host->dma));
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dev_err(mmc_dev(host->mmc), "CMD%d, prevCMD%d, bus %d-bit, dma_size = 0x%x\n",
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host->cmd?host->cmd->opcode:0, host->prev_cmd_code, 1 << host->actual_bus_width, host->dma_size);
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host->cmd ? host->cmd->opcode : 0,
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host->prev_cmd_code,
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1 << host->actual_bus_width, host->dma_size);
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}
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if (!host->present || timeout)
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@ -686,7 +711,7 @@ static void imxmci_tasklet_fnc(unsigned long data)
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if (test_bit(IMXMCI_PEND_IRQ_b, &host->pending_events) || timeout) {
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clear_bit(IMXMCI_PEND_IRQ_b, &host->pending_events);
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stat = MMC_STATUS;
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stat = readw(host->base + MMC_REG_STATUS);
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/*
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* This is not required in theory, but there is chance to miss some flag
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* which clears automatically by mask write, FreeScale original code keeps
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@ -711,7 +736,7 @@ static void imxmci_tasklet_fnc(unsigned long data)
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}
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if (test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events)) {
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stat |= MMC_STATUS;
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stat |= readw(host->base + MMC_REG_STATUS);
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if (imxmci_cpu_driven_data(host, &stat)) {
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if (test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events))
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imxmci_cmd_done(host, stat);
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@ -725,7 +750,7 @@ static void imxmci_tasklet_fnc(unsigned long data)
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if (test_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events) &&
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!test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) {
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stat = MMC_STATUS;
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stat = readw(host->base + MMC_REG_STATUS);
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||||
/* Same as above */
|
||||
stat |= host->status_reg;
|
||||
|
||||
|
|
@ -813,6 +838,7 @@ static void imxmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
|
|||
|
||||
if (ios->clock) {
|
||||
unsigned int clk;
|
||||
u16 reg;
|
||||
|
||||
/* The prescaler is 5 for PERCLK2 equal to 96MHz
|
||||
* then 96MHz / 5 = 19.2 MHz
|
||||
|
|
@ -844,17 +870,22 @@ static void imxmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
|
|||
break;
|
||||
}
|
||||
|
||||
MMC_STR_STP_CLK |= STR_STP_CLK_ENABLE; /* enable controller */
|
||||
/* enable controller */
|
||||
reg = readw(host->base + MMC_REG_STR_STP_CLK);
|
||||
writew(reg | STR_STP_CLK_ENABLE,
|
||||
host->base + MMC_REG_STR_STP_CLK);
|
||||
|
||||
imxmci_stop_clock(host);
|
||||
MMC_CLK_RATE = (prescaler << 3) | clk;
|
||||
writew((prescaler << 3) | clk, host->base + MMC_REG_CLK_RATE);
|
||||
/*
|
||||
* Under my understanding, clock should not be started there, because it would
|
||||
* initiate SDHC sequencer and send last or random command into card
|
||||
*/
|
||||
/* imxmci_start_clock(host); */
|
||||
|
||||
dev_dbg(mmc_dev(host->mmc), "MMC_CLK_RATE: 0x%08x\n", MMC_CLK_RATE);
|
||||
dev_dbg(mmc_dev(host->mmc),
|
||||
"MMC_CLK_RATE: 0x%08x\n",
|
||||
readw(host->base + MMC_REG_CLK_RATE));
|
||||
} else {
|
||||
imxmci_stop_clock(host);
|
||||
}
|
||||
|
|
@ -913,6 +944,7 @@ static int imxmci_probe(struct platform_device *pdev)
|
|||
struct imxmci_host *host = NULL;
|
||||
struct resource *r;
|
||||
int ret = 0, irq;
|
||||
u16 rev_no;
|
||||
|
||||
printk(KERN_INFO "i.MX mmc driver\n");
|
||||
|
||||
|
|
@ -921,7 +953,8 @@ static int imxmci_probe(struct platform_device *pdev)
|
|||
if (!r || irq < 0)
|
||||
return -ENXIO;
|
||||
|
||||
if (!request_mem_region(r->start, 0x100, pdev->name))
|
||||
r = request_mem_region(r->start, resource_size(r), pdev->name);
|
||||
if (!r)
|
||||
return -EBUSY;
|
||||
|
||||
mmc = mmc_alloc_host(sizeof(struct imxmci_host), &pdev->dev);
|
||||
|
|
@ -945,6 +978,12 @@ static int imxmci_probe(struct platform_device *pdev)
|
|||
mmc->max_blk_count = 65535;
|
||||
|
||||
host = mmc_priv(mmc);
|
||||
host->base = ioremap(r->start, resource_size(r));
|
||||
if (!host->base) {
|
||||
ret = -ENOMEM;
|
||||
goto out;
|
||||
}
|
||||
|
||||
host->mmc = mmc;
|
||||
host->dma_allocated = 0;
|
||||
host->pdata = pdev->dev.platform_data;
|
||||
|
|
@ -972,18 +1011,20 @@ static int imxmci_probe(struct platform_device *pdev)
|
|||
imx_gpio_mode(PB12_PF_SD_CLK);
|
||||
imx_gpio_mode(PB13_PF_SD_CMD);
|
||||
|
||||
imxmci_softreset();
|
||||
imxmci_softreset(host);
|
||||
|
||||
if (MMC_REV_NO != 0x390) {
|
||||
rev_no = readw(host->base + MMC_REG_REV_NO);
|
||||
if (rev_no != 0x390) {
|
||||
dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n",
|
||||
MMC_REV_NO);
|
||||
readw(host->base + MMC_REG_REV_NO));
|
||||
goto out;
|
||||
}
|
||||
|
||||
MMC_READ_TO = 0x2db4; /* recommended in data sheet */
|
||||
/* recommended in data sheet */
|
||||
writew(0x2db4, host->base + MMC_REG_READ_TO);
|
||||
|
||||
host->imask = IMXMCI_INT_MASK_DEFAULT;
|
||||
MMC_INT_MASK = host->imask;
|
||||
writew(host->imask, host->base + MMC_REG_INT_MASK);
|
||||
|
||||
host->dma = imx_dma_request_by_prio(DRIVER_NAME, DMA_PRIO_LOW);
|
||||
if(host->dma < 0) {
|
||||
|
|
@ -1029,10 +1070,12 @@ out:
|
|||
clk_disable(host->clk);
|
||||
clk_put(host->clk);
|
||||
}
|
||||
if (host->base)
|
||||
iounmap(host->base);
|
||||
}
|
||||
if (mmc)
|
||||
mmc_free_host(mmc);
|
||||
release_mem_region(r->start, 0x100);
|
||||
release_mem_region(r->start, resource_size(r));
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
@ -1051,6 +1094,7 @@ static int imxmci_remove(struct platform_device *pdev)
|
|||
mmc_remove_host(mmc);
|
||||
|
||||
free_irq(host->irq, host);
|
||||
iounmap(host->base);
|
||||
if (host->dma_allocated) {
|
||||
imx_dma_free(host->dma);
|
||||
host->dma_allocated = 0;
|
||||
|
|
@ -1061,7 +1105,7 @@ static int imxmci_remove(struct platform_device *pdev)
|
|||
clk_disable(host->clk);
|
||||
clk_put(host->clk);
|
||||
|
||||
release_mem_region(host->res->start, 0x100);
|
||||
release_mem_region(host->res->start, resource_size(host->res));
|
||||
|
||||
mmc_free_host(mmc);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,24 +1,21 @@
|
|||
#define MMC_REG_STR_STP_CLK 0x00
|
||||
#define MMC_REG_STATUS 0x04
|
||||
#define MMC_REG_CLK_RATE 0x08
|
||||
#define MMC_REG_CMD_DAT_CONT 0x0C
|
||||
#define MMC_REG_RES_TO 0x10
|
||||
#define MMC_REG_READ_TO 0x14
|
||||
#define MMC_REG_BLK_LEN 0x18
|
||||
#define MMC_REG_NOB 0x1C
|
||||
#define MMC_REG_REV_NO 0x20
|
||||
#define MMC_REG_INT_MASK 0x24
|
||||
#define MMC_REG_CMD 0x28
|
||||
#define MMC_REG_ARGH 0x2C
|
||||
#define MMC_REG_ARGL 0x30
|
||||
#define MMC_REG_RES_FIFO 0x34
|
||||
#define MMC_REG_BUFFER_ACCESS 0x38
|
||||
|
||||
# define __REG16(x) (*((volatile u16 *)IO_ADDRESS(x)))
|
||||
|
||||
#define MMC_STR_STP_CLK __REG16(IMX_MMC_BASE + 0x00)
|
||||
#define MMC_STATUS __REG16(IMX_MMC_BASE + 0x04)
|
||||
#define MMC_CLK_RATE __REG16(IMX_MMC_BASE + 0x08)
|
||||
#define MMC_CMD_DAT_CONT __REG16(IMX_MMC_BASE + 0x0C)
|
||||
#define MMC_RES_TO __REG16(IMX_MMC_BASE + 0x10)
|
||||
#define MMC_READ_TO __REG16(IMX_MMC_BASE + 0x14)
|
||||
#define MMC_BLK_LEN __REG16(IMX_MMC_BASE + 0x18)
|
||||
#define MMC_NOB __REG16(IMX_MMC_BASE + 0x1C)
|
||||
#define MMC_REV_NO __REG16(IMX_MMC_BASE + 0x20)
|
||||
#define MMC_INT_MASK __REG16(IMX_MMC_BASE + 0x24)
|
||||
#define MMC_CMD __REG16(IMX_MMC_BASE + 0x28)
|
||||
#define MMC_ARGH __REG16(IMX_MMC_BASE + 0x2C)
|
||||
#define MMC_ARGL __REG16(IMX_MMC_BASE + 0x30)
|
||||
#define MMC_RES_FIFO __REG16(IMX_MMC_BASE + 0x34)
|
||||
#define MMC_BUFFER_ACCESS __REG16(IMX_MMC_BASE + 0x38)
|
||||
#define MMC_BUFFER_ACCESS_OFS 0x38
|
||||
|
||||
|
||||
#define STR_STP_CLK_IPG_CLK_GATE_DIS (1<<15)
|
||||
#define STR_STP_CLK_IPG_PERCLK_GATE_DIS (1<<14)
|
||||
#define STR_STP_CLK_ENDIAN (1<<5)
|
||||
#define STR_STP_CLK_RESET (1<<3)
|
||||
#define STR_STP_CLK_ENABLE (1<<2)
|
||||
|
|
|
|||
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