Merge branch 'drm-rockchip-next-2015-12-28' of https://github.com/markyzq/kernel-drm-rockchip into drm-next
These patches convert drm/rockchip to atomic API and add rk3036 vop support. * 'drm-rockchip-next-2015-12-28' of https://github.com/markyzq/kernel-drm-rockchip: dt-bindings: add document for rk3036-vop drm/rockchip: vop: add rk3036 vop support drm/rockchip: vop: spilt scale regsters drm/rockchip: vop: spilt register related into rockchip_reg_vop.c drm/rockchip: vop: move interrupt registers into vop_data drm/rockchip: vop: merge vop cfg_done into vop_data drm/rockchip: dw_hdmi: use encoder enable function drm: bridge/dw_hdmi: add atomic API support drm/rockchip: direct config connecter gate and out_mode drm/rockchip: support atomic asynchronous commit drm/rockchip: Optimization vop mode set drm/rockchip: Convert to support atomic API drm/rockchip: vop: replace dpms with enable/disable drm/rockchip: Use new vblank api drm_crtc_vblank_*
This commit is contained in:
Dave Airlie
Коммит
df83690ec2
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@ -7,6 +7,7 @@ buffer to an external LCD interface.
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Required properties:
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- compatible: value should be one of the following
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"rockchip,rk3288-vop";
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"rockchip,rk3036-vop";
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- interrupts: should contain a list of all VOP IP block interrupts in the
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order: VSYNC, LCD_SYSTEM. The interrupt specifier
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@ -22,6 +22,7 @@
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#include <drm/drm_of.h>
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#include <drm/drmP.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/drm_edid.h>
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#include <drm/drm_encoder_slave.h>
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@ -1522,6 +1523,17 @@ static const struct drm_connector_funcs dw_hdmi_connector_funcs = {
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.force = dw_hdmi_connector_force,
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};
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static const struct drm_connector_funcs dw_hdmi_atomic_connector_funcs = {
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.dpms = drm_atomic_helper_connector_dpms,
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.fill_modes = drm_helper_probe_single_connector_modes,
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.detect = dw_hdmi_connector_detect,
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.destroy = dw_hdmi_connector_destroy,
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.force = dw_hdmi_connector_force,
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.reset = drm_atomic_helper_connector_reset,
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.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
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.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
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};
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static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
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.get_modes = dw_hdmi_connector_get_modes,
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.mode_valid = dw_hdmi_connector_mode_valid,
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@ -1645,8 +1657,15 @@ static int dw_hdmi_register(struct drm_device *drm, struct dw_hdmi *hdmi)
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drm_connector_helper_add(&hdmi->connector,
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&dw_hdmi_connector_helper_funcs);
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drm_connector_init(drm, &hdmi->connector, &dw_hdmi_connector_funcs,
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DRM_MODE_CONNECTOR_HDMIA);
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if (drm_core_check_feature(drm, DRIVER_ATOMIC))
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drm_connector_init(drm, &hdmi->connector,
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&dw_hdmi_atomic_connector_funcs,
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DRM_MODE_CONNECTOR_HDMIA);
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else
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drm_connector_init(drm, &hdmi->connector,
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&dw_hdmi_connector_funcs,
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DRM_MODE_CONNECTOR_HDMIA);
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hdmi->connector.encoder = encoder;
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@ -7,4 +7,5 @@ rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o rockchip_drm_fbdev.o \
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obj-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
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obj-$(CONFIG_DRM_ROCKCHIP) += rockchipdrm.o rockchip_drm_vop.o
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obj-$(CONFIG_DRM_ROCKCHIP) += rockchipdrm.o rockchip_drm_vop.o \
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rockchip_vop_reg.o
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@ -195,12 +195,15 @@ static void dw_hdmi_rockchip_encoder_mode_set(struct drm_encoder *encoder,
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{
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}
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static void dw_hdmi_rockchip_encoder_commit(struct drm_encoder *encoder)
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static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder)
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{
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struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
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u32 val;
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int mux;
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rockchip_drm_crtc_mode_config(encoder->crtc, DRM_MODE_CONNECTOR_HDMIA,
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ROCKCHIP_OUT_MODE_AAAA);
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mux = rockchip_drm_encoder_get_mux_id(hdmi->dev->of_node, encoder);
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if (mux)
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val = HDMI_SEL_VOP_LIT | (HDMI_SEL_VOP_LIT << 16);
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@ -212,17 +215,10 @@ static void dw_hdmi_rockchip_encoder_commit(struct drm_encoder *encoder)
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(mux) ? "LIT" : "BIG");
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}
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static void dw_hdmi_rockchip_encoder_prepare(struct drm_encoder *encoder)
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{
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rockchip_drm_crtc_mode_config(encoder->crtc, DRM_MODE_CONNECTOR_HDMIA,
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ROCKCHIP_OUT_MODE_AAAA);
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}
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static const struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_funcs = {
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.mode_fixup = dw_hdmi_rockchip_encoder_mode_fixup,
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.mode_set = dw_hdmi_rockchip_encoder_mode_set,
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.prepare = dw_hdmi_rockchip_encoder_prepare,
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.commit = dw_hdmi_rockchip_encoder_commit,
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.enable = dw_hdmi_rockchip_encoder_enable,
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.disable = dw_hdmi_rockchip_encoder_disable,
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};
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@ -64,11 +64,11 @@ void rockchip_drm_dma_detach_device(struct drm_device *drm_dev,
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}
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EXPORT_SYMBOL_GPL(rockchip_drm_dma_detach_device);
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int rockchip_register_crtc_funcs(struct drm_device *dev,
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const struct rockchip_crtc_funcs *crtc_funcs,
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int pipe)
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int rockchip_register_crtc_funcs(struct drm_crtc *crtc,
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const struct rockchip_crtc_funcs *crtc_funcs)
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{
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struct rockchip_drm_private *priv = dev->dev_private;
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int pipe = drm_crtc_index(crtc);
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struct rockchip_drm_private *priv = crtc->dev->dev_private;
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if (pipe > ROCKCHIP_MAX_CRTC)
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return -EINVAL;
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@ -79,9 +79,10 @@ int rockchip_register_crtc_funcs(struct drm_device *dev,
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}
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EXPORT_SYMBOL_GPL(rockchip_register_crtc_funcs);
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void rockchip_unregister_crtc_funcs(struct drm_device *dev, int pipe)
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void rockchip_unregister_crtc_funcs(struct drm_crtc *crtc)
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{
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struct rockchip_drm_private *priv = dev->dev_private;
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int pipe = drm_crtc_index(crtc);
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struct rockchip_drm_private *priv = crtc->dev->dev_private;
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if (pipe > ROCKCHIP_MAX_CRTC)
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return;
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@ -139,6 +140,9 @@ static int rockchip_drm_load(struct drm_device *drm_dev, unsigned long flags)
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if (!private)
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return -ENOMEM;
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mutex_init(&private->commit.lock);
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INIT_WORK(&private->commit.work, rockchip_drm_atomic_work);
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drm_dev->dev_private = private;
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drm_mode_config_init(drm_dev);
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@ -212,6 +216,8 @@ static int rockchip_drm_load(struct drm_device *drm_dev, unsigned long flags)
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*/
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drm_dev->vblank_disable_allowed = true;
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drm_mode_config_reset(drm_dev);
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ret = rockchip_drm_fbdev_init(drm_dev);
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if (ret)
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goto err_vblank_cleanup;
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@ -275,7 +281,8 @@ const struct vm_operations_struct rockchip_drm_vm_ops = {
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};
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static struct drm_driver rockchip_drm_driver = {
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.driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME,
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.driver_features = DRIVER_MODESET | DRIVER_GEM |
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DRIVER_PRIME | DRIVER_ATOMIC,
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.load = rockchip_drm_load,
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.unload = rockchip_drm_unload,
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.lastclose = rockchip_drm_lastclose,
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@ -18,6 +18,7 @@
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#define _ROCKCHIP_DRM_DRV_H
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#include <drm/drm_fb_helper.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_gem.h>
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#include <linux/module.h>
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@ -38,6 +39,14 @@ struct drm_connector;
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struct rockchip_crtc_funcs {
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int (*enable_vblank)(struct drm_crtc *crtc);
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void (*disable_vblank)(struct drm_crtc *crtc);
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void (*wait_for_update)(struct drm_crtc *crtc);
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};
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struct rockchip_atomic_commit {
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struct work_struct work;
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struct drm_atomic_state *state;
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struct drm_device *dev;
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struct mutex lock;
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};
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/*
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@ -50,12 +59,14 @@ struct rockchip_drm_private {
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struct drm_fb_helper fbdev_helper;
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struct drm_gem_object *fbdev_bo;
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const struct rockchip_crtc_funcs *crtc_funcs[ROCKCHIP_MAX_CRTC];
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struct rockchip_atomic_commit commit;
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};
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int rockchip_register_crtc_funcs(struct drm_device *dev,
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const struct rockchip_crtc_funcs *crtc_funcs,
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int pipe);
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void rockchip_unregister_crtc_funcs(struct drm_device *dev, int pipe);
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void rockchip_drm_atomic_work(struct work_struct *work);
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int rockchip_register_crtc_funcs(struct drm_crtc *crtc,
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const struct rockchip_crtc_funcs *crtc_funcs);
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void rockchip_unregister_crtc_funcs(struct drm_crtc *crtc);
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int rockchip_drm_encoder_get_mux_id(struct device_node *node,
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struct drm_encoder *encoder);
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int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc, int connector_type,
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@ -64,5 +75,4 @@ int rockchip_drm_dma_attach_device(struct drm_device *drm_dev,
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struct device *dev);
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void rockchip_drm_dma_detach_device(struct drm_device *drm_dev,
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struct device *dev);
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#endif /* _ROCKCHIP_DRM_DRV_H_ */
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@ -15,6 +15,7 @@
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#include <linux/kernel.h>
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#include <drm/drm.h>
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#include <drm/drmP.h>
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#include <drm/drm_atomic.h>
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#include <drm/drm_fb_helper.h>
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#include <drm/drm_crtc_helper.h>
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@ -166,9 +167,131 @@ static void rockchip_drm_output_poll_changed(struct drm_device *dev)
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drm_fb_helper_hotplug_event(fb_helper);
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}
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static void rockchip_crtc_wait_for_update(struct drm_crtc *crtc)
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{
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struct rockchip_drm_private *priv = crtc->dev->dev_private;
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int pipe = drm_crtc_index(crtc);
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const struct rockchip_crtc_funcs *crtc_funcs = priv->crtc_funcs[pipe];
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if (crtc_funcs && crtc_funcs->wait_for_update)
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crtc_funcs->wait_for_update(crtc);
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}
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static void
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rockchip_atomic_wait_for_complete(struct drm_atomic_state *old_state)
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{
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struct drm_crtc_state *old_crtc_state;
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struct drm_crtc *crtc;
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int i, ret;
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for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
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/* No one cares about the old state, so abuse it for tracking
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* and store whether we hold a vblank reference (and should do a
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* vblank wait) in the ->enable boolean.
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*/
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old_crtc_state->enable = false;
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if (!crtc->state->active)
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continue;
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ret = drm_crtc_vblank_get(crtc);
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if (ret != 0)
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continue;
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old_crtc_state->enable = true;
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}
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for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
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if (!old_crtc_state->enable)
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continue;
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rockchip_crtc_wait_for_update(crtc);
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drm_crtc_vblank_put(crtc);
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}
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}
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static void
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rockchip_atomic_commit_complete(struct rockchip_atomic_commit *commit)
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{
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struct drm_atomic_state *state = commit->state;
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struct drm_device *dev = commit->dev;
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/*
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* TODO: do fence wait here.
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*/
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/*
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* Rockchip crtc support runtime PM, can't update display planes
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* when crtc is disabled.
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*
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* drm_atomic_helper_commit comments detail that:
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* For drivers supporting runtime PM the recommended sequence is
|
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*
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* drm_atomic_helper_commit_modeset_disables(dev, state);
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*
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* drm_atomic_helper_commit_modeset_enables(dev, state);
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*
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* drm_atomic_helper_commit_planes(dev, state, true);
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*
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* See the kerneldoc entries for these three functions for more details.
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*/
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drm_atomic_helper_commit_modeset_disables(dev, state);
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drm_atomic_helper_commit_modeset_enables(dev, state);
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drm_atomic_helper_commit_planes(dev, state, true);
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rockchip_atomic_wait_for_complete(state);
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|
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drm_atomic_helper_cleanup_planes(dev, state);
|
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|
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drm_atomic_state_free(state);
|
||||
}
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|
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void rockchip_drm_atomic_work(struct work_struct *work)
|
||||
{
|
||||
struct rockchip_atomic_commit *commit = container_of(work,
|
||||
struct rockchip_atomic_commit, work);
|
||||
|
||||
rockchip_atomic_commit_complete(commit);
|
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}
|
||||
|
||||
int rockchip_drm_atomic_commit(struct drm_device *dev,
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struct drm_atomic_state *state,
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bool async)
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||||
{
|
||||
struct rockchip_drm_private *private = dev->dev_private;
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struct rockchip_atomic_commit *commit = &private->commit;
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int ret;
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||||
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||||
ret = drm_atomic_helper_prepare_planes(dev, state);
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if (ret)
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||||
return ret;
|
||||
|
||||
/* serialize outstanding asynchronous commits */
|
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mutex_lock(&commit->lock);
|
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flush_work(&commit->work);
|
||||
|
||||
drm_atomic_helper_swap_state(dev, state);
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|
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commit->dev = dev;
|
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commit->state = state;
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|
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if (async)
|
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schedule_work(&commit->work);
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else
|
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rockchip_atomic_commit_complete(commit);
|
||||
|
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mutex_unlock(&commit->lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct drm_mode_config_funcs rockchip_drm_mode_config_funcs = {
|
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.fb_create = rockchip_user_fb_create,
|
||||
.output_poll_changed = rockchip_drm_output_poll_changed,
|
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.atomic_check = drm_atomic_helper_check,
|
||||
.atomic_commit = rockchip_drm_atomic_commit,
|
||||
};
|
||||
|
||||
struct drm_framebuffer *
|
||||
|
|
|
|||
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
|
@ -15,111 +15,125 @@
|
|||
#ifndef _ROCKCHIP_DRM_VOP_H
|
||||
#define _ROCKCHIP_DRM_VOP_H
|
||||
|
||||
/* register definition */
|
||||
#define REG_CFG_DONE 0x0000
|
||||
#define VERSION_INFO 0x0004
|
||||
#define SYS_CTRL 0x0008
|
||||
#define SYS_CTRL1 0x000c
|
||||
#define DSP_CTRL0 0x0010
|
||||
#define DSP_CTRL1 0x0014
|
||||
#define DSP_BG 0x0018
|
||||
#define MCU_CTRL 0x001c
|
||||
#define INTR_CTRL0 0x0020
|
||||
#define INTR_CTRL1 0x0024
|
||||
#define WIN0_CTRL0 0x0030
|
||||
#define WIN0_CTRL1 0x0034
|
||||
#define WIN0_COLOR_KEY 0x0038
|
||||
#define WIN0_VIR 0x003c
|
||||
#define WIN0_YRGB_MST 0x0040
|
||||
#define WIN0_CBR_MST 0x0044
|
||||
#define WIN0_ACT_INFO 0x0048
|
||||
#define WIN0_DSP_INFO 0x004c
|
||||
#define WIN0_DSP_ST 0x0050
|
||||
#define WIN0_SCL_FACTOR_YRGB 0x0054
|
||||
#define WIN0_SCL_FACTOR_CBR 0x0058
|
||||
#define WIN0_SCL_OFFSET 0x005c
|
||||
#define WIN0_SRC_ALPHA_CTRL 0x0060
|
||||
#define WIN0_DST_ALPHA_CTRL 0x0064
|
||||
#define WIN0_FADING_CTRL 0x0068
|
||||
/* win1 register */
|
||||
#define WIN1_CTRL0 0x0070
|
||||
#define WIN1_CTRL1 0x0074
|
||||
#define WIN1_COLOR_KEY 0x0078
|
||||
#define WIN1_VIR 0x007c
|
||||
#define WIN1_YRGB_MST 0x0080
|
||||
#define WIN1_CBR_MST 0x0084
|
||||
#define WIN1_ACT_INFO 0x0088
|
||||
#define WIN1_DSP_INFO 0x008c
|
||||
#define WIN1_DSP_ST 0x0090
|
||||
#define WIN1_SCL_FACTOR_YRGB 0x0094
|
||||
#define WIN1_SCL_FACTOR_CBR 0x0098
|
||||
#define WIN1_SCL_OFFSET 0x009c
|
||||
#define WIN1_SRC_ALPHA_CTRL 0x00a0
|
||||
#define WIN1_DST_ALPHA_CTRL 0x00a4
|
||||
#define WIN1_FADING_CTRL 0x00a8
|
||||
/* win2 register */
|
||||
#define WIN2_CTRL0 0x00b0
|
||||
#define WIN2_CTRL1 0x00b4
|
||||
#define WIN2_VIR0_1 0x00b8
|
||||
#define WIN2_VIR2_3 0x00bc
|
||||
#define WIN2_MST0 0x00c0
|
||||
#define WIN2_DSP_INFO0 0x00c4
|
||||
#define WIN2_DSP_ST0 0x00c8
|
||||
#define WIN2_COLOR_KEY 0x00cc
|
||||
#define WIN2_MST1 0x00d0
|
||||
#define WIN2_DSP_INFO1 0x00d4
|
||||
#define WIN2_DSP_ST1 0x00d8
|
||||
#define WIN2_SRC_ALPHA_CTRL 0x00dc
|
||||
#define WIN2_MST2 0x00e0
|
||||
#define WIN2_DSP_INFO2 0x00e4
|
||||
#define WIN2_DSP_ST2 0x00e8
|
||||
#define WIN2_DST_ALPHA_CTRL 0x00ec
|
||||
#define WIN2_MST3 0x00f0
|
||||
#define WIN2_DSP_INFO3 0x00f4
|
||||
#define WIN2_DSP_ST3 0x00f8
|
||||
#define WIN2_FADING_CTRL 0x00fc
|
||||
/* win3 register */
|
||||
#define WIN3_CTRL0 0x0100
|
||||
#define WIN3_CTRL1 0x0104
|
||||
#define WIN3_VIR0_1 0x0108
|
||||
#define WIN3_VIR2_3 0x010c
|
||||
#define WIN3_MST0 0x0110
|
||||
#define WIN3_DSP_INFO0 0x0114
|
||||
#define WIN3_DSP_ST0 0x0118
|
||||
#define WIN3_COLOR_KEY 0x011c
|
||||
#define WIN3_MST1 0x0120
|
||||
#define WIN3_DSP_INFO1 0x0124
|
||||
#define WIN3_DSP_ST1 0x0128
|
||||
#define WIN3_SRC_ALPHA_CTRL 0x012c
|
||||
#define WIN3_MST2 0x0130
|
||||
#define WIN3_DSP_INFO2 0x0134
|
||||
#define WIN3_DSP_ST2 0x0138
|
||||
#define WIN3_DST_ALPHA_CTRL 0x013c
|
||||
#define WIN3_MST3 0x0140
|
||||
#define WIN3_DSP_INFO3 0x0144
|
||||
#define WIN3_DSP_ST3 0x0148
|
||||
#define WIN3_FADING_CTRL 0x014c
|
||||
/* hwc register */
|
||||
#define HWC_CTRL0 0x0150
|
||||
#define HWC_CTRL1 0x0154
|
||||
#define HWC_MST 0x0158
|
||||
#define HWC_DSP_ST 0x015c
|
||||
#define HWC_SRC_ALPHA_CTRL 0x0160
|
||||
#define HWC_DST_ALPHA_CTRL 0x0164
|
||||
#define HWC_FADING_CTRL 0x0168
|
||||
/* post process register */
|
||||
#define POST_DSP_HACT_INFO 0x0170
|
||||
#define POST_DSP_VACT_INFO 0x0174
|
||||
#define POST_SCL_FACTOR_YRGB 0x0178
|
||||
#define POST_SCL_CTRL 0x0180
|
||||
#define POST_DSP_VACT_INFO_F1 0x0184
|
||||
#define DSP_HTOTAL_HS_END 0x0188
|
||||
#define DSP_HACT_ST_END 0x018c
|
||||
#define DSP_VTOTAL_VS_END 0x0190
|
||||
#define DSP_VACT_ST_END 0x0194
|
||||
#define DSP_VS_ST_END_F1 0x0198
|
||||
#define DSP_VACT_ST_END_F1 0x019c
|
||||
/* register definition end */
|
||||
enum vop_data_format {
|
||||
VOP_FMT_ARGB8888 = 0,
|
||||
VOP_FMT_RGB888,
|
||||
VOP_FMT_RGB565,
|
||||
VOP_FMT_YUV420SP = 4,
|
||||
VOP_FMT_YUV422SP,
|
||||
VOP_FMT_YUV444SP,
|
||||
};
|
||||
|
||||
struct vop_reg_data {
|
||||
uint32_t offset;
|
||||
uint32_t value;
|
||||
};
|
||||
|
||||
struct vop_reg {
|
||||
uint32_t offset;
|
||||
uint32_t shift;
|
||||
uint32_t mask;
|
||||
};
|
||||
|
||||
struct vop_ctrl {
|
||||
struct vop_reg standby;
|
||||
struct vop_reg data_blank;
|
||||
struct vop_reg gate_en;
|
||||
struct vop_reg mmu_en;
|
||||
struct vop_reg rgb_en;
|
||||
struct vop_reg edp_en;
|
||||
struct vop_reg hdmi_en;
|
||||
struct vop_reg mipi_en;
|
||||
struct vop_reg out_mode;
|
||||
struct vop_reg dither_down;
|
||||
struct vop_reg dither_up;
|
||||
struct vop_reg pin_pol;
|
||||
|
||||
struct vop_reg htotal_pw;
|
||||
struct vop_reg hact_st_end;
|
||||
struct vop_reg vtotal_pw;
|
||||
struct vop_reg vact_st_end;
|
||||
struct vop_reg hpost_st_end;
|
||||
struct vop_reg vpost_st_end;
|
||||
|
||||
struct vop_reg cfg_done;
|
||||
};
|
||||
|
||||
struct vop_intr {
|
||||
const int *intrs;
|
||||
uint32_t nintrs;
|
||||
struct vop_reg enable;
|
||||
struct vop_reg clear;
|
||||
struct vop_reg status;
|
||||
};
|
||||
|
||||
struct vop_scl_extension {
|
||||
struct vop_reg cbcr_vsd_mode;
|
||||
struct vop_reg cbcr_vsu_mode;
|
||||
struct vop_reg cbcr_hsd_mode;
|
||||
struct vop_reg cbcr_ver_scl_mode;
|
||||
struct vop_reg cbcr_hor_scl_mode;
|
||||
struct vop_reg yrgb_vsd_mode;
|
||||
struct vop_reg yrgb_vsu_mode;
|
||||
struct vop_reg yrgb_hsd_mode;
|
||||
struct vop_reg yrgb_ver_scl_mode;
|
||||
struct vop_reg yrgb_hor_scl_mode;
|
||||
struct vop_reg line_load_mode;
|
||||
struct vop_reg cbcr_axi_gather_num;
|
||||
struct vop_reg yrgb_axi_gather_num;
|
||||
struct vop_reg vsd_cbcr_gt2;
|
||||
struct vop_reg vsd_cbcr_gt4;
|
||||
struct vop_reg vsd_yrgb_gt2;
|
||||
struct vop_reg vsd_yrgb_gt4;
|
||||
struct vop_reg bic_coe_sel;
|
||||
struct vop_reg cbcr_axi_gather_en;
|
||||
struct vop_reg yrgb_axi_gather_en;
|
||||
struct vop_reg lb_mode;
|
||||
};
|
||||
|
||||
struct vop_scl_regs {
|
||||
const struct vop_scl_extension *ext;
|
||||
|
||||
struct vop_reg scale_yrgb_x;
|
||||
struct vop_reg scale_yrgb_y;
|
||||
struct vop_reg scale_cbcr_x;
|
||||
struct vop_reg scale_cbcr_y;
|
||||
};
|
||||
|
||||
struct vop_win_phy {
|
||||
const struct vop_scl_regs *scl;
|
||||
const uint32_t *data_formats;
|
||||
uint32_t nformats;
|
||||
|
||||
struct vop_reg enable;
|
||||
struct vop_reg format;
|
||||
struct vop_reg rb_swap;
|
||||
struct vop_reg act_info;
|
||||
struct vop_reg dsp_info;
|
||||
struct vop_reg dsp_st;
|
||||
struct vop_reg yrgb_mst;
|
||||
struct vop_reg uv_mst;
|
||||
struct vop_reg yrgb_vir;
|
||||
struct vop_reg uv_vir;
|
||||
|
||||
struct vop_reg dst_alpha_ctl;
|
||||
struct vop_reg src_alpha_ctl;
|
||||
};
|
||||
|
||||
struct vop_win_data {
|
||||
uint32_t base;
|
||||
const struct vop_win_phy *phy;
|
||||
enum drm_plane_type type;
|
||||
};
|
||||
|
||||
struct vop_data {
|
||||
const struct vop_reg_data *init_table;
|
||||
unsigned int table_size;
|
||||
const struct vop_ctrl *ctrl;
|
||||
const struct vop_intr *intr;
|
||||
const struct vop_win_data *win;
|
||||
unsigned int win_size;
|
||||
};
|
||||
|
||||
/* interrupt define */
|
||||
#define DSP_HOLD_VALID_INTR (1 << 0)
|
||||
|
|
@ -233,6 +247,11 @@ static inline uint16_t scl_cal_scale(int src, int dst, int shift)
|
|||
return ((src * 2 - 3) << (shift - 1)) / (dst - 1);
|
||||
}
|
||||
|
||||
static inline uint16_t scl_cal_scale2(int src, int dst)
|
||||
{
|
||||
return ((src - 1) << 12) / (dst - 1);
|
||||
}
|
||||
|
||||
#define GET_SCL_FT_BILI_DN(src, dst) scl_cal_scale(src, dst, 12)
|
||||
#define GET_SCL_FT_BILI_UP(src, dst) scl_cal_scale(src, dst, 16)
|
||||
#define GET_SCL_FT_BIC(src, dst) scl_cal_scale(src, dst, 16)
|
||||
|
|
@ -286,4 +305,5 @@ static inline int scl_vop_cal_lb_mode(int width, bool is_yuv)
|
|||
return lb_mode;
|
||||
}
|
||||
|
||||
extern const struct component_ops vop_component_ops;
|
||||
#endif /* _ROCKCHIP_DRM_VOP_H */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,316 @@
|
|||
/*
|
||||
* Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
|
||||
* Author:Mark Yao <mark.yao@rock-chips.com>
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <drm/drmP.h>
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/component.h>
|
||||
|
||||
#include "rockchip_drm_vop.h"
|
||||
#include "rockchip_vop_reg.h"
|
||||
|
||||
#define VOP_REG(off, _mask, s) \
|
||||
{.offset = off, \
|
||||
.mask = _mask, \
|
||||
.shift = s,}
|
||||
|
||||
static const uint32_t formats_win_full[] = {
|
||||
DRM_FORMAT_XRGB8888,
|
||||
DRM_FORMAT_ARGB8888,
|
||||
DRM_FORMAT_XBGR8888,
|
||||
DRM_FORMAT_ABGR8888,
|
||||
DRM_FORMAT_RGB888,
|
||||
DRM_FORMAT_BGR888,
|
||||
DRM_FORMAT_RGB565,
|
||||
DRM_FORMAT_BGR565,
|
||||
DRM_FORMAT_NV12,
|
||||
DRM_FORMAT_NV16,
|
||||
DRM_FORMAT_NV24,
|
||||
};
|
||||
|
||||
static const uint32_t formats_win_lite[] = {
|
||||
DRM_FORMAT_XRGB8888,
|
||||
DRM_FORMAT_ARGB8888,
|
||||
DRM_FORMAT_XBGR8888,
|
||||
DRM_FORMAT_ABGR8888,
|
||||
DRM_FORMAT_RGB888,
|
||||
DRM_FORMAT_BGR888,
|
||||
DRM_FORMAT_RGB565,
|
||||
DRM_FORMAT_BGR565,
|
||||
};
|
||||
|
||||
static const struct vop_scl_extension rk3288_win_full_scl_ext = {
|
||||
.cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31),
|
||||
.cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30),
|
||||
.cbcr_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 28),
|
||||
.cbcr_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 26),
|
||||
.cbcr_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 24),
|
||||
.yrgb_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 23),
|
||||
.yrgb_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 22),
|
||||
.yrgb_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 20),
|
||||
.yrgb_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 18),
|
||||
.yrgb_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 16),
|
||||
.line_load_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 15),
|
||||
.cbcr_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0x7, 12),
|
||||
.yrgb_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0xf, 8),
|
||||
.vsd_cbcr_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 7),
|
||||
.vsd_cbcr_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 6),
|
||||
.vsd_yrgb_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 5),
|
||||
.vsd_yrgb_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 4),
|
||||
.bic_coe_sel = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 2),
|
||||
.cbcr_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 1),
|
||||
.yrgb_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 0),
|
||||
.lb_mode = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 5),
|
||||
};
|
||||
|
||||
static const struct vop_scl_regs rk3288_win_full_scl = {
|
||||
.ext = &rk3288_win_full_scl_ext,
|
||||
.scale_yrgb_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
|
||||
.scale_yrgb_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
|
||||
.scale_cbcr_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
|
||||
.scale_cbcr_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
|
||||
};
|
||||
|
||||
static const struct vop_win_phy rk3288_win01_data = {
|
||||
.scl = &rk3288_win_full_scl,
|
||||
.data_formats = formats_win_full,
|
||||
.nformats = ARRAY_SIZE(formats_win_full),
|
||||
.enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
|
||||
.format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
|
||||
.rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
|
||||
.act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
|
||||
.dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0),
|
||||
.dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0),
|
||||
.yrgb_mst = VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0),
|
||||
.uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0),
|
||||
.yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0),
|
||||
.uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16),
|
||||
.src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xff, 0),
|
||||
.dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xff, 0),
|
||||
};
|
||||
|
||||
static const struct vop_win_phy rk3288_win23_data = {
|
||||
.data_formats = formats_win_lite,
|
||||
.nformats = ARRAY_SIZE(formats_win_lite),
|
||||
.enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 0),
|
||||
.format = VOP_REG(RK3288_WIN2_CTRL0, 0x7, 1),
|
||||
.rb_swap = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 12),
|
||||
.dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO0, 0x0fff0fff, 0),
|
||||
.dsp_st = VOP_REG(RK3288_WIN2_DSP_ST0, 0x1fff1fff, 0),
|
||||
.yrgb_mst = VOP_REG(RK3288_WIN2_MST0, 0xffffffff, 0),
|
||||
.yrgb_vir = VOP_REG(RK3288_WIN2_VIR0_1, 0x1fff, 0),
|
||||
.src_alpha_ctl = VOP_REG(RK3288_WIN2_SRC_ALPHA_CTRL, 0xff, 0),
|
||||
.dst_alpha_ctl = VOP_REG(RK3288_WIN2_DST_ALPHA_CTRL, 0xff, 0),
|
||||
};
|
||||
|
||||
static const struct vop_ctrl rk3288_ctrl_data = {
|
||||
.standby = VOP_REG(RK3288_SYS_CTRL, 0x1, 22),
|
||||
.gate_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 23),
|
||||
.mmu_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 20),
|
||||
.rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12),
|
||||
.hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13),
|
||||
.edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14),
|
||||
.mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15),
|
||||
.dither_down = VOP_REG(RK3288_DSP_CTRL1, 0xf, 1),
|
||||
.dither_up = VOP_REG(RK3288_DSP_CTRL1, 0x1, 6),
|
||||
.data_blank = VOP_REG(RK3288_DSP_CTRL0, 0x1, 19),
|
||||
.out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0),
|
||||
.pin_pol = VOP_REG(RK3288_DSP_CTRL0, 0xf, 4),
|
||||
.htotal_pw = VOP_REG(RK3288_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
|
||||
.hact_st_end = VOP_REG(RK3288_DSP_HACT_ST_END, 0x1fff1fff, 0),
|
||||
.vtotal_pw = VOP_REG(RK3288_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
|
||||
.vact_st_end = VOP_REG(RK3288_DSP_VACT_ST_END, 0x1fff1fff, 0),
|
||||
.hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
|
||||
.vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
|
||||
.cfg_done = VOP_REG(RK3288_REG_CFG_DONE, 0x1, 0),
|
||||
};
|
||||
|
||||
static const struct vop_reg_data rk3288_init_reg_table[] = {
|
||||
{RK3288_SYS_CTRL, 0x00c00000},
|
||||
{RK3288_DSP_CTRL0, 0x00000000},
|
||||
{RK3288_WIN0_CTRL0, 0x00000080},
|
||||
{RK3288_WIN1_CTRL0, 0x00000080},
|
||||
/* TODO: Win2/3 support multiple area function, but we haven't found
|
||||
* a suitable way to use it yet, so let's just use them as other windows
|
||||
* with only area 0 enabled.
|
||||
*/
|
||||
{RK3288_WIN2_CTRL0, 0x00000010},
|
||||
{RK3288_WIN3_CTRL0, 0x00000010},
|
||||
};
|
||||
|
||||
/*
|
||||
* Note: rk3288 has a dedicated 'cursor' window, however, that window requires
|
||||
* special support to get alpha blending working. For now, just use overlay
|
||||
* window 3 for the drm cursor.
|
||||
*
|
||||
*/
|
||||
static const struct vop_win_data rk3288_vop_win_data[] = {
|
||||
{ .base = 0x00, .phy = &rk3288_win01_data,
|
||||
.type = DRM_PLANE_TYPE_PRIMARY },
|
||||
{ .base = 0x40, .phy = &rk3288_win01_data,
|
||||
.type = DRM_PLANE_TYPE_OVERLAY },
|
||||
{ .base = 0x00, .phy = &rk3288_win23_data,
|
||||
.type = DRM_PLANE_TYPE_OVERLAY },
|
||||
{ .base = 0x50, .phy = &rk3288_win23_data,
|
||||
.type = DRM_PLANE_TYPE_CURSOR },
|
||||
};
|
||||
|
||||
static const int rk3288_vop_intrs[] = {
|
||||
DSP_HOLD_VALID_INTR,
|
||||
FS_INTR,
|
||||
LINE_FLAG_INTR,
|
||||
BUS_ERROR_INTR,
|
||||
};
|
||||
|
||||
static const struct vop_intr rk3288_vop_intr = {
|
||||
.intrs = rk3288_vop_intrs,
|
||||
.nintrs = ARRAY_SIZE(rk3288_vop_intrs),
|
||||
.status = VOP_REG(RK3288_INTR_CTRL0, 0xf, 0),
|
||||
.enable = VOP_REG(RK3288_INTR_CTRL0, 0xf, 4),
|
||||
.clear = VOP_REG(RK3288_INTR_CTRL0, 0xf, 8),
|
||||
};
|
||||
|
||||
static const struct vop_data rk3288_vop = {
|
||||
.init_table = rk3288_init_reg_table,
|
||||
.table_size = ARRAY_SIZE(rk3288_init_reg_table),
|
||||
.intr = &rk3288_vop_intr,
|
||||
.ctrl = &rk3288_ctrl_data,
|
||||
.win = rk3288_vop_win_data,
|
||||
.win_size = ARRAY_SIZE(rk3288_vop_win_data),
|
||||
};
|
||||
|
||||
static const struct vop_scl_regs rk3066_win_scl = {
|
||||
.scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
|
||||
.scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
|
||||
.scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
|
||||
.scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
|
||||
};
|
||||
|
||||
static const struct vop_win_phy rk3036_win0_data = {
|
||||
.scl = &rk3066_win_scl,
|
||||
.data_formats = formats_win_full,
|
||||
.nformats = ARRAY_SIZE(formats_win_full),
|
||||
.enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0),
|
||||
.format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3),
|
||||
.rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15),
|
||||
.act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0),
|
||||
.dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0),
|
||||
.dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0),
|
||||
.yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0),
|
||||
.uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0),
|
||||
.yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0),
|
||||
};
|
||||
|
||||
static const struct vop_win_phy rk3036_win1_data = {
|
||||
.data_formats = formats_win_lite,
|
||||
.nformats = ARRAY_SIZE(formats_win_lite),
|
||||
.enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1),
|
||||
.format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6),
|
||||
.rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19),
|
||||
.act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0),
|
||||
.dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0),
|
||||
.dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0),
|
||||
.yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0),
|
||||
.yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0),
|
||||
};
|
||||
|
||||
static const struct vop_win_data rk3036_vop_win_data[] = {
|
||||
{ .base = 0x00, .phy = &rk3036_win0_data,
|
||||
.type = DRM_PLANE_TYPE_PRIMARY },
|
||||
{ .base = 0x00, .phy = &rk3036_win1_data,
|
||||
.type = DRM_PLANE_TYPE_CURSOR },
|
||||
};
|
||||
|
||||
static const int rk3036_vop_intrs[] = {
|
||||
DSP_HOLD_VALID_INTR,
|
||||
FS_INTR,
|
||||
LINE_FLAG_INTR,
|
||||
BUS_ERROR_INTR,
|
||||
};
|
||||
|
||||
static const struct vop_intr rk3036_intr = {
|
||||
.intrs = rk3036_vop_intrs,
|
||||
.nintrs = ARRAY_SIZE(rk3036_vop_intrs),
|
||||
.status = VOP_REG(RK3036_INT_STATUS, 0xf, 0),
|
||||
.enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4),
|
||||
.clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8),
|
||||
};
|
||||
|
||||
static const struct vop_ctrl rk3036_ctrl_data = {
|
||||
.standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30),
|
||||
.out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0),
|
||||
.pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4),
|
||||
.htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
|
||||
.hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0),
|
||||
.vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
|
||||
.vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0),
|
||||
.cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0),
|
||||
};
|
||||
|
||||
static const struct vop_reg_data rk3036_vop_init_reg_table[] = {
|
||||
{RK3036_DSP_CTRL1, 0x00000000},
|
||||
};
|
||||
|
||||
static const struct vop_data rk3036_vop = {
|
||||
.init_table = rk3036_vop_init_reg_table,
|
||||
.table_size = ARRAY_SIZE(rk3036_vop_init_reg_table),
|
||||
.ctrl = &rk3036_ctrl_data,
|
||||
.intr = &rk3036_intr,
|
||||
.win = rk3036_vop_win_data,
|
||||
.win_size = ARRAY_SIZE(rk3036_vop_win_data),
|
||||
};
|
||||
|
||||
static const struct of_device_id vop_driver_dt_match[] = {
|
||||
{ .compatible = "rockchip,rk3288-vop",
|
||||
.data = &rk3288_vop },
|
||||
{ .compatible = "rockchip,rk3036-vop",
|
||||
.data = &rk3036_vop },
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, vop_driver_dt_match);
|
||||
|
||||
static int vop_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
|
||||
if (!dev->of_node) {
|
||||
dev_err(dev, "can't find vop devices\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
return component_add(dev, &vop_component_ops);
|
||||
}
|
||||
|
||||
static int vop_remove(struct platform_device *pdev)
|
||||
{
|
||||
component_del(&pdev->dev, &vop_component_ops);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct platform_driver vop_platform_driver = {
|
||||
.probe = vop_probe,
|
||||
.remove = vop_remove,
|
||||
.driver = {
|
||||
.name = "rockchip-vop",
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = of_match_ptr(vop_driver_dt_match),
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(vop_platform_driver);
|
||||
|
||||
MODULE_AUTHOR("Mark Yao <mark.yao@rock-chips.com>");
|
||||
MODULE_DESCRIPTION("ROCKCHIP VOP Driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
|
@ -0,0 +1,169 @@
|
|||
/*
|
||||
* Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
|
||||
* Author:Mark Yao <mark.yao@rock-chips.com>
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef _ROCKCHIP_VOP_REG_H
|
||||
#define _ROCKCHIP_VOP_REG_H
|
||||
|
||||
/* rk3288 register definition */
|
||||
#define RK3288_REG_CFG_DONE 0x0000
|
||||
#define RK3288_VERSION_INFO 0x0004
|
||||
#define RK3288_SYS_CTRL 0x0008
|
||||
#define RK3288_SYS_CTRL1 0x000c
|
||||
#define RK3288_DSP_CTRL0 0x0010
|
||||
#define RK3288_DSP_CTRL1 0x0014
|
||||
#define RK3288_DSP_BG 0x0018
|
||||
#define RK3288_MCU_CTRL 0x001c
|
||||
#define RK3288_INTR_CTRL0 0x0020
|
||||
#define RK3288_INTR_CTRL1 0x0024
|
||||
#define RK3288_WIN0_CTRL0 0x0030
|
||||
#define RK3288_WIN0_CTRL1 0x0034
|
||||
#define RK3288_WIN0_COLOR_KEY 0x0038
|
||||
#define RK3288_WIN0_VIR 0x003c
|
||||
#define RK3288_WIN0_YRGB_MST 0x0040
|
||||
#define RK3288_WIN0_CBR_MST 0x0044
|
||||
#define RK3288_WIN0_ACT_INFO 0x0048
|
||||
#define RK3288_WIN0_DSP_INFO 0x004c
|
||||
#define RK3288_WIN0_DSP_ST 0x0050
|
||||
#define RK3288_WIN0_SCL_FACTOR_YRGB 0x0054
|
||||
#define RK3288_WIN0_SCL_FACTOR_CBR 0x0058
|
||||
#define RK3288_WIN0_SCL_OFFSET 0x005c
|
||||
#define RK3288_WIN0_SRC_ALPHA_CTRL 0x0060
|
||||
#define RK3288_WIN0_DST_ALPHA_CTRL 0x0064
|
||||
#define RK3288_WIN0_FADING_CTRL 0x0068
|
||||
|
||||
/* win1 register */
|
||||
#define RK3288_WIN1_CTRL0 0x0070
|
||||
#define RK3288_WIN1_CTRL1 0x0074
|
||||
#define RK3288_WIN1_COLOR_KEY 0x0078
|
||||
#define RK3288_WIN1_VIR 0x007c
|
||||
#define RK3288_WIN1_YRGB_MST 0x0080
|
||||
#define RK3288_WIN1_CBR_MST 0x0084
|
||||
#define RK3288_WIN1_ACT_INFO 0x0088
|
||||
#define RK3288_WIN1_DSP_INFO 0x008c
|
||||
#define RK3288_WIN1_DSP_ST 0x0090
|
||||
#define RK3288_WIN1_SCL_FACTOR_YRGB 0x0094
|
||||
#define RK3288_WIN1_SCL_FACTOR_CBR 0x0098
|
||||
#define RK3288_WIN1_SCL_OFFSET 0x009c
|
||||
#define RK3288_WIN1_SRC_ALPHA_CTRL 0x00a0
|
||||
#define RK3288_WIN1_DST_ALPHA_CTRL 0x00a4
|
||||
#define RK3288_WIN1_FADING_CTRL 0x00a8
|
||||
/* win2 register */
|
||||
#define RK3288_WIN2_CTRL0 0x00b0
|
||||
#define RK3288_WIN2_CTRL1 0x00b4
|
||||
#define RK3288_WIN2_VIR0_1 0x00b8
|
||||
#define RK3288_WIN2_VIR2_3 0x00bc
|
||||
#define RK3288_WIN2_MST0 0x00c0
|
||||
#define RK3288_WIN2_DSP_INFO0 0x00c4
|
||||
#define RK3288_WIN2_DSP_ST0 0x00c8
|
||||
#define RK3288_WIN2_COLOR_KEY 0x00cc
|
||||
#define RK3288_WIN2_MST1 0x00d0
|
||||
#define RK3288_WIN2_DSP_INFO1 0x00d4
|
||||
#define RK3288_WIN2_DSP_ST1 0x00d8
|
||||
#define RK3288_WIN2_SRC_ALPHA_CTRL 0x00dc
|
||||
#define RK3288_WIN2_MST2 0x00e0
|
||||
#define RK3288_WIN2_DSP_INFO2 0x00e4
|
||||
#define RK3288_WIN2_DSP_ST2 0x00e8
|
||||
#define RK3288_WIN2_DST_ALPHA_CTRL 0x00ec
|
||||
#define RK3288_WIN2_MST3 0x00f0
|
||||
#define RK3288_WIN2_DSP_INFO3 0x00f4
|
||||
#define RK3288_WIN2_DSP_ST3 0x00f8
|
||||
#define RK3288_WIN2_FADING_CTRL 0x00fc
|
||||
/* win3 register */
|
||||
#define RK3288_WIN3_CTRL0 0x0100
|
||||
#define RK3288_WIN3_CTRL1 0x0104
|
||||
#define RK3288_WIN3_VIR0_1 0x0108
|
||||
#define RK3288_WIN3_VIR2_3 0x010c
|
||||
#define RK3288_WIN3_MST0 0x0110
|
||||
#define RK3288_WIN3_DSP_INFO0 0x0114
|
||||
#define RK3288_WIN3_DSP_ST0 0x0118
|
||||
#define RK3288_WIN3_COLOR_KEY 0x011c
|
||||
#define RK3288_WIN3_MST1 0x0120
|
||||
#define RK3288_WIN3_DSP_INFO1 0x0124
|
||||
#define RK3288_WIN3_DSP_ST1 0x0128
|
||||
#define RK3288_WIN3_SRC_ALPHA_CTRL 0x012c
|
||||
#define RK3288_WIN3_MST2 0x0130
|
||||
#define RK3288_WIN3_DSP_INFO2 0x0134
|
||||
#define RK3288_WIN3_DSP_ST2 0x0138
|
||||
#define RK3288_WIN3_DST_ALPHA_CTRL 0x013c
|
||||
#define RK3288_WIN3_MST3 0x0140
|
||||
#define RK3288_WIN3_DSP_INFO3 0x0144
|
||||
#define RK3288_WIN3_DSP_ST3 0x0148
|
||||
#define RK3288_WIN3_FADING_CTRL 0x014c
|
||||
/* hwc register */
|
||||
#define RK3288_HWC_CTRL0 0x0150
|
||||
#define RK3288_HWC_CTRL1 0x0154
|
||||
#define RK3288_HWC_MST 0x0158
|
||||
#define RK3288_HWC_DSP_ST 0x015c
|
||||
#define RK3288_HWC_SRC_ALPHA_CTRL 0x0160
|
||||
#define RK3288_HWC_DST_ALPHA_CTRL 0x0164
|
||||
#define RK3288_HWC_FADING_CTRL 0x0168
|
||||
/* post process register */
|
||||
#define RK3288_POST_DSP_HACT_INFO 0x0170
|
||||
#define RK3288_POST_DSP_VACT_INFO 0x0174
|
||||
#define RK3288_POST_SCL_FACTOR_YRGB 0x0178
|
||||
#define RK3288_POST_SCL_CTRL 0x0180
|
||||
#define RK3288_POST_DSP_VACT_INFO_F1 0x0184
|
||||
#define RK3288_DSP_HTOTAL_HS_END 0x0188
|
||||
#define RK3288_DSP_HACT_ST_END 0x018c
|
||||
#define RK3288_DSP_VTOTAL_VS_END 0x0190
|
||||
#define RK3288_DSP_VACT_ST_END 0x0194
|
||||
#define RK3288_DSP_VS_ST_END_F1 0x0198
|
||||
#define RK3288_DSP_VACT_ST_END_F1 0x019c
|
||||
/* register definition end */
|
||||
|
||||
/* rk3036 register definition */
|
||||
#define RK3036_SYS_CTRL 0x00
|
||||
#define RK3036_DSP_CTRL0 0x04
|
||||
#define RK3036_DSP_CTRL1 0x08
|
||||
#define RK3036_INT_STATUS 0x10
|
||||
#define RK3036_ALPHA_CTRL 0x14
|
||||
#define RK3036_WIN0_COLOR_KEY 0x18
|
||||
#define RK3036_WIN1_COLOR_KEY 0x1c
|
||||
#define RK3036_WIN0_YRGB_MST 0x20
|
||||
#define RK3036_WIN0_CBR_MST 0x24
|
||||
#define RK3036_WIN1_VIR 0x28
|
||||
#define RK3036_AXI_BUS_CTRL 0x2c
|
||||
#define RK3036_WIN0_VIR 0x30
|
||||
#define RK3036_WIN0_ACT_INFO 0x34
|
||||
#define RK3036_WIN0_DSP_INFO 0x38
|
||||
#define RK3036_WIN0_DSP_ST 0x3c
|
||||
#define RK3036_WIN0_SCL_FACTOR_YRGB 0x40
|
||||
#define RK3036_WIN0_SCL_FACTOR_CBR 0x44
|
||||
#define RK3036_WIN0_SCL_OFFSET 0x48
|
||||
#define RK3036_HWC_MST 0x58
|
||||
#define RK3036_HWC_DSP_ST 0x5c
|
||||
#define RK3036_DSP_HTOTAL_HS_END 0x6c
|
||||
#define RK3036_DSP_HACT_ST_END 0x70
|
||||
#define RK3036_DSP_VTOTAL_VS_END 0x74
|
||||
#define RK3036_DSP_VACT_ST_END 0x78
|
||||
#define RK3036_DSP_VS_ST_END_F1 0x7c
|
||||
#define RK3036_DSP_VACT_ST_END_F1 0x80
|
||||
#define RK3036_GATHER_TRANSFER 0x84
|
||||
#define RK3036_VERSION_INFO 0x94
|
||||
#define RK3036_REG_CFG_DONE 0x90
|
||||
#define RK3036_WIN1_MST 0xa0
|
||||
#define RK3036_WIN1_ACT_INFO 0xb4
|
||||
#define RK3036_WIN1_DSP_INFO 0xb8
|
||||
#define RK3036_WIN1_DSP_ST 0xbc
|
||||
#define RK3036_WIN1_SCL_FACTOR_YRGB 0xc0
|
||||
#define RK3036_WIN1_SCL_OFFSET 0xc8
|
||||
#define RK3036_BCSH_CTRL 0xd0
|
||||
#define RK3036_BCSH_COLOR_BAR 0xd4
|
||||
#define RK3036_BCSH_BCS 0xd8
|
||||
#define RK3036_BCSH_H 0xdc
|
||||
#define RK3036_WIN1_LUT_ADDR 0x400
|
||||
#define RK3036_HWC_LUT_ADDR 0x800
|
||||
/* rk3036 register definition end */
|
||||
|
||||
#endif /* _ROCKCHIP_VOP_REG_H */
|
||||
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