ASoC: add Renesas R-Car ADG feature
Renesas R-Car series sound circuit consists of SSI and its peripheral. But this peripheral circuit is different between R-Car Generation1 (E1/M1/H1) and Generation2 (E2/M2/H2) (Actually, there are many difference in Generation1 chips) This patch adds ADG feature which controls sound clock Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Mark Brown <broonie@linaro.org>
This commit is contained in:
Родитель
07539c1de8
Коммит
dfc9403b7c
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@ -15,10 +15,12 @@
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#include <linux/sh_clk.h>
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#define RSND_GEN1_SRU 0
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#define RSND_GEN1_ADG 1
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#define RSND_GEN2_SRU 0
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#define RSND_GEN2_ADG 1
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#define RSND_BASE_MAX 1
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#define RSND_BASE_MAX 2
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struct rsnd_scu_platform_info {
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u32 flags;
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@ -1,2 +1,2 @@
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snd-soc-rcar-objs := core.o gen.o scu.o
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snd-soc-rcar-objs := core.o gen.o scu.o adg.o
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obj-$(CONFIG_SND_SOC_RCAR) += snd-soc-rcar.o
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@ -0,0 +1,234 @@
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/*
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* Helper routines for R-Car sound ADG.
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*
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* Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/sh_clk.h>
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#include <mach/clock.h>
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#include "rsnd.h"
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#define CLKA 0
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#define CLKB 1
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#define CLKC 2
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#define CLKI 3
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#define CLKMAX 4
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struct rsnd_adg {
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struct clk *clk[CLKMAX];
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int rate_of_441khz_div_6;
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int rate_of_48khz_div_6;
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};
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#define for_each_rsnd_clk(pos, adg, i) \
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for (i = 0, (pos) = adg->clk[i]; \
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i < CLKMAX; \
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i++, (pos) = adg->clk[i])
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#define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg)
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static enum rsnd_reg rsnd_adg_ssi_reg_get(int id)
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{
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enum rsnd_reg reg;
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/*
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* SSI 8 is not connected to ADG.
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* it works with SSI 7
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*/
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if (id == 8)
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return RSND_REG_MAX;
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if (0 <= id && id <= 3)
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reg = RSND_REG_AUDIO_CLK_SEL0;
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else if (4 <= id && id <= 7)
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reg = RSND_REG_AUDIO_CLK_SEL1;
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else
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reg = RSND_REG_AUDIO_CLK_SEL2;
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return reg;
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}
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int rsnd_adg_ssi_clk_stop(struct rsnd_mod *mod)
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{
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struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
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enum rsnd_reg reg;
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int id;
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/*
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* "mod" = "ssi" here.
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* we can get "ssi id" from mod
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*/
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id = rsnd_mod_id(mod);
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reg = rsnd_adg_ssi_reg_get(id);
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rsnd_write(priv, mod, reg, 0);
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return 0;
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}
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int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *mod, unsigned int rate)
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{
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struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
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struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
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struct device *dev = rsnd_priv_to_dev(priv);
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struct clk *clk;
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enum rsnd_reg reg;
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int id, shift, i;
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u32 data;
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int sel_table[] = {
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[CLKA] = 0x1,
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[CLKB] = 0x2,
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[CLKC] = 0x3,
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[CLKI] = 0x0,
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};
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dev_dbg(dev, "request clock = %d\n", rate);
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/*
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* find suitable clock from
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* AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC/AUDIO_CLKI.
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*/
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data = 0;
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for_each_rsnd_clk(clk, adg, i) {
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if (rate == clk_get_rate(clk)) {
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data = sel_table[i];
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goto found_clock;
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}
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}
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/*
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* find 1/6 clock from BRGA/BRGB
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*/
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if (rate == adg->rate_of_441khz_div_6) {
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data = 0x10;
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goto found_clock;
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}
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if (rate == adg->rate_of_48khz_div_6) {
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data = 0x20;
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goto found_clock;
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}
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return -EIO;
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found_clock:
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/*
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* This "mod" = "ssi" here.
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* we can get "ssi id" from mod
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*/
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id = rsnd_mod_id(mod);
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reg = rsnd_adg_ssi_reg_get(id);
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dev_dbg(dev, "ADG: ssi%d selects clk%d = %d", id, i, rate);
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/*
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* Enable SSIx clock
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*/
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shift = (id % 4) * 8;
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rsnd_bset(priv, mod, reg,
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0xFF << shift,
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data << shift);
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return 0;
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}
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static void rsnd_adg_ssi_clk_init(struct rsnd_priv *priv, struct rsnd_adg *adg)
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{
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struct clk *clk;
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unsigned long rate;
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u32 ckr;
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int i;
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int brg_table[] = {
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[CLKA] = 0x0,
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[CLKB] = 0x1,
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[CLKC] = 0x4,
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[CLKI] = 0x2,
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};
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/*
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* This driver is assuming that AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC
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* have 44.1kHz or 48kHz base clocks for now.
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*
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* SSI itself can divide parent clock by 1/1 - 1/16
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* So, BRGA outputs 44.1kHz base parent clock 1/32,
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* and, BRGB outputs 48.0kHz base parent clock 1/32 here.
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* see
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* rsnd_adg_ssi_clk_try_start()
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*/
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ckr = 0;
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adg->rate_of_441khz_div_6 = 0;
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adg->rate_of_48khz_div_6 = 0;
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for_each_rsnd_clk(clk, adg, i) {
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rate = clk_get_rate(clk);
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if (0 == rate) /* not used */
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continue;
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/* RBGA */
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if (!adg->rate_of_441khz_div_6 && (0 == rate % 44100)) {
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adg->rate_of_441khz_div_6 = rate / 6;
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ckr |= brg_table[i] << 20;
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}
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/* RBGB */
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if (!adg->rate_of_48khz_div_6 && (0 == rate % 48000)) {
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adg->rate_of_48khz_div_6 = rate / 6;
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ckr |= brg_table[i] << 16;
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}
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}
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rsnd_priv_bset(priv, SSICKR, 0x00FF0000, ckr);
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rsnd_priv_write(priv, BRRA, 0x00000002); /* 1/6 */
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rsnd_priv_write(priv, BRRB, 0x00000002); /* 1/6 */
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}
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int rsnd_adg_probe(struct platform_device *pdev,
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struct rcar_snd_info *info,
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struct rsnd_priv *priv)
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{
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struct rsnd_adg *adg;
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struct device *dev = rsnd_priv_to_dev(priv);
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struct clk *clk;
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int i;
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adg = devm_kzalloc(dev, sizeof(*adg), GFP_KERNEL);
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if (!adg) {
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dev_err(dev, "ADG allocate failed\n");
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return -ENOMEM;
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}
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adg->clk[CLKA] = clk_get(NULL, "audio_clk_a");
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adg->clk[CLKB] = clk_get(NULL, "audio_clk_b");
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adg->clk[CLKC] = clk_get(NULL, "audio_clk_c");
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adg->clk[CLKI] = clk_get(NULL, "audio_clk_internal");
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for_each_rsnd_clk(clk, adg, i) {
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if (IS_ERR(clk)) {
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dev_err(dev, "Audio clock failed\n");
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return -EIO;
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}
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}
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rsnd_adg_ssi_clk_init(priv, adg);
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priv->adg = adg;
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dev_dbg(dev, "adg probed\n");
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return 0;
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}
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void rsnd_adg_remove(struct platform_device *pdev,
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struct rsnd_priv *priv)
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{
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struct rsnd_adg *adg = priv->adg;
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struct clk *clk;
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int i;
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for_each_rsnd_clk(clk, adg, i)
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clk_put(clk);
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}
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@ -635,6 +635,10 @@ static int rsnd_probe(struct platform_device *pdev)
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if (ret < 0)
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return ret;
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ret = rsnd_adg_probe(pdev, info, priv);
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if (ret < 0)
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return ret;
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/*
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* asoc register
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*/
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/*
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* remove each module
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*/
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rsnd_adg_remove(pdev, priv);
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rsnd_scu_remove(pdev, priv);
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rsnd_dai_remove(pdev, priv);
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rsnd_gen_remove(pdev, priv);
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@ -111,6 +111,15 @@ static void rsnd_gen1_reg_map_init(struct rsnd_gen *gen)
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{
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RSND_GEN1_REG_MAP(gen, SRU, SSI_MODE0, 0x0, 0xD0);
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RSND_GEN1_REG_MAP(gen, SRU, SSI_MODE1, 0x0, 0xD4);
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RSND_GEN1_REG_MAP(gen, ADG, BRRA, 0x0, 0x00);
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RSND_GEN1_REG_MAP(gen, ADG, BRRB, 0x0, 0x04);
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RSND_GEN1_REG_MAP(gen, ADG, SSICKR, 0x0, 0x08);
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RSND_GEN1_REG_MAP(gen, ADG, AUDIO_CLK_SEL0, 0x0, 0x0c);
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RSND_GEN1_REG_MAP(gen, ADG, AUDIO_CLK_SEL1, 0x0, 0x10);
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RSND_GEN1_REG_MAP(gen, ADG, AUDIO_CLK_SEL3, 0x0, 0x18);
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RSND_GEN1_REG_MAP(gen, ADG, AUDIO_CLK_SEL4, 0x0, 0x1c);
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RSND_GEN1_REG_MAP(gen, ADG, AUDIO_CLK_SEL5, 0x0, 0x20);
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}
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static int rsnd_gen1_probe(struct platform_device *pdev,
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struct device *dev = rsnd_priv_to_dev(priv);
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struct rsnd_gen *gen = rsnd_priv_to_gen(priv);
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struct resource *sru_res;
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struct resource *adg_res;
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/*
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* map address
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*/
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sru_res = platform_get_resource(pdev, IORESOURCE_MEM, RSND_GEN1_SRU);
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if (!sru_res) {
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adg_res = platform_get_resource(pdev, IORESOURCE_MEM, RSND_GEN1_ADG);
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if (!sru_res ||
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!adg_res) {
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dev_err(dev, "Not enough SRU/SSI/ADG platform resources.\n");
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return -ENODEV;
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}
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gen->ops = &rsnd_gen1_ops;
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gen->base[RSND_GEN1_SRU] = devm_ioremap_resource(dev, sru_res);
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if (!gen->base[RSND_GEN1_SRU]) {
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gen->base[RSND_GEN1_ADG] = devm_ioremap_resource(dev, adg_res);
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if (!gen->base[RSND_GEN1_SRU] ||
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!gen->base[RSND_GEN1_ADG]) {
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dev_err(dev, "SRU/SSI/ADG ioremap failed\n");
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return -ENODEV;
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}
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dev_dbg(dev, "Gen1 device probed\n");
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dev_dbg(dev, "SRU : %08x => %p\n", sru_res->start,
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gen->base[RSND_GEN1_SRU]);
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dev_dbg(dev, "ADG : %08x => %p\n", adg_res->start,
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gen->base[RSND_GEN1_ADG]);
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return 0;
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}
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@ -32,6 +32,17 @@ enum rsnd_reg {
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RSND_REG_SSI_MODE0,
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RSND_REG_SSI_MODE1,
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/* ADG */
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RSND_REG_BRRA,
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RSND_REG_BRRB,
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RSND_REG_SSICKR,
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RSND_REG_AUDIO_CLK_SEL0,
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RSND_REG_AUDIO_CLK_SEL1,
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RSND_REG_AUDIO_CLK_SEL2,
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RSND_REG_AUDIO_CLK_SEL3,
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RSND_REG_AUDIO_CLK_SEL4,
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RSND_REG_AUDIO_CLK_SEL5,
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RSND_REG_MAX,
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};
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struct rsnd_mod *mod,
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enum rsnd_reg reg);
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/*
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* R-Car ADG
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*/
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int rsnd_adg_ssi_clk_stop(struct rsnd_mod *mod);
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int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *mod, unsigned int rate);
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int rsnd_adg_probe(struct platform_device *pdev,
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struct rcar_snd_info *info,
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struct rsnd_priv *priv);
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void rsnd_adg_remove(struct platform_device *pdev,
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struct rsnd_priv *priv);
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/*
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* R-Car sound priv
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*/
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@ -182,6 +204,11 @@ struct rsnd_priv {
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void *scu;
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int scu_nr;
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/*
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* below value will be filled on rsnd_adg_probe()
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*/
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void *adg;
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/*
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* below value will be filled on rsnd_dai_probe()
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*/
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