i2c: octeon: Cleanup i2c-octeon driver
Cleanup only without functional change. - removed DRV_VERSION - defines: use defines instead of plain values, use BIT_ULL macro, add comments - rename waitqueue return value to time_left - sort local variables by length - fix indentation and whitespace errors - make function return void if the result is not used (octeon_i2c_stop, octeon_i2c_set_clock) - remove debug code from octeon_i2c_stop - renamed some functions for readability - update copyright Signed-off-by: Jan Glauber <jglauber@cavium.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
This commit is contained in:
Jan Glauber
Wolfram Sang
Родитель
7724fd0462
Коммит
dfcd821218
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@ -2,7 +2,7 @@
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* (C) Copyright 2009-2010
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* Nokia Siemens Networks, michael.lawnick.ext@nsn.com
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*
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* Portions Copyright (C) 2010, 2011 Cavium Networks, Inc.
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* Portions Copyright (C) 2010 - 2016 Cavium, Inc.
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*
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* This is a driver for the i2c adapter in Cavium Networks' OCTEON processors.
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*
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@ -26,39 +26,48 @@
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#define DRV_NAME "i2c-octeon"
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/* The previous out-of-tree version was implicitly version 1.0. */
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#define DRV_VERSION "2.0"
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/* register offsets */
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#define SW_TWSI 0x00
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#define TWSI_INT 0x10
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/* Register offsets */
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#define SW_TWSI 0x00
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#define TWSI_INT 0x10
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/* Controller command patterns */
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#define SW_TWSI_V 0x8000000000000000ull
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#define SW_TWSI_EOP_TWSI_DATA 0x0C00000100000000ull
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#define SW_TWSI_EOP_TWSI_CTL 0x0C00000200000000ull
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#define SW_TWSI_EOP_TWSI_CLKCTL 0x0C00000300000000ull
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#define SW_TWSI_EOP_TWSI_STAT 0x0C00000300000000ull
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#define SW_TWSI_EOP_TWSI_RST 0x0C00000700000000ull
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#define SW_TWSI_OP_TWSI_CLK 0x0800000000000000ull
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#define SW_TWSI_R 0x0100000000000000ull
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#define SW_TWSI_V BIT_ULL(63) /* Valid bit */
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#define SW_TWSI_R BIT_ULL(56) /* Result or read bit */
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/* Controller opcode word (bits 60:57) */
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#define SW_TWSI_OP_SHIFT 57
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#define SW_TWSI_OP_TWSI_CLK (4ULL << SW_TWSI_OP_SHIFT)
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#define SW_TWSI_OP_EOP (6ULL << SW_TWSI_OP_SHIFT) /* Extended opcode */
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/* Controller extended opcode word (bits 34:32) */
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#define SW_TWSI_EOP_SHIFT 32
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#define SW_TWSI_EOP_TWSI_DATA (SW_TWSI_OP_EOP | 1ULL << SW_TWSI_EOP_SHIFT)
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#define SW_TWSI_EOP_TWSI_CTL (SW_TWSI_OP_EOP | 2ULL << SW_TWSI_EOP_SHIFT)
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#define SW_TWSI_EOP_TWSI_CLKCTL (SW_TWSI_OP_EOP | 3ULL << SW_TWSI_EOP_SHIFT)
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#define SW_TWSI_EOP_TWSI_STAT (SW_TWSI_OP_EOP | 3ULL << SW_TWSI_EOP_SHIFT)
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#define SW_TWSI_EOP_TWSI_RST (SW_TWSI_OP_EOP | 7ULL << SW_TWSI_EOP_SHIFT)
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/* Controller command and status bits */
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#define TWSI_CTL_CE 0x80
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#define TWSI_CTL_ENAB 0x40
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#define TWSI_CTL_STA 0x20
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#define TWSI_CTL_STP 0x10
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#define TWSI_CTL_IFLG 0x08
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#define TWSI_CTL_AAK 0x04
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#define TWSI_CTL_CE 0x80
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#define TWSI_CTL_ENAB 0x40 /* Bus enable */
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#define TWSI_CTL_STA 0x20 /* Master-mode start, HW clears when done */
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#define TWSI_CTL_STP 0x10 /* Master-mode stop, HW clears when done */
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#define TWSI_CTL_IFLG 0x08 /* HW event, SW writes 0 to ACK */
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#define TWSI_CTL_AAK 0x04 /* Assert ACK */
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/* Some status values */
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#define STAT_START 0x08
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#define STAT_RSTART 0x10
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#define STAT_TXADDR_ACK 0x18
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#define STAT_TXDATA_ACK 0x28
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#define STAT_RXADDR_ACK 0x40
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#define STAT_RXDATA_ACK 0x50
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#define STAT_IDLE 0xF8
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#define STAT_START 0x08
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#define STAT_RSTART 0x10
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#define STAT_TXADDR_ACK 0x18
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#define STAT_TXDATA_ACK 0x28
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#define STAT_RXADDR_ACK 0x40
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#define STAT_RXDATA_ACK 0x50
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#define STAT_IDLE 0xF8
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/* TWSI_INT values */
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#define TWSI_INT_CORE_EN BIT_ULL(6)
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#define TWSI_INT_SDA_OVR BIT_ULL(8)
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#define TWSI_INT_SCL_OVR BIT_ULL(9)
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struct octeon_i2c {
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wait_queue_head_t queue;
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@ -80,9 +89,7 @@ struct octeon_i2c {
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*
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* The I2C core registers are accessed indirectly via the SW_TWSI CSR.
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*/
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static void octeon_i2c_write_sw(struct octeon_i2c *i2c,
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u64 eop_reg,
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u8 data)
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static void octeon_i2c_write_sw(struct octeon_i2c *i2c, u64 eop_reg, u8 data)
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{
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u64 tmp;
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@ -93,7 +100,7 @@ static void octeon_i2c_write_sw(struct octeon_i2c *i2c,
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}
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/**
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* octeon_i2c_read_sw - write an I2C core register
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* octeon_i2c_read_sw - read lower bits of an I2C core register
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* @i2c: The struct octeon_i2c
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* @eop_reg: Register selector
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*
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@ -133,12 +140,13 @@ static void octeon_i2c_write_int(struct octeon_i2c *i2c, u64 data)
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*/
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static void octeon_i2c_int_enable(struct octeon_i2c *i2c)
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{
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octeon_i2c_write_int(i2c, 0x40);
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octeon_i2c_write_int(i2c, TWSI_INT_CORE_EN);
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}
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/* disable the CORE interrupt */
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static void octeon_i2c_int_disable(struct octeon_i2c *i2c)
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{
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/* clear TS/ST/IFLG events */
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octeon_i2c_write_int(i2c, 0);
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}
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@ -154,17 +162,19 @@ static void octeon_i2c_unblock(struct octeon_i2c *i2c)
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int i;
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dev_dbg(i2c->dev, "%s\n", __func__);
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for (i = 0; i < 9; i++) {
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octeon_i2c_write_int(i2c, 0x0);
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octeon_i2c_write_int(i2c, 0);
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udelay(5);
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octeon_i2c_write_int(i2c, 0x200);
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octeon_i2c_write_int(i2c, TWSI_INT_SCL_OVR);
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udelay(5);
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}
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octeon_i2c_write_int(i2c, 0x300);
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/* hand-crank a STOP */
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octeon_i2c_write_int(i2c, TWSI_INT_SDA_OVR | TWSI_INT_SCL_OVR);
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udelay(5);
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octeon_i2c_write_int(i2c, 0x100);
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octeon_i2c_write_int(i2c, TWSI_INT_SDA_OVR);
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udelay(5);
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octeon_i2c_write_int(i2c, 0x0);
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octeon_i2c_write_int(i2c, 0);
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}
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/* interrupt service routine */
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@ -192,17 +202,13 @@ static int octeon_i2c_test_iflg(struct octeon_i2c *i2c)
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*/
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static int octeon_i2c_wait(struct octeon_i2c *i2c)
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{
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long result;
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long time_left;
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octeon_i2c_int_enable(i2c);
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result = wait_event_timeout(i2c->queue,
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octeon_i2c_test_iflg(i2c),
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i2c->adap.timeout);
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time_left = wait_event_timeout(i2c->queue, octeon_i2c_test_iflg(i2c),
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i2c->adap.timeout);
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octeon_i2c_int_disable(i2c);
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if (result == 0) {
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if (!time_left) {
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dev_dbg(i2c->dev, "%s: timeout\n", __func__);
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return -ETIMEDOUT;
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}
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@ -218,11 +224,11 @@ static int octeon_i2c_wait(struct octeon_i2c *i2c)
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*/
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static int octeon_i2c_start(struct octeon_i2c *i2c)
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{
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u8 data;
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int result;
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u8 data;
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octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
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TWSI_CTL_ENAB | TWSI_CTL_STA);
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TWSI_CTL_ENAB | TWSI_CTL_STA);
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result = octeon_i2c_wait(i2c);
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if (result) {
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@ -235,7 +241,6 @@ static int octeon_i2c_start(struct octeon_i2c *i2c)
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octeon_i2c_unblock(i2c);
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octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
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TWSI_CTL_ENAB | TWSI_CTL_STA);
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result = octeon_i2c_wait(i2c);
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}
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if (result)
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@ -251,26 +256,11 @@ static int octeon_i2c_start(struct octeon_i2c *i2c)
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return 0;
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}
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/**
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* octeon_i2c_stop - send STOP to the bus
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* @i2c: The struct octeon_i2c
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*
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* Returns 0 on success, otherwise a negative errno.
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*/
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static int octeon_i2c_stop(struct octeon_i2c *i2c)
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/* send STOP to the bus */
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static void octeon_i2c_stop(struct octeon_i2c *i2c)
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{
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u8 data;
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octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
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TWSI_CTL_ENAB | TWSI_CTL_STP);
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data = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);
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if (data != STAT_IDLE) {
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dev_err(i2c->dev, "%s: bad status(0x%x)\n", __func__, data);
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return -EIO;
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}
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return 0;
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}
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/**
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@ -303,6 +293,7 @@ static int octeon_i2c_write(struct octeon_i2c *i2c, int target,
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for (i = 0; i < length; i++) {
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tmp = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);
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if ((tmp != STAT_TXADDR_ACK) && (tmp != STAT_TXDATA_ACK)) {
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dev_err(i2c->dev,
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"%s: bad status before write (0x%x)\n",
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@ -345,7 +336,7 @@ static int octeon_i2c_read(struct octeon_i2c *i2c, int target,
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if (result)
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return result;
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octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_DATA, (target<<1) | 1);
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octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_DATA, (target << 1) | 1);
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octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
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result = octeon_i2c_wait(i2c);
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@ -354,6 +345,7 @@ static int octeon_i2c_read(struct octeon_i2c *i2c, int target,
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for (i = 0; i < length; i++) {
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tmp = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);
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if ((tmp != STAT_RXDATA_ACK) && (tmp != STAT_RXADDR_ACK)) {
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dev_err(i2c->dev,
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"%s: bad status before read (0x%x)\n",
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@ -361,12 +353,12 @@ static int octeon_i2c_read(struct octeon_i2c *i2c, int target,
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return -EIO;
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}
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if (i+1 < length)
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if (i + 1 < length)
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octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
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TWSI_CTL_ENAB | TWSI_CTL_AAK);
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TWSI_CTL_ENAB | TWSI_CTL_AAK);
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else
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octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
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TWSI_CTL_ENAB);
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TWSI_CTL_ENAB);
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result = octeon_i2c_wait(i2c);
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if (result)
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@ -385,27 +377,25 @@ static int octeon_i2c_read(struct octeon_i2c *i2c, int target,
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*
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* Returns the number of messages processed, or a negative errno on failure.
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*/
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static int octeon_i2c_xfer(struct i2c_adapter *adap,
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struct i2c_msg *msgs,
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static int octeon_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
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int num)
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{
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struct i2c_msg *pmsg;
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int i;
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int ret = 0;
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struct octeon_i2c *i2c = i2c_get_adapdata(adap);
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int i, ret = 0;
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for (i = 0; ret == 0 && i < num; i++) {
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pmsg = &msgs[i];
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struct i2c_msg *pmsg = &msgs[i];
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dev_dbg(i2c->dev,
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"Doing %s %d byte(s) to/from 0x%02x - %d of %d messages\n",
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pmsg->flags & I2C_M_RD ? "read" : "write",
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pmsg->len, pmsg->addr, i + 1, num);
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if (pmsg->flags & I2C_M_RD)
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ret = octeon_i2c_read(i2c, pmsg->addr, pmsg->buf,
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pmsg->len);
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pmsg->len);
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else
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ret = octeon_i2c_write(i2c, pmsg->addr, pmsg->buf,
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pmsg->len);
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pmsg->len);
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}
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octeon_i2c_stop(i2c);
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@ -430,7 +420,7 @@ static struct i2c_adapter octeon_i2c_ops = {
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};
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/* calculate and set clock divisors */
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static int octeon_i2c_setclock(struct octeon_i2c *i2c)
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static void octeon_i2c_set_clock(struct octeon_i2c *i2c)
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{
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int tclk, thp_base, inc, thp_idx, mdiv_idx, ndiv_idx, foscl, diff;
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int thp = 0x18, mdiv = 2, ndiv = 0, delta_hz = 1000000;
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@ -438,8 +428,7 @@ static int octeon_i2c_setclock(struct octeon_i2c *i2c)
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for (ndiv_idx = 0; ndiv_idx < 8 && delta_hz != 0; ndiv_idx++) {
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/*
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* An mdiv value of less than 2 seems to not work well
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* with ds1337 RTCs, so we constrain it to larger
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* values.
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* with ds1337 RTCs, so we constrain it to larger values.
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*/
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for (mdiv_idx = 15; mdiv_idx >= 2 && delta_hz != 0; mdiv_idx--) {
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/*
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@ -449,6 +438,7 @@ static int octeon_i2c_setclock(struct octeon_i2c *i2c)
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tclk = i2c->twsi_freq * (mdiv_idx + 1) * 10;
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tclk *= (1 << ndiv_idx);
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thp_base = (i2c->sys_freq / (tclk * 2)) - 1;
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for (inc = 0; inc <= 1; inc++) {
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thp_idx = thp_base + inc;
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if (thp_idx < 5 || thp_idx > 0xff)
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@ -469,11 +459,9 @@ static int octeon_i2c_setclock(struct octeon_i2c *i2c)
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}
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octeon_i2c_write_sw(i2c, SW_TWSI_OP_TWSI_CLK, thp);
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octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CLKCTL, (mdiv << 3) | ndiv);
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return 0;
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}
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static int octeon_i2c_initlowlevel(struct octeon_i2c *i2c)
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static int octeon_i2c_init_lowlevel(struct octeon_i2c *i2c)
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{
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u8 status;
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int tries;
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@ -496,9 +484,10 @@ static int octeon_i2c_initlowlevel(struct octeon_i2c *i2c)
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static int octeon_i2c_probe(struct platform_device *pdev)
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{
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int irq, result = 0;
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struct octeon_i2c *i2c;
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struct device_node *node = pdev->dev.of_node;
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struct resource *res_mem;
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struct octeon_i2c *i2c;
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int irq, result = 0;
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/* All adaptors have an irq. */
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irq = platform_get_irq(pdev, 0);
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@ -507,7 +496,6 @@ static int octeon_i2c_probe(struct platform_device *pdev)
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i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
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if (!i2c) {
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dev_err(&pdev->dev, "kzalloc failed\n");
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result = -ENOMEM;
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goto out;
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}
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@ -528,10 +516,8 @@ static int octeon_i2c_probe(struct platform_device *pdev)
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* "clock-frequency". Try the official one first and then
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* fall back if it doesn't exist.
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*/
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if (of_property_read_u32(pdev->dev.of_node,
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"clock-frequency", &i2c->twsi_freq) &&
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of_property_read_u32(pdev->dev.of_node,
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"clock-rate", &i2c->twsi_freq)) {
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if (of_property_read_u32(node, "clock-frequency", &i2c->twsi_freq) &&
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of_property_read_u32(node, "clock-rate", &i2c->twsi_freq)) {
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dev_err(i2c->dev,
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"no I2C 'clock-rate' or 'clock-frequency' property\n");
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result = -ENXIO;
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@ -541,7 +527,7 @@ static int octeon_i2c_probe(struct platform_device *pdev)
|
|||
i2c->sys_freq = octeon_get_io_clock_rate();
|
||||
|
||||
if (!devm_request_mem_region(&pdev->dev, i2c->twsi_phys, i2c->regsize,
|
||||
res_mem->name)) {
|
||||
res_mem->name)) {
|
||||
dev_err(i2c->dev, "request_mem_region failed\n");
|
||||
goto out;
|
||||
}
|
||||
|
|
@ -558,21 +544,17 @@ static int octeon_i2c_probe(struct platform_device *pdev)
|
|||
goto out;
|
||||
}
|
||||
|
||||
result = octeon_i2c_initlowlevel(i2c);
|
||||
result = octeon_i2c_init_lowlevel(i2c);
|
||||
if (result) {
|
||||
dev_err(i2c->dev, "init low level failed\n");
|
||||
goto out;
|
||||
}
|
||||
|
||||
result = octeon_i2c_setclock(i2c);
|
||||
if (result) {
|
||||
dev_err(i2c->dev, "clock init failed\n");
|
||||
goto out;
|
||||
}
|
||||
octeon_i2c_set_clock(i2c);
|
||||
|
||||
i2c->adap = octeon_i2c_ops;
|
||||
i2c->adap.dev.parent = &pdev->dev;
|
||||
i2c->adap.dev.of_node = pdev->dev.of_node;
|
||||
i2c->adap.dev.of_node = node;
|
||||
i2c_set_adapdata(&i2c->adap, i2c);
|
||||
platform_set_drvdata(pdev, i2c);
|
||||
|
||||
|
|
@ -581,8 +563,7 @@ static int octeon_i2c_probe(struct platform_device *pdev)
|
|||
dev_err(i2c->dev, "failed to add adapter\n");
|
||||
goto out;
|
||||
}
|
||||
dev_info(i2c->dev, "version %s\n", DRV_VERSION);
|
||||
|
||||
dev_info(i2c->dev, "probed\n");
|
||||
return 0;
|
||||
|
||||
out:
|
||||
|
|
@ -597,10 +578,8 @@ static int octeon_i2c_remove(struct platform_device *pdev)
|
|||
return 0;
|
||||
};
|
||||
|
||||
static struct of_device_id octeon_i2c_match[] = {
|
||||
{
|
||||
.compatible = "cavium,octeon-3860-twsi",
|
||||
},
|
||||
static const struct of_device_id octeon_i2c_match[] = {
|
||||
{ .compatible = "cavium,octeon-3860-twsi", },
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, octeon_i2c_match);
|
||||
|
|
@ -619,4 +598,3 @@ module_platform_driver(octeon_i2c_driver);
|
|||
MODULE_AUTHOR("Michael Lawnick <michael.lawnick.ext@nsn.com>");
|
||||
MODULE_DESCRIPTION("I2C-Bus adapter for Cavium OCTEON processors");
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_VERSION(DRV_VERSION);
|
||||
|
|
|
|||
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