Just behavorial changes to a controller driver:
- Modified the Broadcom's Flexrm mailbox driver to support debugfs and TX-Done mechanism by ACK. Nothing for the core mailbox stack. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJZsDEqAAoJEH/ZZH/HmD+VQo4QAIArqs/lsbTnKLueGqFq3nVg gQUw4oJT0faqEWRNrDXTvp3sxO3kQwY0mUcKSX7E7zW8t9fUEvdTwVrRL5dw0ujf WEiO4MSeFGuelOyTNwrT4uds7ZMzydoqpFGLTBJGlfLTEULbkmj1S2n0OXBd0HAQ WpRL+3OSUsMz+gCX0Dd/uQ07NrBGFsPwCgW0aKVrK7whmBV/K95aStMSKxgxPUQX N97Etcg5IMdPuBXdAg/yQ9fq+8cjxzeOVOyRvYzAhTdgwaHI6rEcrYmVyhSepM1Y t3Bv9QSShfEoaSKofB9bYXqqP1PpzhrvgsmIUEGgBF/nTdEBnnkcgQ9yRcltDsuA uKwH9B/ISK9GU1/ZNGBo9+bHdCcEFUt7wFwIpTHmtJ7oAswb1OfiYGTAk3fhr9Tf I1hTNtW4LBsq8L9IJUvqlyP1RDemzjmCaLjUtZSkHThU6ltjzoLinuiqjW261ITq 4GxlS2A6fD7v8G4gHBPbLpO8xOZ8XGk+cAxlYi6hOH8qj55vSZCIpMvuTqbcTn/k bsR94JFDRIjuoRsIRMFwuw87WNqcPGIAwQm04nyFw6GNsTE70O74Dfnooqv1bJzT /mCKMw5en/SJVRZRerntPYOjaJLxBf92/lEVeSOagey0irTDrzovU2hiH+oyZAEw qqkUJoI4+4YwX7nhkLdG =N5tj -----END PGP SIGNATURE----- Merge tag 'mailbox-v4.14' of git://git.linaro.org/landing-teams/working/fujitsu/integration Pull mailbox updates from Jassi Brar: "Just behavorial changes to a controller driver: the Broadcom's Flexrm mailbox driver has been modifified to support debugfs and TX-Done mechanism by ACK. Nothing for the core mailbox stack" * tag 'mailbox-v4.14' of git://git.linaro.org/landing-teams/working/fujitsu/integration: mailbox: bcm-flexrm-mailbox: Use txdone_ack instead of txdone_poll mailbox: bcm-flexrm-mailbox: Use bitmap instead of IDA mailbox: bcm-flexrm-mailbox: Fix mask used in CMPL_START_ADDR_VALUE() mailbox: bcm-flexrm-mailbox: Add debugfs support mailbox: bcm-flexrm-mailbox: Set IRQ affinity hint for FlexRM ring IRQs
This commit is contained in:
Linus Torvalds
Коммит
dfd9e6d231
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@ -17,12 +17,14 @@
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#include <asm/barrier.h>
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#include <asm/byteorder.h>
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#include <linux/atomic.h>
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#include <linux/bitmap.h>
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#include <linux/debugfs.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/dma-mapping.h>
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#include <linux/dmapool.h>
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#include <linux/err.h>
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#include <linux/idr.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/mailbox_controller.h>
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@ -95,7 +97,7 @@
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/* Register RING_CMPL_START_ADDR fields */
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#define CMPL_START_ADDR_VALUE(pa) \
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((u32)((((u64)(pa)) >> RING_CMPL_ALIGN_ORDER) & 0x03ffffff))
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((u32)((((u64)(pa)) >> RING_CMPL_ALIGN_ORDER) & 0x07ffffff))
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/* Register RING_CONTROL fields */
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#define CONTROL_MASK_DISABLE_CONTROL 12
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@ -260,18 +262,21 @@ struct flexrm_ring {
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void __iomem *regs;
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bool irq_requested;
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unsigned int irq;
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cpumask_t irq_aff_hint;
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unsigned int msi_timer_val;
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unsigned int msi_count_threshold;
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struct ida requests_ida;
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struct brcm_message *requests[RING_MAX_REQ_COUNT];
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void *bd_base;
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dma_addr_t bd_dma_base;
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u32 bd_write_offset;
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void *cmpl_base;
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dma_addr_t cmpl_dma_base;
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/* Atomic stats */
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atomic_t msg_send_count;
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atomic_t msg_cmpl_count;
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/* Protected members */
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spinlock_t lock;
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struct brcm_message *last_pending_msg;
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DECLARE_BITMAP(requests_bmap, RING_MAX_REQ_COUNT);
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u32 cmpl_read_offset;
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};
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@ -282,6 +287,9 @@ struct flexrm_mbox {
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struct flexrm_ring *rings;
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struct dma_pool *bd_pool;
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struct dma_pool *cmpl_pool;
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struct dentry *root;
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struct dentry *config;
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struct dentry *stats;
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struct mbox_controller controller;
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};
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@ -912,6 +920,62 @@ static void *flexrm_write_descs(struct brcm_message *msg, u32 nhcnt,
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/* ====== FlexRM driver helper routines ===== */
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static void flexrm_write_config_in_seqfile(struct flexrm_mbox *mbox,
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struct seq_file *file)
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{
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int i;
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const char *state;
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struct flexrm_ring *ring;
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seq_printf(file, "%-5s %-9s %-18s %-10s %-18s %-10s\n",
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"Ring#", "State", "BD_Addr", "BD_Size",
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"Cmpl_Addr", "Cmpl_Size");
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for (i = 0; i < mbox->num_rings; i++) {
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ring = &mbox->rings[i];
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if (readl(ring->regs + RING_CONTROL) &
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BIT(CONTROL_ACTIVE_SHIFT))
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state = "active";
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else
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state = "inactive";
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seq_printf(file,
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"%-5d %-9s 0x%016llx 0x%08x 0x%016llx 0x%08x\n",
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ring->num, state,
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(unsigned long long)ring->bd_dma_base,
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(u32)RING_BD_SIZE,
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(unsigned long long)ring->cmpl_dma_base,
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(u32)RING_CMPL_SIZE);
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}
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}
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static void flexrm_write_stats_in_seqfile(struct flexrm_mbox *mbox,
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struct seq_file *file)
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{
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int i;
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u32 val, bd_read_offset;
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struct flexrm_ring *ring;
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seq_printf(file, "%-5s %-10s %-10s %-10s %-11s %-11s\n",
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"Ring#", "BD_Read", "BD_Write",
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"Cmpl_Read", "Submitted", "Completed");
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for (i = 0; i < mbox->num_rings; i++) {
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ring = &mbox->rings[i];
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bd_read_offset = readl_relaxed(ring->regs + RING_BD_READ_PTR);
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val = readl_relaxed(ring->regs + RING_BD_START_ADDR);
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bd_read_offset *= RING_DESC_SIZE;
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bd_read_offset += (u32)(BD_START_ADDR_DECODE(val) -
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ring->bd_dma_base);
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seq_printf(file, "%-5d 0x%08x 0x%08x 0x%08x %-11d %-11d\n",
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ring->num,
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(u32)bd_read_offset,
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(u32)ring->bd_write_offset,
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(u32)ring->cmpl_read_offset,
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(u32)atomic_read(&ring->msg_send_count),
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(u32)atomic_read(&ring->msg_cmpl_count));
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}
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}
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static int flexrm_new_request(struct flexrm_ring *ring,
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struct brcm_message *batch_msg,
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struct brcm_message *msg)
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@ -929,38 +993,24 @@ static int flexrm_new_request(struct flexrm_ring *ring,
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msg->error = 0;
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/* If no requests possible then save data pointer and goto done. */
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reqid = ida_simple_get(&ring->requests_ida, 0,
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RING_MAX_REQ_COUNT, GFP_KERNEL);
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if (reqid < 0) {
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spin_lock_irqsave(&ring->lock, flags);
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if (batch_msg)
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ring->last_pending_msg = batch_msg;
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else
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ring->last_pending_msg = msg;
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spin_unlock_irqrestore(&ring->lock, flags);
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return 0;
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}
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spin_lock_irqsave(&ring->lock, flags);
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reqid = bitmap_find_free_region(ring->requests_bmap,
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RING_MAX_REQ_COUNT, 0);
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spin_unlock_irqrestore(&ring->lock, flags);
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if (reqid < 0)
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return -ENOSPC;
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ring->requests[reqid] = msg;
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/* Do DMA mappings for the message */
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ret = flexrm_dma_map(ring->mbox->dev, msg);
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if (ret < 0) {
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ring->requests[reqid] = NULL;
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ida_simple_remove(&ring->requests_ida, reqid);
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spin_lock_irqsave(&ring->lock, flags);
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bitmap_release_region(ring->requests_bmap, reqid, 0);
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spin_unlock_irqrestore(&ring->lock, flags);
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return ret;
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}
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/* If last_pending_msg is already set then goto done with error */
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spin_lock_irqsave(&ring->lock, flags);
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if (ring->last_pending_msg)
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ret = -ENOSPC;
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spin_unlock_irqrestore(&ring->lock, flags);
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if (ret < 0) {
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dev_warn(ring->mbox->dev, "no space in ring %d\n", ring->num);
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exit_cleanup = true;
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goto exit;
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}
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/* Determine current HW BD read offset */
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read_offset = readl_relaxed(ring->regs + RING_BD_READ_PTR);
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val = readl_relaxed(ring->regs + RING_BD_START_ADDR);
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@ -987,13 +1037,7 @@ static int flexrm_new_request(struct flexrm_ring *ring,
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break;
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}
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if (count) {
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spin_lock_irqsave(&ring->lock, flags);
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if (batch_msg)
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ring->last_pending_msg = batch_msg;
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else
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ring->last_pending_msg = msg;
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spin_unlock_irqrestore(&ring->lock, flags);
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ret = 0;
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ret = -ENOSPC;
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exit_cleanup = true;
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goto exit;
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}
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@ -1012,6 +1056,9 @@ static int flexrm_new_request(struct flexrm_ring *ring,
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/* Save ring BD write offset */
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ring->bd_write_offset = (unsigned long)(next - ring->bd_base);
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/* Increment number of messages sent */
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atomic_inc_return(&ring->msg_send_count);
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exit:
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/* Update error status in message */
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msg->error = ret;
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@ -1020,7 +1067,9 @@ exit:
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if (exit_cleanup) {
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flexrm_dma_unmap(ring->mbox->dev, msg);
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ring->requests[reqid] = NULL;
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ida_simple_remove(&ring->requests_ida, reqid);
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spin_lock_irqsave(&ring->lock, flags);
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bitmap_release_region(ring->requests_bmap, reqid, 0);
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spin_unlock_irqrestore(&ring->lock, flags);
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}
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return ret;
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@ -1037,12 +1086,6 @@ static int flexrm_process_completions(struct flexrm_ring *ring)
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spin_lock_irqsave(&ring->lock, flags);
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/* Check last_pending_msg */
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if (ring->last_pending_msg) {
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msg = ring->last_pending_msg;
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ring->last_pending_msg = NULL;
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}
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/*
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* Get current completion read and write offset
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*
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@ -1058,10 +1101,6 @@ static int flexrm_process_completions(struct flexrm_ring *ring)
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spin_unlock_irqrestore(&ring->lock, flags);
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/* If last_pending_msg was set then queue it back */
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if (msg)
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mbox_send_message(chan, msg);
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/* For each completed request notify mailbox clients */
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reqid = 0;
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while (cmpl_read_offset != cmpl_write_offset) {
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@ -1095,7 +1134,9 @@ static int flexrm_process_completions(struct flexrm_ring *ring)
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/* Release reqid for recycling */
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ring->requests[reqid] = NULL;
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ida_simple_remove(&ring->requests_ida, reqid);
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spin_lock_irqsave(&ring->lock, flags);
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bitmap_release_region(ring->requests_bmap, reqid, 0);
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spin_unlock_irqrestore(&ring->lock, flags);
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/* Unmap DMA mappings */
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flexrm_dma_unmap(ring->mbox->dev, msg);
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@ -1105,12 +1146,37 @@ static int flexrm_process_completions(struct flexrm_ring *ring)
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mbox_chan_received_data(chan, msg);
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/* Increment number of completions processed */
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atomic_inc_return(&ring->msg_cmpl_count);
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count++;
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}
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return count;
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}
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/* ====== FlexRM Debugfs callbacks ====== */
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static int flexrm_debugfs_conf_show(struct seq_file *file, void *offset)
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{
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struct platform_device *pdev = to_platform_device(file->private);
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struct flexrm_mbox *mbox = platform_get_drvdata(pdev);
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/* Write config in file */
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flexrm_write_config_in_seqfile(mbox, file);
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return 0;
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}
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static int flexrm_debugfs_stats_show(struct seq_file *file, void *offset)
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{
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struct platform_device *pdev = to_platform_device(file->private);
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struct flexrm_mbox *mbox = platform_get_drvdata(pdev);
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/* Write stats in file */
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flexrm_write_stats_in_seqfile(mbox, file);
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return 0;
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}
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/* ====== FlexRM interrupt handler ===== */
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static irqreturn_t flexrm_irq_event(int irq, void *dev_id)
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@ -1217,6 +1283,18 @@ static int flexrm_startup(struct mbox_chan *chan)
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}
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ring->irq_requested = true;
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/* Set IRQ affinity hint */
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ring->irq_aff_hint = CPU_MASK_NONE;
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val = ring->mbox->num_rings;
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val = (num_online_cpus() < val) ? val / num_online_cpus() : 1;
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cpumask_set_cpu((ring->num / val) % num_online_cpus(),
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&ring->irq_aff_hint);
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ret = irq_set_affinity_hint(ring->irq, &ring->irq_aff_hint);
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if (ret) {
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dev_err(ring->mbox->dev, "failed to set IRQ affinity hint\n");
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goto fail_free_irq;
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}
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|
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/* Disable/inactivate ring */
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writel_relaxed(0x0, ring->regs + RING_CONTROL);
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|
|
@ -1233,9 +1311,6 @@ static int flexrm_startup(struct mbox_chan *chan)
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val = CMPL_START_ADDR_VALUE(ring->cmpl_dma_base);
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writel_relaxed(val, ring->regs + RING_CMPL_START_ADDR);
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|
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/* Ensure last pending message is cleared */
|
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ring->last_pending_msg = NULL;
|
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|
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/* Completion read pointer will be same as HW write pointer */
|
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ring->cmpl_read_offset =
|
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readl_relaxed(ring->regs + RING_CMPL_WRITE_PTR);
|
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|
|
@ -1259,8 +1334,15 @@ static int flexrm_startup(struct mbox_chan *chan)
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val = BIT(CONTROL_ACTIVE_SHIFT);
|
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writel_relaxed(val, ring->regs + RING_CONTROL);
|
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|
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/* Reset stats to zero */
|
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atomic_set(&ring->msg_send_count, 0);
|
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atomic_set(&ring->msg_cmpl_count, 0);
|
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|
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return 0;
|
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|
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fail_free_irq:
|
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free_irq(ring->irq, ring);
|
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ring->irq_requested = false;
|
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fail_free_cmpl_memory:
|
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dma_pool_free(ring->mbox->cmpl_pool,
|
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ring->cmpl_base, ring->cmpl_dma_base);
|
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|
|
@ -1302,7 +1384,6 @@ static void flexrm_shutdown(struct mbox_chan *chan)
|
|||
|
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/* Release reqid for recycling */
|
||||
ring->requests[reqid] = NULL;
|
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ida_simple_remove(&ring->requests_ida, reqid);
|
||||
|
||||
/* Unmap DMA mappings */
|
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flexrm_dma_unmap(ring->mbox->dev, msg);
|
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|
|
@ -1312,8 +1393,12 @@ static void flexrm_shutdown(struct mbox_chan *chan)
|
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mbox_chan_received_data(chan, msg);
|
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}
|
||||
|
||||
/* Clear requests bitmap */
|
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bitmap_zero(ring->requests_bmap, RING_MAX_REQ_COUNT);
|
||||
|
||||
/* Release IRQ */
|
||||
if (ring->irq_requested) {
|
||||
irq_set_affinity_hint(ring->irq, NULL);
|
||||
free_irq(ring->irq, ring);
|
||||
ring->irq_requested = false;
|
||||
}
|
||||
|
|
@ -1333,24 +1418,10 @@ static void flexrm_shutdown(struct mbox_chan *chan)
|
|||
}
|
||||
}
|
||||
|
||||
static bool flexrm_last_tx_done(struct mbox_chan *chan)
|
||||
{
|
||||
bool ret;
|
||||
unsigned long flags;
|
||||
struct flexrm_ring *ring = chan->con_priv;
|
||||
|
||||
spin_lock_irqsave(&ring->lock, flags);
|
||||
ret = (ring->last_pending_msg) ? false : true;
|
||||
spin_unlock_irqrestore(&ring->lock, flags);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct mbox_chan_ops flexrm_mbox_chan_ops = {
|
||||
.send_data = flexrm_send_data,
|
||||
.startup = flexrm_startup,
|
||||
.shutdown = flexrm_shutdown,
|
||||
.last_tx_done = flexrm_last_tx_done,
|
||||
.peek_data = flexrm_peek_data,
|
||||
};
|
||||
|
||||
|
|
@ -1468,14 +1539,15 @@ static int flexrm_mbox_probe(struct platform_device *pdev)
|
|||
ring->irq_requested = false;
|
||||
ring->msi_timer_val = MSI_TIMER_VAL_MASK;
|
||||
ring->msi_count_threshold = 0x1;
|
||||
ida_init(&ring->requests_ida);
|
||||
memset(ring->requests, 0, sizeof(ring->requests));
|
||||
ring->bd_base = NULL;
|
||||
ring->bd_dma_base = 0;
|
||||
ring->cmpl_base = NULL;
|
||||
ring->cmpl_dma_base = 0;
|
||||
atomic_set(&ring->msg_send_count, 0);
|
||||
atomic_set(&ring->msg_cmpl_count, 0);
|
||||
spin_lock_init(&ring->lock);
|
||||
ring->last_pending_msg = NULL;
|
||||
bitmap_zero(ring->requests_bmap, RING_MAX_REQ_COUNT);
|
||||
ring->cmpl_read_offset = 0;
|
||||
}
|
||||
|
||||
|
|
@ -1515,10 +1587,39 @@ static int flexrm_mbox_probe(struct platform_device *pdev)
|
|||
ring->irq = desc->irq;
|
||||
}
|
||||
|
||||
/* Check availability of debugfs */
|
||||
if (!debugfs_initialized())
|
||||
goto skip_debugfs;
|
||||
|
||||
/* Create debugfs root entry */
|
||||
mbox->root = debugfs_create_dir(dev_name(mbox->dev), NULL);
|
||||
if (IS_ERR_OR_NULL(mbox->root)) {
|
||||
ret = PTR_ERR_OR_ZERO(mbox->root);
|
||||
goto fail_free_msis;
|
||||
}
|
||||
|
||||
/* Create debugfs config entry */
|
||||
mbox->config = debugfs_create_devm_seqfile(mbox->dev,
|
||||
"config", mbox->root,
|
||||
flexrm_debugfs_conf_show);
|
||||
if (IS_ERR_OR_NULL(mbox->config)) {
|
||||
ret = PTR_ERR_OR_ZERO(mbox->config);
|
||||
goto fail_free_debugfs_root;
|
||||
}
|
||||
|
||||
/* Create debugfs stats entry */
|
||||
mbox->stats = debugfs_create_devm_seqfile(mbox->dev,
|
||||
"stats", mbox->root,
|
||||
flexrm_debugfs_stats_show);
|
||||
if (IS_ERR_OR_NULL(mbox->stats)) {
|
||||
ret = PTR_ERR_OR_ZERO(mbox->stats);
|
||||
goto fail_free_debugfs_root;
|
||||
}
|
||||
skip_debugfs:
|
||||
|
||||
/* Initialize mailbox controller */
|
||||
mbox->controller.txdone_irq = false;
|
||||
mbox->controller.txdone_poll = true;
|
||||
mbox->controller.txpoll_period = 1;
|
||||
mbox->controller.txdone_poll = false;
|
||||
mbox->controller.ops = &flexrm_mbox_chan_ops;
|
||||
mbox->controller.dev = dev;
|
||||
mbox->controller.num_chans = mbox->num_rings;
|
||||
|
|
@ -1527,7 +1628,7 @@ static int flexrm_mbox_probe(struct platform_device *pdev)
|
|||
sizeof(*mbox->controller.chans), GFP_KERNEL);
|
||||
if (!mbox->controller.chans) {
|
||||
ret = -ENOMEM;
|
||||
goto fail_free_msis;
|
||||
goto fail_free_debugfs_root;
|
||||
}
|
||||
for (index = 0; index < mbox->num_rings; index++)
|
||||
mbox->controller.chans[index].con_priv = &mbox->rings[index];
|
||||
|
|
@ -1535,13 +1636,15 @@ static int flexrm_mbox_probe(struct platform_device *pdev)
|
|||
/* Register mailbox controller */
|
||||
ret = mbox_controller_register(&mbox->controller);
|
||||
if (ret)
|
||||
goto fail_free_msis;
|
||||
goto fail_free_debugfs_root;
|
||||
|
||||
dev_info(dev, "registered flexrm mailbox with %d channels\n",
|
||||
mbox->controller.num_chans);
|
||||
|
||||
return 0;
|
||||
|
||||
fail_free_debugfs_root:
|
||||
debugfs_remove_recursive(mbox->root);
|
||||
fail_free_msis:
|
||||
platform_msi_domain_free_irqs(dev);
|
||||
fail_destroy_cmpl_pool:
|
||||
|
|
@ -1554,23 +1657,18 @@ fail:
|
|||
|
||||
static int flexrm_mbox_remove(struct platform_device *pdev)
|
||||
{
|
||||
int index;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct flexrm_ring *ring;
|
||||
struct flexrm_mbox *mbox = platform_get_drvdata(pdev);
|
||||
|
||||
mbox_controller_unregister(&mbox->controller);
|
||||
|
||||
debugfs_remove_recursive(mbox->root);
|
||||
|
||||
platform_msi_domain_free_irqs(dev);
|
||||
|
||||
dma_pool_destroy(mbox->cmpl_pool);
|
||||
dma_pool_destroy(mbox->bd_pool);
|
||||
|
||||
for (index = 0; index < mbox->num_rings; index++) {
|
||||
ring = &mbox->rings[index];
|
||||
ida_destroy(&ring->requests_ida);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
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