mtd: omap: adding DMA mode support in nand prefetch/post-write
This patch adds DMA mode support for nand prefetch/post-write engine. Signed-off-by: Vimal Singh <vimalsingh@ti.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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Коммит
dfe32893cb
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@ -88,6 +88,15 @@ config MTD_NAND_OMAP_PREFETCH
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The NAND device can be accessed for Read/Write using GPMC PREFETCH engine
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to improve the performance.
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config MTD_NAND_OMAP_PREFETCH_DMA
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depends on MTD_NAND_OMAP_PREFETCH
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bool "DMA mode"
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default n
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help
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The GPMC PREFETCH engine can be configured eigther in MPU interrupt mode
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or in DMA interrupt mode.
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Say y for DMA mode or MPU mode will be used
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config MTD_NAND_TS7250
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tristate "NAND Flash device on TS-7250 board"
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depends on MACH_TS72XX
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@ -18,8 +18,7 @@
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#include <linux/mtd/partitions.h>
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#include <linux/io.h>
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#include <asm/dma.h>
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#include <mach/dma.h>
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#include <mach/gpmc.h>
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#include <mach/nand.h>
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@ -118,8 +117,19 @@ static int use_prefetch = 1;
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/* "modprobe ... use_prefetch=0" etc */
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module_param(use_prefetch, bool, 0);
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MODULE_PARM_DESC(use_prefetch, "enable/disable use of PREFETCH");
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#ifdef CONFIG_MTD_NAND_OMAP_PREFETCH_DMA
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static int use_dma = 1;
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/* "modprobe ... use_dma=0" etc */
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module_param(use_dma, bool, 0);
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MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
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#else
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const int use_dma;
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#endif
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#else
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const int use_prefetch;
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const int use_dma;
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#endif
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struct omap_nand_info {
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@ -135,6 +145,8 @@ struct omap_nand_info {
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void __iomem *gpmc_cs_baseaddr;
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void __iomem *gpmc_baseaddr;
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void __iomem *nand_pref_fifo_add;
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struct completion comp;
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int dma_ch;
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};
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/**
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@ -355,6 +367,147 @@ static void omap_write_buf_pref(struct mtd_info *mtd,
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}
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}
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#ifdef CONFIG_MTD_NAND_OMAP_PREFETCH_DMA
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/*
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* omap_nand_dma_cb: callback on the completion of dma transfer
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* @lch: logical channel
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* @ch_satuts: channel status
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* @data: pointer to completion data structure
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*/
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static void omap_nand_dma_cb(int lch, u16 ch_status, void *data)
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{
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complete((struct completion *) data);
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}
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/*
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* omap_nand_dma_transfer: configer and start dma transfer
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* @mtd: MTD device structure
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* @addr: virtual address in RAM of source/destination
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* @len: number of data bytes to be transferred
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* @is_write: flag for read/write operation
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*/
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static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
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unsigned int len, int is_write)
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{
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struct omap_nand_info *info = container_of(mtd,
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struct omap_nand_info, mtd);
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uint32_t prefetch_status = 0;
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enum dma_data_direction dir = is_write ? DMA_TO_DEVICE :
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DMA_FROM_DEVICE;
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dma_addr_t dma_addr;
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int ret;
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/* The fifo depth is 64 bytes. We have a sync at each frame and frame
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* length is 64 bytes.
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*/
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int buf_len = len >> 6;
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if (addr >= high_memory) {
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struct page *p1;
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if (((size_t)addr & PAGE_MASK) !=
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((size_t)(addr + len - 1) & PAGE_MASK))
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goto out_copy;
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p1 = vmalloc_to_page(addr);
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if (!p1)
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goto out_copy;
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addr = page_address(p1) + ((size_t)addr & ~PAGE_MASK);
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}
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dma_addr = dma_map_single(&info->pdev->dev, addr, len, dir);
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if (dma_mapping_error(&info->pdev->dev, dma_addr)) {
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dev_err(&info->pdev->dev,
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"Couldn't DMA map a %d byte buffer\n", len);
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goto out_copy;
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}
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if (is_write) {
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omap_set_dma_dest_params(info->dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
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info->phys_base, 0, 0);
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omap_set_dma_src_params(info->dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
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dma_addr, 0, 0);
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omap_set_dma_transfer_params(info->dma_ch, OMAP_DMA_DATA_TYPE_S32,
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0x10, buf_len, OMAP_DMA_SYNC_FRAME,
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OMAP24XX_DMA_GPMC, OMAP_DMA_DST_SYNC);
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} else {
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omap_set_dma_src_params(info->dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
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info->phys_base, 0, 0);
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omap_set_dma_dest_params(info->dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
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dma_addr, 0, 0);
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omap_set_dma_transfer_params(info->dma_ch, OMAP_DMA_DATA_TYPE_S32,
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0x10, buf_len, OMAP_DMA_SYNC_FRAME,
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OMAP24XX_DMA_GPMC, OMAP_DMA_SRC_SYNC);
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}
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/* configure and start prefetch transfer */
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ret = gpmc_prefetch_enable(info->gpmc_cs, 0x1, len, is_write);
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if (ret)
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/* PFPW engine is busy, use cpu copy methode */
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goto out_copy;
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init_completion(&info->comp);
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omap_start_dma(info->dma_ch);
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/* setup and start DMA using dma_addr */
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wait_for_completion(&info->comp);
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while (0x3fff & (prefetch_status = gpmc_prefetch_status()))
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;
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/* disable and stop the PFPW engine */
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gpmc_prefetch_reset();
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dma_unmap_single(&info->pdev->dev, dma_addr, len, dir);
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return 0;
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out_copy:
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if (info->nand.options & NAND_BUSWIDTH_16)
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is_write == 0 ? omap_read_buf16(mtd, (u_char *) addr, len)
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: omap_write_buf16(mtd, (u_char *) addr, len);
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else
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is_write == 0 ? omap_read_buf8(mtd, (u_char *) addr, len)
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: omap_write_buf8(mtd, (u_char *) addr, len);
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return 0;
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}
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#else
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static void omap_nand_dma_cb(int lch, u16 ch_status, void *data) {}
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static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
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unsigned int len, int is_write)
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{
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return 0;
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}
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#endif
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/**
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* omap_read_buf_dma_pref - read data from NAND controller into buffer
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* @mtd: MTD device structure
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* @buf: buffer to store date
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* @len: number of bytes to read
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*/
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static void omap_read_buf_dma_pref(struct mtd_info *mtd, u_char *buf, int len)
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{
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if (len <= mtd->oobsize)
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omap_read_buf_pref(mtd, buf, len);
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else
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/* start transfer in DMA mode */
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omap_nand_dma_transfer(mtd, buf, len, 0x0);
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}
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/**
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* omap_write_buf_dma_pref - write buffer to NAND controller
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* @mtd: MTD device structure
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* @buf: data buffer
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* @len: number of bytes to write
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*/
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static void omap_write_buf_dma_pref(struct mtd_info *mtd,
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const u_char *buf, int len)
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{
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if (len <= mtd->oobsize)
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omap_write_buf_pref(mtd, buf, len);
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else
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/* start transfer in DMA mode */
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omap_nand_dma_transfer(mtd, buf, len, 0x1);
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}
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/**
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* omap_verify_buf - Verify chip data against buffer
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* @mtd: MTD device structure
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@ -821,6 +974,23 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
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info->nand.read_buf = omap_read_buf_pref;
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info->nand.write_buf = omap_write_buf_pref;
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if (use_dma) {
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err = omap_request_dma(OMAP24XX_DMA_GPMC, "NAND",
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omap_nand_dma_cb, &info->comp, &info->dma_ch);
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if (err < 0) {
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info->dma_ch = -1;
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printk(KERN_WARNING "DMA request failed."
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" Non-dma data transfer mode\n");
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} else {
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omap_set_dma_dest_burst_mode(info->dma_ch,
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OMAP_DMA_DATA_BURST_16);
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omap_set_dma_src_burst_mode(info->dma_ch,
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OMAP_DMA_DATA_BURST_16);
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info->nand.read_buf = omap_read_buf_dma_pref;
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info->nand.write_buf = omap_write_buf_dma_pref;
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}
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}
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} else {
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if (info->nand.options & NAND_BUSWIDTH_16) {
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info->nand.read_buf = omap_read_buf16;
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@ -887,6 +1057,9 @@ static int omap_nand_remove(struct platform_device *pdev)
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struct omap_nand_info *info = mtd->priv;
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platform_set_drvdata(pdev, NULL);
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if (use_dma)
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omap_free_dma(info->dma_ch);
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/* Release NAND device, its internal structures and partitions */
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nand_release(&info->mtd);
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iounmap(info->nand_pref_fifo_add);
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@ -906,6 +1079,15 @@ static struct platform_driver omap_nand_driver = {
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static int __init omap_nand_init(void)
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{
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printk(KERN_INFO "%s driver initializing\n", DRIVER_NAME);
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/* This check is required if driver is being
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* loaded run time as a module
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*/
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if ((1 == use_dma) && (0 == use_prefetch)) {
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printk(KERN_INFO"Wrong parameters: 'use_dma' can not be 1 "
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"without use_prefetch'. Prefetch will not be"
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" used in either mode (mpu or dma)\n");
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}
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return platform_driver_register(&omap_nand_driver);
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}
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