rtc: sirfsoc: move to regmap APIs from platform-specific APIs
The current codes use CSR platform specific API exported by machine
codes to read/write RTC registers. they are:
sirfsoc_rtc_iobrg_readl()
sirfsoc_rtc_iobrg_writel()
commit b1999477ed ("ARM: prima2: move to use REGMAP APIs for rtciobrg")
moves to regmap support, now we can move to use regmap APIs in RTC
driver.
Signed-off-by: Guo Zeng <guo.zeng@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
This commit is contained in:
Guo Zeng
Alexandre Belloni
Родитель
f4a2eecb3f
Коммит
dfe6c04aa2
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@ -13,6 +13,7 @@
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/regmap.h>
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#include <linux/rtc/sirfsoc_rtciobrg.h>
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@ -48,12 +49,27 @@ struct sirfsoc_rtc_drv {
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/* Overflow for every 8 years extra time */
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u32 overflow_rtc;
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spinlock_t lock;
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struct regmap *regmap;
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#ifdef CONFIG_PM
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u32 saved_counter;
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u32 saved_overflow_rtc;
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#endif
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};
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static u32 sirfsoc_rtc_readl(struct sirfsoc_rtc_drv *rtcdrv, u32 offset)
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{
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u32 val;
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regmap_read(rtcdrv->regmap, rtcdrv->rtc_base + offset, &val);
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return val;
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}
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static void sirfsoc_rtc_writel(struct sirfsoc_rtc_drv *rtcdrv,
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u32 offset, u32 val)
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{
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regmap_write(rtcdrv->regmap, rtcdrv->rtc_base + offset, val);
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}
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static int sirfsoc_rtc_read_alarm(struct device *dev,
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struct rtc_wkalrm *alrm)
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{
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@ -64,9 +80,9 @@ static int sirfsoc_rtc_read_alarm(struct device *dev,
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spin_lock_irq(&rtcdrv->lock);
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rtc_count = sirfsoc_rtc_iobrg_readl(rtcdrv->rtc_base + RTC_CN);
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rtc_count = sirfsoc_rtc_readl(rtcdrv, RTC_CN);
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rtc_alarm = sirfsoc_rtc_iobrg_readl(rtcdrv->rtc_base + RTC_ALARM0);
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rtc_alarm = sirfsoc_rtc_readl(rtcdrv, RTC_ALARM0);
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memset(alrm, 0, sizeof(struct rtc_wkalrm));
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/*
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@ -82,8 +98,7 @@ static int sirfsoc_rtc_read_alarm(struct device *dev,
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rtc_time_to_tm(rtcdrv->overflow_rtc
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<< (BITS_PER_LONG - RTC_SHIFT)
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| rtc_alarm >> RTC_SHIFT, &(alrm->time));
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if (sirfsoc_rtc_iobrg_readl(
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rtcdrv->rtc_base + RTC_STATUS) & SIRFSOC_RTC_AL0E)
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if (sirfsoc_rtc_readl(rtcdrv, RTC_STATUS) & SIRFSOC_RTC_AL0E)
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alrm->enabled = 1;
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spin_unlock_irq(&rtcdrv->lock);
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@ -103,8 +118,7 @@ static int sirfsoc_rtc_set_alarm(struct device *dev,
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spin_lock_irq(&rtcdrv->lock);
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rtc_status_reg = sirfsoc_rtc_iobrg_readl(
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rtcdrv->rtc_base + RTC_STATUS);
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rtc_status_reg = sirfsoc_rtc_readl(rtcdrv, RTC_STATUS);
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if (rtc_status_reg & SIRFSOC_RTC_AL0E) {
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/*
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* An ongoing alarm in progress - ingore it and not
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@ -113,8 +127,7 @@ static int sirfsoc_rtc_set_alarm(struct device *dev,
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dev_info(dev, "An old alarm was set, will be replaced by a new one\n");
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}
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sirfsoc_rtc_iobrg_writel(
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rtc_alarm << RTC_SHIFT, rtcdrv->rtc_base + RTC_ALARM0);
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sirfsoc_rtc_writel(rtcdrv, RTC_ALARM0, rtc_alarm << RTC_SHIFT);
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rtc_status_reg &= ~0x07; /* mask out the lower status bits */
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/*
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* This bit RTC_AL sets it as a wake-up source for Sleep Mode
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@ -123,8 +136,7 @@ static int sirfsoc_rtc_set_alarm(struct device *dev,
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rtc_status_reg |= SIRFSOC_RTC_AL0;
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/* enable the RTC alarm interrupt */
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rtc_status_reg |= SIRFSOC_RTC_AL0E;
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sirfsoc_rtc_iobrg_writel(
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rtc_status_reg, rtcdrv->rtc_base + RTC_STATUS);
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sirfsoc_rtc_writel(rtcdrv, RTC_STATUS, rtc_status_reg);
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spin_unlock_irq(&rtcdrv->lock);
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} else {
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@ -135,8 +147,7 @@ static int sirfsoc_rtc_set_alarm(struct device *dev,
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*/
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spin_lock_irq(&rtcdrv->lock);
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rtc_status_reg = sirfsoc_rtc_iobrg_readl(
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rtcdrv->rtc_base + RTC_STATUS);
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rtc_status_reg = sirfsoc_rtc_readl(rtcdrv, RTC_STATUS);
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if (rtc_status_reg & SIRFSOC_RTC_AL0E) {
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/* clear the RTC status register's alarm bit */
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rtc_status_reg &= ~0x07;
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@ -145,8 +156,8 @@ static int sirfsoc_rtc_set_alarm(struct device *dev,
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/* Clear the Alarm enable bit */
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rtc_status_reg &= ~(SIRFSOC_RTC_AL0E);
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sirfsoc_rtc_iobrg_writel(rtc_status_reg,
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rtcdrv->rtc_base + RTC_STATUS);
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sirfsoc_rtc_writel(rtcdrv, RTC_STATUS,
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rtc_status_reg);
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}
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spin_unlock_irq(&rtcdrv->lock);
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@ -167,9 +178,9 @@ static int sirfsoc_rtc_read_time(struct device *dev,
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* fail, read several times to make sure get stable value.
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*/
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do {
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tmp_rtc = sirfsoc_rtc_iobrg_readl(rtcdrv->rtc_base + RTC_CN);
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tmp_rtc = sirfsoc_rtc_readl(rtcdrv, RTC_CN);
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cpu_relax();
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} while (tmp_rtc != sirfsoc_rtc_iobrg_readl(rtcdrv->rtc_base + RTC_CN));
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} while (tmp_rtc != sirfsoc_rtc_readl(rtcdrv, RTC_CN));
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rtc_time_to_tm(rtcdrv->overflow_rtc << (BITS_PER_LONG - RTC_SHIFT) |
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tmp_rtc >> RTC_SHIFT, tm);
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@ -187,10 +198,8 @@ static int sirfsoc_rtc_set_time(struct device *dev,
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rtcdrv->overflow_rtc = rtc_time >> (BITS_PER_LONG - RTC_SHIFT);
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sirfsoc_rtc_iobrg_writel(rtcdrv->overflow_rtc,
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rtcdrv->rtc_base + RTC_SW_VALUE);
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sirfsoc_rtc_iobrg_writel(
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rtc_time << RTC_SHIFT, rtcdrv->rtc_base + RTC_CN);
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sirfsoc_rtc_writel(rtcdrv, RTC_SW_VALUE, rtcdrv->overflow_rtc);
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sirfsoc_rtc_writel(rtcdrv, RTC_CN, rtc_time << RTC_SHIFT);
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return 0;
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}
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@ -222,14 +231,13 @@ static int sirfsoc_rtc_alarm_irq_enable(struct device *dev,
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spin_lock_irq(&rtcdrv->lock);
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rtc_status_reg = sirfsoc_rtc_iobrg_readl(
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rtcdrv->rtc_base + RTC_STATUS);
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rtc_status_reg = sirfsoc_rtc_readl(rtcdrv, RTC_STATUS);
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if (enabled)
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rtc_status_reg |= SIRFSOC_RTC_AL0E;
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else
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rtc_status_reg &= ~SIRFSOC_RTC_AL0E;
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sirfsoc_rtc_iobrg_writel(rtc_status_reg, rtcdrv->rtc_base + RTC_STATUS);
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sirfsoc_rtc_writel(rtcdrv, RTC_STATUS, rtc_status_reg);
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spin_unlock_irq(&rtcdrv->lock);
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@ -254,7 +262,7 @@ static irqreturn_t sirfsoc_rtc_irq_handler(int irq, void *pdata)
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spin_lock(&rtcdrv->lock);
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rtc_status_reg = sirfsoc_rtc_iobrg_readl(rtcdrv->rtc_base + RTC_STATUS);
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rtc_status_reg = sirfsoc_rtc_readl(rtcdrv, RTC_STATUS);
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/* this bit will be set ONLY if an alarm was active
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* and it expired NOW
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* So this is being used as an ASSERT
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@ -270,7 +278,8 @@ static irqreturn_t sirfsoc_rtc_irq_handler(int irq, void *pdata)
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/* Clear the Alarm enable bit */
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rtc_status_reg &= ~(SIRFSOC_RTC_AL0E);
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}
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sirfsoc_rtc_iobrg_writel(rtc_status_reg, rtcdrv->rtc_base + RTC_STATUS);
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sirfsoc_rtc_writel(rtcdrv, RTC_STATUS, rtc_status_reg);
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spin_unlock(&rtcdrv->lock);
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@ -287,6 +296,13 @@ static const struct of_device_id sirfsoc_rtc_of_match[] = {
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{ .compatible = "sirf,prima2-sysrtc"},
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{},
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};
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const struct regmap_config sysrtc_regmap_config = {
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.reg_bits = 32,
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.val_bits = 32,
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.fast_io = true,
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};
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MODULE_DEVICE_TABLE(of, sirfsoc_rtc_of_match);
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static int sirfsoc_rtc_probe(struct platform_device *pdev)
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@ -314,27 +330,35 @@ static int sirfsoc_rtc_probe(struct platform_device *pdev)
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/* Register rtc alarm as a wakeup source */
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device_init_wakeup(&pdev->dev, 1);
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rtcdrv->regmap = devm_regmap_init_iobg(&pdev->dev,
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&sysrtc_regmap_config);
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if (IS_ERR(rtcdrv->regmap)) {
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err = PTR_ERR(rtcdrv->regmap);
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dev_err(&pdev->dev, "Failed to allocate register map: %d\n",
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err);
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return err;
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}
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/*
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* Set SYS_RTC counter in RTC_HZ HZ Units
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* We are using 32K RTC crystal (32768 / RTC_HZ / 2) -1
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* If 16HZ, therefore RTC_DIV = 1023;
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*/
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rtc_div = ((32768 / RTC_HZ) / 2) - 1;
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sirfsoc_rtc_iobrg_writel(rtc_div, rtcdrv->rtc_base + RTC_DIV);
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sirfsoc_rtc_writel(rtcdrv, RTC_DIV, rtc_div);
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/* 0x3 -> RTC_CLK */
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sirfsoc_rtc_iobrg_writel(SIRFSOC_RTC_CLK,
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rtcdrv->rtc_base + RTC_CLOCK_SWITCH);
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sirfsoc_rtc_writel(rtcdrv, RTC_CLOCK_SWITCH, SIRFSOC_RTC_CLK);
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/* reset SYS RTC ALARM0 */
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sirfsoc_rtc_iobrg_writel(0x0, rtcdrv->rtc_base + RTC_ALARM0);
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sirfsoc_rtc_writel(rtcdrv, RTC_ALARM0, 0x0);
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/* reset SYS RTC ALARM1 */
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sirfsoc_rtc_iobrg_writel(0x0, rtcdrv->rtc_base + RTC_ALARM1);
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sirfsoc_rtc_writel(rtcdrv, RTC_ALARM1, 0x0);
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/* Restore RTC Overflow From Register After Command Reboot */
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rtcdrv->overflow_rtc =
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sirfsoc_rtc_iobrg_readl(rtcdrv->rtc_base + RTC_SW_VALUE);
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sirfsoc_rtc_readl(rtcdrv, RTC_SW_VALUE);
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rtcdrv->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
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&sirfsoc_rtc_ops, THIS_MODULE);
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@ -372,10 +396,10 @@ static int sirfsoc_rtc_suspend(struct device *dev)
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{
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struct sirfsoc_rtc_drv *rtcdrv = dev_get_drvdata(dev);
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rtcdrv->overflow_rtc =
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sirfsoc_rtc_iobrg_readl(rtcdrv->rtc_base + RTC_SW_VALUE);
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sirfsoc_rtc_readl(rtcdrv, RTC_SW_VALUE);
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rtcdrv->saved_counter =
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sirfsoc_rtc_iobrg_readl(rtcdrv->rtc_base + RTC_CN);
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sirfsoc_rtc_readl(rtcdrv, RTC_CN);
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rtcdrv->saved_overflow_rtc = rtcdrv->overflow_rtc;
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if (device_may_wakeup(dev) && !enable_irq_wake(rtcdrv->irq))
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rtcdrv->irq_wake = 1;
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@ -392,12 +416,10 @@ static int sirfsoc_rtc_resume(struct device *dev)
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* if resume from snapshot and the rtc power is lost,
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* restroe the rtc settings
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*/
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if (SIRFSOC_RTC_CLK != sirfsoc_rtc_iobrg_readl(
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rtcdrv->rtc_base + RTC_CLOCK_SWITCH)) {
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if (SIRFSOC_RTC_CLK != sirfsoc_rtc_readl(rtcdrv, RTC_CLOCK_SWITCH)) {
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u32 rtc_div;
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/* 0x3 -> RTC_CLK */
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sirfsoc_rtc_iobrg_writel(SIRFSOC_RTC_CLK,
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rtcdrv->rtc_base + RTC_CLOCK_SWITCH);
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sirfsoc_rtc_writel(rtcdrv, RTC_CLOCK_SWITCH, SIRFSOC_RTC_CLK);
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/*
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* Set SYS_RTC counter in RTC_HZ HZ Units
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* We are using 32K RTC crystal (32768 / RTC_HZ / 2) -1
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@ -405,13 +427,13 @@ static int sirfsoc_rtc_resume(struct device *dev)
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*/
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rtc_div = ((32768 / RTC_HZ) / 2) - 1;
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sirfsoc_rtc_iobrg_writel(rtc_div, rtcdrv->rtc_base + RTC_DIV);
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sirfsoc_rtc_writel(rtcdrv, RTC_DIV, rtc_div);
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/* reset SYS RTC ALARM0 */
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sirfsoc_rtc_iobrg_writel(0x0, rtcdrv->rtc_base + RTC_ALARM0);
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sirfsoc_rtc_writel(rtcdrv, RTC_ALARM0, 0x0);
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/* reset SYS RTC ALARM1 */
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sirfsoc_rtc_iobrg_writel(0x0, rtcdrv->rtc_base + RTC_ALARM1);
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sirfsoc_rtc_writel(rtcdrv, RTC_ALARM1, 0x0);
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}
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rtcdrv->overflow_rtc = rtcdrv->saved_overflow_rtc;
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@ -419,15 +441,14 @@ static int sirfsoc_rtc_resume(struct device *dev)
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* if current counter is small than previous,
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* it means overflow in sleep
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*/
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tmp = sirfsoc_rtc_iobrg_readl(rtcdrv->rtc_base + RTC_CN);
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tmp = sirfsoc_rtc_readl(rtcdrv, RTC_CN);
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if (tmp <= rtcdrv->saved_counter)
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rtcdrv->overflow_rtc++;
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/*
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*PWRC Value Be Changed When Suspend, Restore Overflow
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* In Memory To Register
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*/
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sirfsoc_rtc_iobrg_writel(rtcdrv->overflow_rtc,
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rtcdrv->rtc_base + RTC_SW_VALUE);
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sirfsoc_rtc_writel(rtcdrv, RTC_SW_VALUE, rtcdrv->overflow_rtc);
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if (device_may_wakeup(dev) && rtcdrv->irq_wake) {
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disable_irq_wake(rtcdrv->irq);
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