KVM: MIPS/VZ: Support guest CP0_[X]ContextConfig
Add support for VZ guest CP0_ContextConfig and CP0_XContextConfig (MIPS64 only) registers, as found on P5600 and P6600 cores. These guest registers need initialising, context switching, and exposing via the KVM ioctl API when they are present. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: "Radim Krčmář" <rkrcmar@redhat.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Jonathan Corbet <corbet@lwn.net> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Cc: linux-doc@vger.kernel.org
This commit is contained in:
James Hogan
Родитель
edc89260d4
Коммит
dffe042fd8
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@ -2073,7 +2073,9 @@ registers, find a list below:
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MIPS | KVM_REG_MIPS_CP0_ENTRYLO0 | 64
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MIPS | KVM_REG_MIPS_CP0_ENTRYLO1 | 64
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MIPS | KVM_REG_MIPS_CP0_CONTEXT | 64
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MIPS | KVM_REG_MIPS_CP0_CONTEXTCONFIG| 32
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MIPS | KVM_REG_MIPS_CP0_USERLOCAL | 64
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MIPS | KVM_REG_MIPS_CP0_XCONTEXTCONFIG| 64
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MIPS | KVM_REG_MIPS_CP0_PAGEMASK | 32
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MIPS | KVM_REG_MIPS_CP0_PAGEGRAIN | 32
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MIPS | KVM_REG_MIPS_CP0_WIRED | 32
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@ -34,7 +34,9 @@
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#define KVM_REG_MIPS_CP0_ENTRYLO0 MIPS_CP0_64(2, 0)
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#define KVM_REG_MIPS_CP0_ENTRYLO1 MIPS_CP0_64(3, 0)
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#define KVM_REG_MIPS_CP0_CONTEXT MIPS_CP0_64(4, 0)
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#define KVM_REG_MIPS_CP0_CONTEXTCONFIG MIPS_CP0_32(4, 1)
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#define KVM_REG_MIPS_CP0_USERLOCAL MIPS_CP0_64(4, 2)
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#define KVM_REG_MIPS_CP0_XCONTEXTCONFIG MIPS_CP0_64(4, 3)
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#define KVM_REG_MIPS_CP0_PAGEMASK MIPS_CP0_32(5, 0)
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#define KVM_REG_MIPS_CP0_PAGEGRAIN MIPS_CP0_32(5, 1)
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#define KVM_REG_MIPS_CP0_WIRED MIPS_CP0_32(6, 0)
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@ -665,7 +667,9 @@ __BUILD_KVM_RW_HW(index, 32, MIPS_CP0_TLB_INDEX, 0)
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__BUILD_KVM_RW_HW(entrylo0, l, MIPS_CP0_TLB_LO0, 0)
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__BUILD_KVM_RW_HW(entrylo1, l, MIPS_CP0_TLB_LO1, 0)
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__BUILD_KVM_RW_HW(context, l, MIPS_CP0_TLB_CONTEXT, 0)
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__BUILD_KVM_RW_HW(contextconfig, 32, MIPS_CP0_TLB_CONTEXT, 1)
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__BUILD_KVM_RW_HW(userlocal, l, MIPS_CP0_TLB_CONTEXT, 2)
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__BUILD_KVM_RW_HW(xcontextconfig, l, MIPS_CP0_TLB_CONTEXT, 3)
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__BUILD_KVM_RW_HW(pagemask, l, MIPS_CP0_TLB_PG_MASK, 0)
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__BUILD_KVM_RW_HW(pagegrain, 32, MIPS_CP0_TLB_PG_MASK, 1)
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__BUILD_KVM_RW_HW(wired, 32, MIPS_CP0_TLB_WIRED, 0)
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@ -131,7 +131,7 @@ static inline unsigned int kvm_vz_config5_guest_wrmask(struct kvm_vcpu *vcpu)
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* Config: M, [MT]
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* Config1: M, [MMUSize-1, C2, MD, PC, WR, CA], FP
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* Config2: M
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* Config3: M, MSAP, [BPG], ULRI, [DSP2P, DSPP, CTXTC, ITL, LPA, VEIC,
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* Config3: M, MSAP, [BPG], ULRI, [DSP2P, DSPP], CTXTC, [ITL, LPA, VEIC,
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* VInt, SP, CDMM, MT, SM, TL]
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* Config4: M, [VTLBSizeExt, MMUSizeExt]
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* Config5: [MRP]
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@ -161,7 +161,7 @@ static inline unsigned int kvm_vz_config2_user_wrmask(struct kvm_vcpu *vcpu)
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static inline unsigned int kvm_vz_config3_user_wrmask(struct kvm_vcpu *vcpu)
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{
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unsigned int mask = kvm_vz_config3_guest_wrmask(vcpu) | MIPS_CONF_M |
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MIPS_CONF3_ULRI;
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MIPS_CONF3_ULRI | MIPS_CONF3_CTXTC;
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/* Permit MSA to be present if MSA is supported */
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if (kvm_mips_guest_can_have_msa(&vcpu->arch))
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@ -1205,6 +1205,13 @@ static u64 kvm_vz_get_one_regs[] = {
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KVM_REG_MIPS_COUNT_HZ,
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};
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static u64 kvm_vz_get_one_regs_contextconfig[] = {
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KVM_REG_MIPS_CP0_CONTEXTCONFIG,
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#ifdef CONFIG_64BIT
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KVM_REG_MIPS_CP0_XCONTEXTCONFIG,
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#endif
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};
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static u64 kvm_vz_get_one_regs_kscratch[] = {
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KVM_REG_MIPS_CP0_KSCRATCH1,
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KVM_REG_MIPS_CP0_KSCRATCH2,
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@ -1225,6 +1232,8 @@ static unsigned long kvm_vz_num_regs(struct kvm_vcpu *vcpu)
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++ret;
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if (cpu_guest_has_badinstrp)
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++ret;
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if (cpu_guest_has_contextconfig)
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ret += ARRAY_SIZE(kvm_vz_get_one_regs_contextconfig);
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ret += __arch_hweight8(cpu_data[0].guest.kscratch_mask);
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return ret;
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@ -1258,6 +1267,12 @@ static int kvm_vz_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices)
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return -EFAULT;
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++indices;
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}
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if (cpu_guest_has_contextconfig) {
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if (copy_to_user(indices, kvm_vz_get_one_regs_contextconfig,
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sizeof(kvm_vz_get_one_regs_contextconfig)))
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return -EFAULT;
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indices += ARRAY_SIZE(kvm_vz_get_one_regs_contextconfig);
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}
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for (i = 0; i < 6; ++i) {
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if (!cpu_guest_has_kscr(i + 2))
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continue;
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@ -1323,11 +1338,23 @@ static int kvm_vz_get_one_reg(struct kvm_vcpu *vcpu,
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case KVM_REG_MIPS_CP0_CONTEXT:
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*v = (long)read_gc0_context();
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break;
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case KVM_REG_MIPS_CP0_CONTEXTCONFIG:
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if (!cpu_guest_has_contextconfig)
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return -EINVAL;
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*v = read_gc0_contextconfig();
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break;
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case KVM_REG_MIPS_CP0_USERLOCAL:
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if (!cpu_guest_has_userlocal)
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return -EINVAL;
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*v = read_gc0_userlocal();
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break;
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#ifdef CONFIG_64BIT
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case KVM_REG_MIPS_CP0_XCONTEXTCONFIG:
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if (!cpu_guest_has_contextconfig)
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return -EINVAL;
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*v = read_gc0_xcontextconfig();
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break;
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#endif
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case KVM_REG_MIPS_CP0_PAGEMASK:
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*v = (long)read_gc0_pagemask();
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break;
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@ -1478,11 +1505,23 @@ static int kvm_vz_set_one_reg(struct kvm_vcpu *vcpu,
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case KVM_REG_MIPS_CP0_CONTEXT:
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write_gc0_context(v);
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break;
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case KVM_REG_MIPS_CP0_CONTEXTCONFIG:
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if (!cpu_guest_has_contextconfig)
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return -EINVAL;
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write_gc0_contextconfig(v);
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break;
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case KVM_REG_MIPS_CP0_USERLOCAL:
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if (!cpu_guest_has_userlocal)
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return -EINVAL;
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write_gc0_userlocal(v);
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break;
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#ifdef CONFIG_64BIT
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case KVM_REG_MIPS_CP0_XCONTEXTCONFIG:
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if (!cpu_guest_has_contextconfig)
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return -EINVAL;
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write_gc0_xcontextconfig(v);
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break;
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#endif
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case KVM_REG_MIPS_CP0_PAGEMASK:
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write_gc0_pagemask(v);
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break;
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@ -1874,8 +1913,12 @@ static int kvm_vz_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
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kvm_restore_gc0_entrylo0(cop0);
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kvm_restore_gc0_entrylo1(cop0);
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kvm_restore_gc0_context(cop0);
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if (cpu_guest_has_contextconfig)
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kvm_restore_gc0_contextconfig(cop0);
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#ifdef CONFIG_64BIT
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kvm_restore_gc0_xcontext(cop0);
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if (cpu_guest_has_contextconfig)
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kvm_restore_gc0_xcontextconfig(cop0);
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#endif
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kvm_restore_gc0_pagemask(cop0);
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kvm_restore_gc0_pagegrain(cop0);
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@ -1933,8 +1976,12 @@ static int kvm_vz_vcpu_put(struct kvm_vcpu *vcpu, int cpu)
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kvm_save_gc0_entrylo0(cop0);
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kvm_save_gc0_entrylo1(cop0);
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kvm_save_gc0_context(cop0);
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if (cpu_guest_has_contextconfig)
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kvm_save_gc0_contextconfig(cop0);
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#ifdef CONFIG_64BIT
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kvm_save_gc0_xcontext(cop0);
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if (cpu_guest_has_contextconfig)
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kvm_save_gc0_xcontextconfig(cop0);
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#endif
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kvm_save_gc0_pagemask(cop0);
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kvm_save_gc0_pagegrain(cop0);
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@ -2298,6 +2345,17 @@ static int kvm_vz_vcpu_setup(struct kvm_vcpu *vcpu)
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kvm_clear_sw_gc0_config5(cop0, MIPS_CONF5_MRP);
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}
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if (cpu_guest_has_contextconfig) {
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/* ContextConfig */
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kvm_write_sw_gc0_contextconfig(cop0, 0x007ffff0);
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#ifdef CONFIG_64BIT
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/* XContextConfig */
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/* bits SEGBITS-13+3:4 set */
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kvm_write_sw_gc0_xcontextconfig(cop0,
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((1ull << (cpu_vmbits - 13)) - 1) << 4);
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#endif
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}
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/* start with no pending virtual guest interrupts */
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if (cpu_has_guestctl2)
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cop0->reg[MIPS_CP0_GUESTCTL2][MIPS_CP0_GUESTCTL2_SEL] = 0;
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