ASoC: SOF: mediatek: Add mt8186 ipc support
mt8186 DSP uses two hardware mailbox IP to communicate with AP. One mailbox is used for requests coming from AP, and the other one is for requests from DSP. Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng@mediatek.com> Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> Link: https://lore.kernel.org/r/20220512082215.3018-4-tinghan.shen@mediatek.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Tinghan Shen
Mark Brown
Родитель
aea9350108
Коммит
e0100bfd38
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@ -24,6 +24,7 @@ config SND_SOC_SOF_MTK_COMMON
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config SND_SOC_SOF_MT8186
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tristate "SOF support for MT8186 audio DSP"
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select SND_SOC_SOF_MTK_COMMON
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depends on MTK_ADSP_IPC
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help
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This adds support for Sound Open Firmware for Mediatek platforms
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using the mt8186 processors.
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@ -17,6 +17,11 @@ void mt8186_sof_hifixdsp_boot_sequence(struct snd_sof_dev *sdev, u32 boot_addr)
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snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, ADSP_HIFI_IO_CONFIG,
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RUNSTALL, RUNSTALL);
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/* enable mbox 0 & 1 IRQ */
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snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, ADSP_MBOX_IRQ_EN,
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DSP_MBOX0_IRQ_EN | DSP_MBOX1_IRQ_EN,
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DSP_MBOX0_IRQ_EN | DSP_MBOX1_IRQ_EN);
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/* set core boot address */
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snd_sof_dsp_write(sdev, DSP_SECREG_BAR, ADSP_ALTVEC_C0, boot_addr);
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snd_sof_dsp_write(sdev, DSP_SECREG_BAR, ADSP_ALTVECSEL, ADSP_ALTVECSEL_C0);
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@ -27,6 +27,99 @@
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#include "mt8186.h"
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#include "mt8186-clk.h"
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static int mt8186_get_mailbox_offset(struct snd_sof_dev *sdev)
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{
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return MBOX_OFFSET;
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}
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static int mt8186_get_window_offset(struct snd_sof_dev *sdev, u32 id)
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{
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return MBOX_OFFSET;
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}
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static int mt8186_send_msg(struct snd_sof_dev *sdev,
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struct snd_sof_ipc_msg *msg)
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{
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struct adsp_priv *priv = sdev->pdata->hw_pdata;
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sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data,
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msg->msg_size);
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return mtk_adsp_ipc_send(priv->dsp_ipc, MTK_ADSP_IPC_REQ, MTK_ADSP_IPC_OP_REQ);
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}
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static void mt8186_get_reply(struct snd_sof_dev *sdev)
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{
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struct snd_sof_ipc_msg *msg = sdev->msg;
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struct sof_ipc_reply reply;
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int ret = 0;
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if (!msg) {
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dev_warn(sdev->dev, "unexpected ipc interrupt\n");
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return;
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}
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/* get reply */
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sof_mailbox_read(sdev, sdev->host_box.offset, &reply, sizeof(reply));
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if (reply.error < 0) {
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memcpy(msg->reply_data, &reply, sizeof(reply));
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ret = reply.error;
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} else {
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/* reply has correct size? */
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if (reply.hdr.size != msg->reply_size) {
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dev_err(sdev->dev, "error: reply expected %zu got %u bytes\n",
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msg->reply_size, reply.hdr.size);
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ret = -EINVAL;
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}
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/* read the message */
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if (msg->reply_size > 0)
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sof_mailbox_read(sdev, sdev->host_box.offset,
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msg->reply_data, msg->reply_size);
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}
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msg->reply_error = ret;
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}
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static void mt8186_dsp_handle_reply(struct mtk_adsp_ipc *ipc)
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{
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struct adsp_priv *priv = mtk_adsp_ipc_get_data(ipc);
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unsigned long flags;
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spin_lock_irqsave(&priv->sdev->ipc_lock, flags);
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mt8186_get_reply(priv->sdev);
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snd_sof_ipc_reply(priv->sdev, 0);
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spin_unlock_irqrestore(&priv->sdev->ipc_lock, flags);
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}
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static void mt8186_dsp_handle_request(struct mtk_adsp_ipc *ipc)
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{
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struct adsp_priv *priv = mtk_adsp_ipc_get_data(ipc);
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u32 p; /* panic code */
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int ret;
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/* Read the message from the debug box. */
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sof_mailbox_read(priv->sdev, priv->sdev->debug_box.offset + 4,
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&p, sizeof(p));
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/* Check to see if the message is a panic code 0x0dead*** */
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if ((p & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC) {
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snd_sof_dsp_panic(priv->sdev, p, true);
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} else {
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snd_sof_ipc_msgs_rx(priv->sdev);
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/* tell DSP cmd is done */
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ret = mtk_adsp_ipc_send(priv->dsp_ipc, MTK_ADSP_IPC_RSP, MTK_ADSP_IPC_OP_RSP);
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if (ret)
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dev_err(priv->dev, "request send ipc failed");
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}
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}
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static struct mtk_adsp_ipc_ops dsp_ops = {
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.handle_reply = mt8186_dsp_handle_reply,
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.handle_request = mt8186_dsp_handle_request,
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};
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static int platform_parse_resource(struct platform_device *pdev, void *data)
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{
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struct resource *mmio;
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@ -271,6 +364,9 @@ static int mt8186_dsp_probe(struct snd_sof_dev *sdev)
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sdev->mmio_bar = SOF_FW_BLK_TYPE_SRAM;
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sdev->mailbox_bar = SOF_FW_BLK_TYPE_SRAM;
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/* set default mailbox offset for FW ready message */
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sdev->dsp_box.offset = mt8186_get_mailbox_offset(sdev);
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ret = adsp_memory_remap_init(sdev, priv->adsp);
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if (ret) {
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dev_err(sdev->dev, "adsp_memory_remap_init fail!\n");
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@ -292,11 +388,41 @@ static int mt8186_dsp_probe(struct snd_sof_dev *sdev)
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adsp_sram_power_on(sdev);
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priv->ipc_dev = platform_device_register_data(&pdev->dev, "mtk-adsp-ipc",
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PLATFORM_DEVID_NONE,
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pdev, sizeof(*pdev));
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if (IS_ERR(priv->ipc_dev)) {
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ret = IS_ERR(priv->ipc_dev);
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dev_err(sdev->dev, "failed to create mtk-adsp-ipc device\n");
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goto err_adsp_off;
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}
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priv->dsp_ipc = dev_get_drvdata(&priv->ipc_dev->dev);
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if (!priv->dsp_ipc) {
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ret = -EPROBE_DEFER;
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dev_err(sdev->dev, "failed to get drvdata\n");
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goto exit_pdev_unregister;
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}
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mtk_adsp_ipc_set_data(priv->dsp_ipc, priv);
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priv->dsp_ipc->ops = &dsp_ops;
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return 0;
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exit_pdev_unregister:
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platform_device_unregister(priv->ipc_dev);
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err_adsp_off:
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adsp_sram_power_off(sdev);
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mt8186_adsp_clock_off(sdev);
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return ret;
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}
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static int mt8186_dsp_remove(struct snd_sof_dev *sdev)
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{
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struct adsp_priv *priv = sdev->pdata->hw_pdata;
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platform_device_unregister(priv->ipc_dev);
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mt8186_sof_hifixdsp_shutdown(sdev);
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adsp_sram_power_off(sdev);
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mt8186_adsp_clock_off(sdev);
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@ -334,6 +460,14 @@ static int mt8186_get_bar_index(struct snd_sof_dev *sdev, u32 type)
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return type;
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}
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static int mt8186_ipc_msg_data(struct snd_sof_dev *sdev,
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struct snd_pcm_substream *substream,
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void *p, size_t sz)
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{
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sof_mailbox_read(sdev, sdev->dsp_box.offset, p, sz);
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return 0;
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}
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/* mt8186 ops */
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static struct snd_sof_dsp_ops sof_mt8186_ops = {
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/* probe and remove */
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@ -353,6 +487,13 @@ static struct snd_sof_dsp_ops sof_mt8186_ops = {
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.write64 = sof_io_write64,
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.read64 = sof_io_read64,
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/* ipc */
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.send_msg = mt8186_send_msg,
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.get_mailbox_offset = mt8186_get_mailbox_offset,
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.get_window_offset = mt8186_get_window_offset,
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.ipc_msg_data = mt8186_ipc_msg_data,
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.set_stream_data_offset = sof_set_stream_data_offset,
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/* misc */
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.get_bar_index = mt8186_get_bar_index,
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