Renesas fixes for v5.14
- Fix a clock/reset handling design issue on the new RZ/G2L SoC,
requiring an atomic change to DT binding definitions, clock driver,
and DTS,
- Restore graphical consoles in the shmobile_defconfig.
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Merge tag 'renesas-fixes-for-v5.14-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/fixes
Renesas fixes for v5.14
- Fix a clock/reset handling design issue on the new RZ/G2L SoC,
requiring an atomic change to DT binding definitions, clock driver,
and DTS,
- Restore graphical consoles in the shmobile_defconfig.
* tag 'renesas-fixes-for-v5.14-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
ARM: shmobile: defconfig: Restore graphical consoles
dt-bindings: clock: r9a07g044-cpg: Update clock/reset definitions
clk: renesas: r9a07g044: Add P2 Clock support
clk: renesas: r9a07g044: Fix P1 Clock
clk: renesas: r9a07g044: Rename divider table
clk: renesas: rzg2l: Add multi clock PM support
Link: https://lore.kernel.org/r/cover.1626253929.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
Коммит
e0129a0e82
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@ -135,6 +135,7 @@ CONFIG_DRM_SII902X=y
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CONFIG_DRM_SIMPLE_BRIDGE=y
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CONFIG_DRM_I2C_ADV7511=y
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CONFIG_DRM_I2C_ADV7511_AUDIO=y
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CONFIG_FB=y
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CONFIG_FB_SH_MOBILE_LCDC=y
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CONFIG_BACKLIGHT_PWM=y
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CONFIG_BACKLIGHT_AS3711=y
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@ -82,10 +82,10 @@
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<GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "eri", "rxi", "txi",
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"bri", "dri", "tei";
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clocks = <&cpg CPG_MOD R9A07G044_CLK_SCIF0>;
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clocks = <&cpg CPG_MOD R9A07G044_SCIF0_CLK_PCK>;
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clock-names = "fck";
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power-domains = <&cpg>;
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resets = <&cpg R9A07G044_CLK_SCIF0>;
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resets = <&cpg R9A07G044_SCIF0_RST_SYSTEM_N>;
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status = "disabled";
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};
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@ -30,8 +30,9 @@ enum clk_ids {
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CLK_PLL2_DIV20,
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CLK_PLL3,
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CLK_PLL3_DIV2,
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CLK_PLL3_DIV2_4,
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CLK_PLL3_DIV2_4_2,
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CLK_PLL3_DIV4,
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CLK_PLL3_DIV8,
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CLK_PLL4,
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CLK_PLL5,
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CLK_PLL5_DIV2,
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@ -42,12 +43,13 @@ enum clk_ids {
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};
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/* Divider tables */
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static const struct clk_div_table dtable_3b[] = {
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static const struct clk_div_table dtable_1_32[] = {
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{0, 1},
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{1, 2},
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{2, 4},
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{3, 8},
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{4, 32},
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{0, 0},
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};
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static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {
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@ -66,47 +68,56 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {
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DEF_FIXED(".pll2_div20", CLK_PLL2_DIV20, CLK_PLL2, 1, 20),
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DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2),
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DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4),
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DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2),
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DEF_FIXED(".pll3_div4", CLK_PLL3_DIV4, CLK_PLL3, 1, 4),
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DEF_FIXED(".pll3_div8", CLK_PLL3_DIV8, CLK_PLL3, 1, 8),
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/* Core output clk */
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DEF_FIXED("I", R9A07G044_CLK_I, CLK_PLL1, 1, 1),
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DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV16, DIVPL2A,
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dtable_3b, CLK_DIVIDER_HIWORD_MASK),
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dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
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DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV20, 1, 1),
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DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV8,
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DIVPL3B, dtable_3b, CLK_DIVIDER_HIWORD_MASK),
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DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV2_4,
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DIVPL3B, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
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DEF_DIV("P2", R9A07G044_CLK_P2, CLK_PLL3_DIV2_4_2,
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DIVPL3A, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
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};
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static struct rzg2l_mod_clk r9a07g044_mod_clks[] = {
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DEF_MOD("gic", R9A07G044_CLK_GIC600,
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R9A07G044_CLK_P1,
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0x514, BIT(0), (BIT(0) | BIT(1))),
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DEF_MOD("ia55", R9A07G044_CLK_IA55,
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R9A07G044_CLK_P1,
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0x518, (BIT(0) | BIT(1)), BIT(0)),
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DEF_MOD("scif0", R9A07G044_CLK_SCIF0,
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R9A07G044_CLK_P0,
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0x584, BIT(0), BIT(0)),
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DEF_MOD("scif1", R9A07G044_CLK_SCIF1,
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R9A07G044_CLK_P0,
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0x584, BIT(1), BIT(1)),
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DEF_MOD("scif2", R9A07G044_CLK_SCIF2,
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R9A07G044_CLK_P0,
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0x584, BIT(2), BIT(2)),
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DEF_MOD("scif3", R9A07G044_CLK_SCIF3,
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R9A07G044_CLK_P0,
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0x584, BIT(3), BIT(3)),
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DEF_MOD("scif4", R9A07G044_CLK_SCIF4,
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R9A07G044_CLK_P0,
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0x584, BIT(4), BIT(4)),
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DEF_MOD("sci0", R9A07G044_CLK_SCI0,
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R9A07G044_CLK_P0,
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0x588, BIT(0), BIT(0)),
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DEF_MOD("gic", R9A07G044_GIC600_GICCLK, R9A07G044_CLK_P1,
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0x514, 0),
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DEF_MOD("ia55_pclk", R9A07G044_IA55_PCLK, R9A07G044_CLK_P2,
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0x518, 0),
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DEF_MOD("ia55_clk", R9A07G044_IA55_CLK, R9A07G044_CLK_P1,
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0x518, 1),
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DEF_MOD("scif0", R9A07G044_SCIF0_CLK_PCK, R9A07G044_CLK_P0,
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0x584, 0),
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DEF_MOD("scif1", R9A07G044_SCIF1_CLK_PCK, R9A07G044_CLK_P0,
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0x584, 1),
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DEF_MOD("scif2", R9A07G044_SCIF2_CLK_PCK, R9A07G044_CLK_P0,
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0x584, 2),
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DEF_MOD("scif3", R9A07G044_SCIF3_CLK_PCK, R9A07G044_CLK_P0,
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0x584, 3),
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DEF_MOD("scif4", R9A07G044_SCIF4_CLK_PCK, R9A07G044_CLK_P0,
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0x584, 4),
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DEF_MOD("sci0", R9A07G044_SCI0_CLKP, R9A07G044_CLK_P0,
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0x588, 0),
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};
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static struct rzg2l_reset r9a07g044_resets[] = {
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DEF_RST(R9A07G044_GIC600_GICRESET_N, 0x814, 0),
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DEF_RST(R9A07G044_GIC600_DBG_GICRESET_N, 0x814, 1),
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DEF_RST(R9A07G044_IA55_RESETN, 0x818, 0),
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DEF_RST(R9A07G044_SCIF0_RST_SYSTEM_N, 0x884, 0),
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DEF_RST(R9A07G044_SCIF1_RST_SYSTEM_N, 0x884, 1),
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DEF_RST(R9A07G044_SCIF2_RST_SYSTEM_N, 0x884, 2),
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DEF_RST(R9A07G044_SCIF3_RST_SYSTEM_N, 0x884, 3),
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DEF_RST(R9A07G044_SCIF4_RST_SYSTEM_N, 0x884, 4),
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DEF_RST(R9A07G044_SCI0_RST, 0x888, 0),
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};
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static const unsigned int r9a07g044_crit_mod_clks[] __initconst = {
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MOD_CLK_BASE + R9A07G044_CLK_GIC600,
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MOD_CLK_BASE + R9A07G044_GIC600_GICCLK,
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};
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const struct rzg2l_cpg_info r9a07g044_cpg_info = {
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@ -123,5 +134,9 @@ const struct rzg2l_cpg_info r9a07g044_cpg_info = {
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/* Module Clocks */
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.mod_clks = r9a07g044_mod_clks,
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.num_mod_clks = ARRAY_SIZE(r9a07g044_mod_clks),
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.num_hw_mod_clks = R9A07G044_CLK_MIPI_DSI_PIN + 1,
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.num_hw_mod_clks = R9A07G044_TSU_PCLK + 1,
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/* Resets */
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.resets = r9a07g044_resets,
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.num_resets = ARRAY_SIZE(r9a07g044_resets),
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};
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@ -47,9 +47,9 @@
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#define SDIV(val) DIV_RSMASK(val, 0, 0x7)
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#define CLK_ON_R(reg) (reg)
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#define CLK_MON_R(reg) (0x680 - 0x500 + (reg))
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#define CLK_RST_R(reg) (0x800 - 0x500 + (reg))
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#define CLK_MRST_R(reg) (0x980 - 0x500 + (reg))
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#define CLK_MON_R(reg) (0x180 + (reg))
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#define CLK_RST_R(reg) (reg)
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#define CLK_MRST_R(reg) (0x180 + (reg))
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#define GET_REG_OFFSET(val) ((val >> 20) & 0xfff)
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#define GET_REG_SAMPLL_CLK1(val) ((val >> 22) & 0xfff)
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@ -78,6 +78,7 @@ struct rzg2l_cpg_priv {
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struct clk **clks;
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unsigned int num_core_clks;
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unsigned int num_mod_clks;
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unsigned int num_resets;
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unsigned int last_dt_core_clk;
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struct raw_notifier_head notifiers;
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@ -315,15 +316,13 @@ fail:
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*
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* @hw: handle between common and hardware-specific interfaces
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* @off: register offset
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* @onoff: ON/MON bits
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* @reset: reset bits
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* @bit: ON/MON bit
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* @priv: CPG/MSTP private data
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*/
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struct mstp_clock {
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struct clk_hw hw;
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u16 off;
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u8 onoff;
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u8 reset;
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u8 bit;
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struct rzg2l_cpg_priv *priv;
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};
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@ -337,6 +336,7 @@ static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable)
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struct device *dev = priv->dev;
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unsigned long flags;
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unsigned int i;
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u32 bitmask = BIT(clock->bit);
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u32 value;
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if (!clock->off) {
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@ -349,9 +349,9 @@ static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable)
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spin_lock_irqsave(&priv->rmw_lock, flags);
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if (enable)
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value = (clock->onoff << 16) | clock->onoff;
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value = (bitmask << 16) | bitmask;
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else
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value = clock->onoff << 16;
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value = bitmask << 16;
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writel(value, priv->base + CLK_ON_R(reg));
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spin_unlock_irqrestore(&priv->rmw_lock, flags);
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@ -360,7 +360,7 @@ static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable)
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return 0;
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for (i = 1000; i > 0; --i) {
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if (((readl(priv->base + CLK_MON_R(reg))) & clock->onoff))
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if (((readl(priv->base + CLK_MON_R(reg))) & bitmask))
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break;
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cpu_relax();
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}
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@ -388,6 +388,7 @@ static int rzg2l_mod_clock_is_enabled(struct clk_hw *hw)
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{
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struct mstp_clock *clock = to_mod_clock(hw);
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struct rzg2l_cpg_priv *priv = clock->priv;
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u32 bitmask = BIT(clock->bit);
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u32 value;
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if (!clock->off) {
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|
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@ -397,7 +398,7 @@ static int rzg2l_mod_clock_is_enabled(struct clk_hw *hw)
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value = readl(priv->base + CLK_MON_R(clock->off));
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return !(value & clock->onoff);
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return !(value & bitmask);
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}
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static const struct clk_ops rzg2l_mod_clock_ops = {
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|
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@ -457,8 +458,7 @@ rzg2l_cpg_register_mod_clk(const struct rzg2l_mod_clk *mod,
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init.num_parents = 1;
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clock->off = mod->off;
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clock->onoff = mod->onoff;
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clock->reset = mod->reset;
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clock->bit = mod->bit;
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clock->priv = priv;
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clock->hw.init = &init;
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|
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|
|
@ -483,12 +483,11 @@ static int rzg2l_cpg_reset(struct reset_controller_dev *rcdev,
|
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{
|
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struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);
|
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const struct rzg2l_cpg_info *info = priv->info;
|
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unsigned int reg = info->mod_clks[id].off;
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u32 dis = info->mod_clks[id].reset;
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unsigned int reg = info->resets[id].off;
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u32 dis = BIT(info->resets[id].bit);
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u32 we = dis << 16;
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|
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dev_dbg(rcdev->dev, "reset name:%s id:%ld offset:0x%x\n",
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info->mod_clks[id].name, id, CLK_RST_R(reg));
|
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dev_dbg(rcdev->dev, "reset id:%ld offset:0x%x\n", id, CLK_RST_R(reg));
|
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|
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/* Reset module */
|
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writel(we, priv->base + CLK_RST_R(reg));
|
||||
|
|
@ -507,11 +506,10 @@ static int rzg2l_cpg_assert(struct reset_controller_dev *rcdev,
|
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{
|
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struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);
|
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const struct rzg2l_cpg_info *info = priv->info;
|
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unsigned int reg = info->mod_clks[id].off;
|
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u32 value = info->mod_clks[id].reset << 16;
|
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unsigned int reg = info->resets[id].off;
|
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u32 value = BIT(info->resets[id].bit) << 16;
|
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|
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dev_dbg(rcdev->dev, "assert name:%s id:%ld offset:0x%x\n",
|
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info->mod_clks[id].name, id, CLK_RST_R(reg));
|
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dev_dbg(rcdev->dev, "assert id:%ld offset:0x%x\n", id, CLK_RST_R(reg));
|
||||
|
||||
writel(value, priv->base + CLK_RST_R(reg));
|
||||
return 0;
|
||||
|
|
@ -522,12 +520,12 @@ static int rzg2l_cpg_deassert(struct reset_controller_dev *rcdev,
|
|||
{
|
||||
struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);
|
||||
const struct rzg2l_cpg_info *info = priv->info;
|
||||
unsigned int reg = info->mod_clks[id].off;
|
||||
u32 dis = info->mod_clks[id].reset;
|
||||
unsigned int reg = info->resets[id].off;
|
||||
u32 dis = BIT(info->resets[id].bit);
|
||||
u32 value = (dis << 16) | dis;
|
||||
|
||||
dev_dbg(rcdev->dev, "deassert name:%s id:%ld offset:0x%x\n",
|
||||
info->mod_clks[id].name, id, CLK_RST_R(reg));
|
||||
dev_dbg(rcdev->dev, "deassert id:%ld offset:0x%x\n", id,
|
||||
CLK_RST_R(reg));
|
||||
|
||||
writel(value, priv->base + CLK_RST_R(reg));
|
||||
return 0;
|
||||
|
|
@ -538,8 +536,8 @@ static int rzg2l_cpg_status(struct reset_controller_dev *rcdev,
|
|||
{
|
||||
struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);
|
||||
const struct rzg2l_cpg_info *info = priv->info;
|
||||
unsigned int reg = info->mod_clks[id].off;
|
||||
u32 bitmask = info->mod_clks[id].reset;
|
||||
unsigned int reg = info->resets[id].off;
|
||||
u32 bitmask = BIT(info->resets[id].bit);
|
||||
|
||||
return !(readl(priv->base + CLK_MRST_R(reg)) & bitmask);
|
||||
}
|
||||
|
|
@ -554,9 +552,11 @@ static const struct reset_control_ops rzg2l_cpg_reset_ops = {
|
|||
static int rzg2l_cpg_reset_xlate(struct reset_controller_dev *rcdev,
|
||||
const struct of_phandle_args *reset_spec)
|
||||
{
|
||||
struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);
|
||||
const struct rzg2l_cpg_info *info = priv->info;
|
||||
unsigned int id = reset_spec->args[0];
|
||||
|
||||
if (id >= rcdev->nr_resets) {
|
||||
if (id >= rcdev->nr_resets || !info->resets[id].off) {
|
||||
dev_err(rcdev->dev, "Invalid reset index %u\n", id);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
|
@ -571,7 +571,7 @@ static int rzg2l_cpg_reset_controller_register(struct rzg2l_cpg_priv *priv)
|
|||
priv->rcdev.dev = priv->dev;
|
||||
priv->rcdev.of_reset_n_cells = 1;
|
||||
priv->rcdev.of_xlate = rzg2l_cpg_reset_xlate;
|
||||
priv->rcdev.nr_resets = priv->num_mod_clks;
|
||||
priv->rcdev.nr_resets = priv->num_resets;
|
||||
|
||||
return devm_reset_controller_register(priv->dev, &priv->rcdev);
|
||||
}
|
||||
|
|
@ -594,42 +594,49 @@ static int rzg2l_cpg_attach_dev(struct generic_pm_domain *unused, struct device
|
|||
{
|
||||
struct device_node *np = dev->of_node;
|
||||
struct of_phandle_args clkspec;
|
||||
bool once = true;
|
||||
struct clk *clk;
|
||||
int error;
|
||||
int i = 0;
|
||||
|
||||
while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
|
||||
&clkspec)) {
|
||||
if (rzg2l_cpg_is_pm_clk(&clkspec))
|
||||
goto found;
|
||||
if (rzg2l_cpg_is_pm_clk(&clkspec)) {
|
||||
if (once) {
|
||||
once = false;
|
||||
error = pm_clk_create(dev);
|
||||
if (error) {
|
||||
of_node_put(clkspec.np);
|
||||
goto err;
|
||||
}
|
||||
}
|
||||
clk = of_clk_get_from_provider(&clkspec);
|
||||
of_node_put(clkspec.np);
|
||||
if (IS_ERR(clk)) {
|
||||
error = PTR_ERR(clk);
|
||||
goto fail_destroy;
|
||||
}
|
||||
|
||||
of_node_put(clkspec.np);
|
||||
error = pm_clk_add_clk(dev, clk);
|
||||
if (error) {
|
||||
dev_err(dev, "pm_clk_add_clk failed %d\n",
|
||||
error);
|
||||
goto fail_put;
|
||||
}
|
||||
} else {
|
||||
of_node_put(clkspec.np);
|
||||
}
|
||||
i++;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
found:
|
||||
clk = of_clk_get_from_provider(&clkspec);
|
||||
of_node_put(clkspec.np);
|
||||
|
||||
if (IS_ERR(clk))
|
||||
return PTR_ERR(clk);
|
||||
|
||||
error = pm_clk_create(dev);
|
||||
if (error)
|
||||
goto fail_put;
|
||||
|
||||
error = pm_clk_add_clk(dev, clk);
|
||||
if (error)
|
||||
goto fail_destroy;
|
||||
|
||||
return 0;
|
||||
fail_put:
|
||||
clk_put(clk);
|
||||
|
||||
fail_destroy:
|
||||
pm_clk_destroy(dev);
|
||||
fail_put:
|
||||
clk_put(clk);
|
||||
err:
|
||||
return error;
|
||||
}
|
||||
|
||||
|
|
@ -692,6 +699,7 @@ static int __init rzg2l_cpg_probe(struct platform_device *pdev)
|
|||
priv->clks = clks;
|
||||
priv->num_core_clks = info->num_total_core_clks;
|
||||
priv->num_mod_clks = info->num_hw_mod_clks;
|
||||
priv->num_resets = info->num_resets;
|
||||
priv->last_dt_core_clk = info->last_dt_core_clk;
|
||||
|
||||
for (i = 0; i < nclks; i++)
|
||||
|
|
|
|||
|
|
@ -21,6 +21,7 @@
|
|||
#define DDIV_PACK(offset, bitpos, size) \
|
||||
(((offset) << 20) | ((bitpos) << 12) | ((size) << 8))
|
||||
#define DIVPL2A DDIV_PACK(CPG_PL2_DDIV, 0, 3)
|
||||
#define DIVPL3A DDIV_PACK(CPG_PL3A_DDIV, 0, 3)
|
||||
#define DIVPL3B DDIV_PACK(CPG_PL3A_DDIV, 4, 3)
|
||||
|
||||
/**
|
||||
|
|
@ -76,26 +77,40 @@ enum clk_types {
|
|||
* @id: clock index in array containing all Core and Module Clocks
|
||||
* @parent: id of parent clock
|
||||
* @off: register offset
|
||||
* @onoff: ON/MON bits
|
||||
* @reset: reset bits
|
||||
* @bit: ON/MON bit
|
||||
*/
|
||||
struct rzg2l_mod_clk {
|
||||
const char *name;
|
||||
unsigned int id;
|
||||
unsigned int parent;
|
||||
u16 off;
|
||||
u8 onoff;
|
||||
u8 reset;
|
||||
u8 bit;
|
||||
};
|
||||
|
||||
#define DEF_MOD(_name, _id, _parent, _off, _onoff, _reset) \
|
||||
[_id] = { \
|
||||
#define DEF_MOD(_name, _id, _parent, _off, _bit) \
|
||||
{ \
|
||||
.name = _name, \
|
||||
.id = MOD_CLK_BASE + _id, \
|
||||
.id = MOD_CLK_BASE + (_id), \
|
||||
.parent = (_parent), \
|
||||
.off = (_off), \
|
||||
.onoff = (_onoff), \
|
||||
.reset = (_reset) \
|
||||
.bit = (_bit), \
|
||||
}
|
||||
|
||||
/**
|
||||
* struct rzg2l_reset - Reset definitions
|
||||
*
|
||||
* @off: register offset
|
||||
* @bit: reset bit
|
||||
*/
|
||||
struct rzg2l_reset {
|
||||
u16 off;
|
||||
u8 bit;
|
||||
};
|
||||
|
||||
#define DEF_RST(_id, _off, _bit) \
|
||||
[_id] = { \
|
||||
.off = (_off), \
|
||||
.bit = (_bit) \
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -126,6 +141,10 @@ struct rzg2l_cpg_info {
|
|||
unsigned int num_mod_clks;
|
||||
unsigned int num_hw_mod_clks;
|
||||
|
||||
/* Resets */
|
||||
const struct rzg2l_reset *resets;
|
||||
unsigned int num_resets;
|
||||
|
||||
/* Critical Module Clocks that should not be disabled */
|
||||
const unsigned int *crit_mod_clks;
|
||||
unsigned int num_crit_mod_clks;
|
||||
|
|
|
|||
|
|
@ -32,58 +32,188 @@
|
|||
#define R9A07G044_OSCCLK 21
|
||||
|
||||
/* R9A07G044 Module Clocks */
|
||||
#define R9A07G044_CLK_GIC600 0
|
||||
#define R9A07G044_CLK_IA55 1
|
||||
#define R9A07G044_CLK_SYC 2
|
||||
#define R9A07G044_CLK_DMAC 3
|
||||
#define R9A07G044_CLK_SYSC 4
|
||||
#define R9A07G044_CLK_MTU 5
|
||||
#define R9A07G044_CLK_GPT 6
|
||||
#define R9A07G044_CLK_ETH0 7
|
||||
#define R9A07G044_CLK_ETH1 8
|
||||
#define R9A07G044_CLK_I2C0 9
|
||||
#define R9A07G044_CLK_I2C1 10
|
||||
#define R9A07G044_CLK_I2C2 11
|
||||
#define R9A07G044_CLK_I2C3 12
|
||||
#define R9A07G044_CLK_SCIF0 13
|
||||
#define R9A07G044_CLK_SCIF1 14
|
||||
#define R9A07G044_CLK_SCIF2 15
|
||||
#define R9A07G044_CLK_SCIF3 16
|
||||
#define R9A07G044_CLK_SCIF4 17
|
||||
#define R9A07G044_CLK_SCI0 18
|
||||
#define R9A07G044_CLK_SCI1 19
|
||||
#define R9A07G044_CLK_GPIO 20
|
||||
#define R9A07G044_CLK_SDHI0 21
|
||||
#define R9A07G044_CLK_SDHI1 22
|
||||
#define R9A07G044_CLK_USB0 23
|
||||
#define R9A07G044_CLK_USB1 24
|
||||
#define R9A07G044_CLK_CANFD 25
|
||||
#define R9A07G044_CLK_SSI0 26
|
||||
#define R9A07G044_CLK_SSI1 27
|
||||
#define R9A07G044_CLK_SSI2 28
|
||||
#define R9A07G044_CLK_SSI3 29
|
||||
#define R9A07G044_CLK_MHU 30
|
||||
#define R9A07G044_CLK_OSTM0 31
|
||||
#define R9A07G044_CLK_OSTM1 32
|
||||
#define R9A07G044_CLK_OSTM2 33
|
||||
#define R9A07G044_CLK_WDT0 34
|
||||
#define R9A07G044_CLK_WDT1 35
|
||||
#define R9A07G044_CLK_WDT2 36
|
||||
#define R9A07G044_CLK_WDT_PON 37
|
||||
#define R9A07G044_CLK_GPU 38
|
||||
#define R9A07G044_CLK_ISU 39
|
||||
#define R9A07G044_CLK_H264 40
|
||||
#define R9A07G044_CLK_CRU 41
|
||||
#define R9A07G044_CLK_MIPI_DSI 42
|
||||
#define R9A07G044_CLK_LCDC 43
|
||||
#define R9A07G044_CLK_SRC 44
|
||||
#define R9A07G044_CLK_RSPI0 45
|
||||
#define R9A07G044_CLK_RSPI1 46
|
||||
#define R9A07G044_CLK_RSPI2 47
|
||||
#define R9A07G044_CLK_ADC 48
|
||||
#define R9A07G044_CLK_TSU_PCLK 49
|
||||
#define R9A07G044_CLK_SPI 50
|
||||
#define R9A07G044_CLK_MIPI_DSI_V 51
|
||||
#define R9A07G044_CLK_MIPI_DSI_PIN 52
|
||||
#define R9A07G044_CA55_SCLK 0
|
||||
#define R9A07G044_CA55_PCLK 1
|
||||
#define R9A07G044_CA55_ATCLK 2
|
||||
#define R9A07G044_CA55_GICCLK 3
|
||||
#define R9A07G044_CA55_PERICLK 4
|
||||
#define R9A07G044_CA55_ACLK 5
|
||||
#define R9A07G044_CA55_TSCLK 6
|
||||
#define R9A07G044_GIC600_GICCLK 7
|
||||
#define R9A07G044_IA55_CLK 8
|
||||
#define R9A07G044_IA55_PCLK 9
|
||||
#define R9A07G044_MHU_PCLK 10
|
||||
#define R9A07G044_SYC_CNT_CLK 11
|
||||
#define R9A07G044_DMAC_ACLK 12
|
||||
#define R9A07G044_DMAC_PCLK 13
|
||||
#define R9A07G044_OSTM0_PCLK 14
|
||||
#define R9A07G044_OSTM1_PCLK 15
|
||||
#define R9A07G044_OSTM2_PCLK 16
|
||||
#define R9A07G044_MTU_X_MCK_MTU3 17
|
||||
#define R9A07G044_POE3_CLKM_POE 18
|
||||
#define R9A07G044_GPT_PCLK 19
|
||||
#define R9A07G044_POEG_A_CLKP 20
|
||||
#define R9A07G044_POEG_B_CLKP 21
|
||||
#define R9A07G044_POEG_C_CLKP 22
|
||||
#define R9A07G044_POEG_D_CLKP 23
|
||||
#define R9A07G044_WDT0_PCLK 24
|
||||
#define R9A07G044_WDT0_CLK 25
|
||||
#define R9A07G044_WDT1_PCLK 26
|
||||
#define R9A07G044_WDT1_CLK 27
|
||||
#define R9A07G044_WDT2_PCLK 28
|
||||
#define R9A07G044_WDT2_CLK 29
|
||||
#define R9A07G044_SPI_CLK2 30
|
||||
#define R9A07G044_SPI_CLK 31
|
||||
#define R9A07G044_SDHI0_IMCLK 32
|
||||
#define R9A07G044_SDHI0_IMCLK2 33
|
||||
#define R9A07G044_SDHI0_CLK_HS 34
|
||||
#define R9A07G044_SDHI0_ACLK 35
|
||||
#define R9A07G044_SDHI1_IMCLK 36
|
||||
#define R9A07G044_SDHI1_IMCLK2 37
|
||||
#define R9A07G044_SDHI1_CLK_HS 38
|
||||
#define R9A07G044_SDHI1_ACLK 39
|
||||
#define R9A07G044_GPU_CLK 40
|
||||
#define R9A07G044_GPU_AXI_CLK 41
|
||||
#define R9A07G044_GPU_ACE_CLK 42
|
||||
#define R9A07G044_ISU_ACLK 43
|
||||
#define R9A07G044_ISU_PCLK 44
|
||||
#define R9A07G044_H264_CLK_A 45
|
||||
#define R9A07G044_H264_CLK_P 46
|
||||
#define R9A07G044_CRU_SYSCLK 47
|
||||
#define R9A07G044_CRU_VCLK 48
|
||||
#define R9A07G044_CRU_PCLK 49
|
||||
#define R9A07G044_CRU_ACLK 50
|
||||
#define R9A07G044_MIPI_DSI_PLLCLK 51
|
||||
#define R9A07G044_MIPI_DSI_SYSCLK 52
|
||||
#define R9A07G044_MIPI_DSI_ACLK 53
|
||||
#define R9A07G044_MIPI_DSI_PCLK 54
|
||||
#define R9A07G044_MIPI_DSI_VCLK 55
|
||||
#define R9A07G044_MIPI_DSI_LPCLK 56
|
||||
#define R9A07G044_LCDC_CLK_A 57
|
||||
#define R9A07G044_LCDC_CLK_P 58
|
||||
#define R9A07G044_LCDC_CLK_D 59
|
||||
#define R9A07G044_SSI0_PCLK2 60
|
||||
#define R9A07G044_SSI0_PCLK_SFR 61
|
||||
#define R9A07G044_SSI1_PCLK2 62
|
||||
#define R9A07G044_SSI1_PCLK_SFR 63
|
||||
#define R9A07G044_SSI2_PCLK2 64
|
||||
#define R9A07G044_SSI2_PCLK_SFR 65
|
||||
#define R9A07G044_SSI3_PCLK2 66
|
||||
#define R9A07G044_SSI3_PCLK_SFR 67
|
||||
#define R9A07G044_SRC_CLKP 68
|
||||
#define R9A07G044_USB_U2H0_HCLK 69
|
||||
#define R9A07G044_USB_U2H1_HCLK 70
|
||||
#define R9A07G044_USB_U2P_EXR_CPUCLK 71
|
||||
#define R9A07G044_USB_PCLK 72
|
||||
#define R9A07G044_ETH0_CLK_AXI 73
|
||||
#define R9A07G044_ETH0_CLK_CHI 74
|
||||
#define R9A07G044_ETH1_CLK_AXI 75
|
||||
#define R9A07G044_ETH1_CLK_CHI 76
|
||||
#define R9A07G044_I2C0_PCLK 77
|
||||
#define R9A07G044_I2C1_PCLK 78
|
||||
#define R9A07G044_I2C2_PCLK 79
|
||||
#define R9A07G044_I2C3_PCLK 80
|
||||
#define R9A07G044_SCIF0_CLK_PCK 81
|
||||
#define R9A07G044_SCIF1_CLK_PCK 82
|
||||
#define R9A07G044_SCIF2_CLK_PCK 83
|
||||
#define R9A07G044_SCIF3_CLK_PCK 84
|
||||
#define R9A07G044_SCIF4_CLK_PCK 85
|
||||
#define R9A07G044_SCI0_CLKP 86
|
||||
#define R9A07G044_SCI1_CLKP 87
|
||||
#define R9A07G044_IRDA_CLKP 88
|
||||
#define R9A07G044_RSPI0_CLKB 89
|
||||
#define R9A07G044_RSPI1_CLKB 90
|
||||
#define R9A07G044_RSPI2_CLKB 91
|
||||
#define R9A07G044_CANFD_PCLK 92
|
||||
#define R9A07G044_GPIO_HCLK 93
|
||||
#define R9A07G044_ADC_ADCLK 94
|
||||
#define R9A07G044_ADC_PCLK 95
|
||||
#define R9A07G044_TSU_PCLK 96
|
||||
|
||||
/* R9A07G044 Resets */
|
||||
#define R9A07G044_CA55_RST_1_0 0
|
||||
#define R9A07G044_CA55_RST_1_1 1
|
||||
#define R9A07G044_CA55_RST_3_0 2
|
||||
#define R9A07G044_CA55_RST_3_1 3
|
||||
#define R9A07G044_CA55_RST_4 4
|
||||
#define R9A07G044_CA55_RST_5 5
|
||||
#define R9A07G044_CA55_RST_6 6
|
||||
#define R9A07G044_CA55_RST_7 7
|
||||
#define R9A07G044_CA55_RST_8 8
|
||||
#define R9A07G044_CA55_RST_9 9
|
||||
#define R9A07G044_CA55_RST_10 10
|
||||
#define R9A07G044_CA55_RST_11 11
|
||||
#define R9A07G044_CA55_RST_12 12
|
||||
#define R9A07G044_GIC600_GICRESET_N 13
|
||||
#define R9A07G044_GIC600_DBG_GICRESET_N 14
|
||||
#define R9A07G044_IA55_RESETN 15
|
||||
#define R9A07G044_MHU_RESETN 16
|
||||
#define R9A07G044_DMAC_ARESETN 17
|
||||
#define R9A07G044_DMAC_RST_ASYNC 18
|
||||
#define R9A07G044_SYC_RESETN 19
|
||||
#define R9A07G044_OSTM0_PRESETZ 20
|
||||
#define R9A07G044_OSTM1_PRESETZ 21
|
||||
#define R9A07G044_OSTM2_PRESETZ 22
|
||||
#define R9A07G044_MTU_X_PRESET_MTU3 23
|
||||
#define R9A07G044_POE3_RST_M_REG 24
|
||||
#define R9A07G044_GPT_RST_C 25
|
||||
#define R9A07G044_POEG_A_RST 26
|
||||
#define R9A07G044_POEG_B_RST 27
|
||||
#define R9A07G044_POEG_C_RST 28
|
||||
#define R9A07G044_POEG_D_RST 29
|
||||
#define R9A07G044_WDT0_PRESETN 30
|
||||
#define R9A07G044_WDT1_PRESETN 31
|
||||
#define R9A07G044_WDT2_PRESETN 32
|
||||
#define R9A07G044_SPI_RST 33
|
||||
#define R9A07G044_SDHI0_IXRST 34
|
||||
#define R9A07G044_SDHI1_IXRST 35
|
||||
#define R9A07G044_GPU_RESETN 36
|
||||
#define R9A07G044_GPU_AXI_RESETN 37
|
||||
#define R9A07G044_GPU_ACE_RESETN 38
|
||||
#define R9A07G044_ISU_ARESETN 39
|
||||
#define R9A07G044_ISU_PRESETN 40
|
||||
#define R9A07G044_H264_X_RESET_VCP 41
|
||||
#define R9A07G044_H264_CP_PRESET_P 42
|
||||
#define R9A07G044_CRU_CMN_RSTB 43
|
||||
#define R9A07G044_CRU_PRESETN 44
|
||||
#define R9A07G044_CRU_ARESETN 45
|
||||
#define R9A07G044_MIPI_DSI_CMN_RSTB 46
|
||||
#define R9A07G044_MIPI_DSI_ARESET_N 47
|
||||
#define R9A07G044_MIPI_DSI_PRESET_N 48
|
||||
#define R9A07G044_LCDC_RESET_N 49
|
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#define R9A07G044_SSI0_RST_M2_REG 50
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#define R9A07G044_SSI1_RST_M2_REG 51
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#define R9A07G044_SSI2_RST_M2_REG 52
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#define R9A07G044_SSI3_RST_M2_REG 53
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#define R9A07G044_SRC_RST 54
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#define R9A07G044_USB_U2H0_HRESETN 55
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#define R9A07G044_USB_U2H1_HRESETN 56
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#define R9A07G044_USB_U2P_EXL_SYSRST 57
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#define R9A07G044_USB_PRESETN 58
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#define R9A07G044_ETH0_RST_HW_N 59
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#define R9A07G044_ETH1_RST_HW_N 60
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#define R9A07G044_I2C0_MRST 61
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#define R9A07G044_I2C1_MRST 62
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#define R9A07G044_I2C2_MRST 63
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#define R9A07G044_I2C3_MRST 64
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#define R9A07G044_SCIF0_RST_SYSTEM_N 65
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#define R9A07G044_SCIF1_RST_SYSTEM_N 66
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#define R9A07G044_SCIF2_RST_SYSTEM_N 67
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#define R9A07G044_SCIF3_RST_SYSTEM_N 68
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#define R9A07G044_SCIF4_RST_SYSTEM_N 69
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#define R9A07G044_SCI0_RST 70
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#define R9A07G044_SCI1_RST 71
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#define R9A07G044_IRDA_RST 72
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#define R9A07G044_RSPI0_RST 73
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#define R9A07G044_RSPI1_RST 74
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#define R9A07G044_RSPI2_RST 75
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#define R9A07G044_CANFD_RSTP_N 76
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#define R9A07G044_CANFD_RSTC_N 77
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#define R9A07G044_GPIO_RSTN 78
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#define R9A07G044_GPIO_PORT_RESETN 79
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#define R9A07G044_GPIO_SPARE_RESETN 80
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#define R9A07G044_ADC_PRESETN 81
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#define R9A07G044_ADC_ADRST_N 82
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#define R9A07G044_TSU_PRESETN 83
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#endif /* __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__ */
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