igb: Create separate functions for generating cmd_type and olinfo
This change is meant to improve the readability of the driver by separating out the cmd_type configuration and the olinfo configuration into their own functions. By doing this it is much easier to determine which ingredients go into setting up these to portions of the descriptor. Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Tested-by: Aaron Brown <aaron.f.brown@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
This commit is contained in:
Alexander Duyck
Jeff Kirsher
Родитель
8542db05db
Коммит
e032afc80c
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@ -130,7 +130,9 @@ union e1000_adv_tx_desc {
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#define E1000_ADVTXD_MAC_TSTAMP 0x00080000 /* IEEE1588 Timestamp packet */
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#define E1000_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Descriptor */
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#define E1000_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */
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#define E1000_ADVTXD_DCMD_EOP 0x01000000 /* End of Packet */
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#define E1000_ADVTXD_DCMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
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#define E1000_ADVTXD_DCMD_RS 0x08000000 /* Report Status */
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#define E1000_ADVTXD_DCMD_DEXT 0x20000000 /* Descriptor extension (1=Adv) */
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#define E1000_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */
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#define E1000_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */
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@ -231,7 +231,7 @@ struct igb_ring {
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#define IGB_RING_FLAG_TX_CTX_IDX 0x00000001 /* HW requires context index */
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#define IGB_ADVTXD_DCMD (E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS)
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#define IGB_TXD_DCMD (E1000_ADVTXD_DCMD_EOP | E1000_ADVTXD_DCMD_RS)
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#define IGB_RX_DESC(R, i) \
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(&(((union e1000_adv_rx_desc *)((R)->desc))[i]))
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@ -4103,6 +4103,50 @@ static inline bool igb_tx_csum(struct igb_ring *tx_ring,
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return (skb->ip_summed == CHECKSUM_PARTIAL);
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}
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static __le32 igb_tx_cmd_type(u32 tx_flags)
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{
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/* set type for advanced descriptor with frame checksum insertion */
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__le32 cmd_type = cpu_to_le32(E1000_ADVTXD_DTYP_DATA |
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E1000_ADVTXD_DCMD_IFCS |
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E1000_ADVTXD_DCMD_DEXT);
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/* set HW vlan bit if vlan is present */
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if (tx_flags & IGB_TX_FLAGS_VLAN)
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cmd_type |= cpu_to_le32(E1000_ADVTXD_DCMD_VLE);
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/* set timestamp bit if present */
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if (tx_flags & IGB_TX_FLAGS_TSTAMP)
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cmd_type |= cpu_to_le32(E1000_ADVTXD_MAC_TSTAMP);
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/* set segmentation bits for TSO */
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if (tx_flags & IGB_TX_FLAGS_TSO)
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cmd_type |= cpu_to_le32(E1000_ADVTXD_DCMD_TSE);
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return cmd_type;
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}
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static __le32 igb_tx_olinfo_status(u32 tx_flags, unsigned int paylen,
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struct igb_ring *tx_ring)
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{
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u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
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/* 82575 requires a unique index per ring if any offload is enabled */
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if ((tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_VLAN)) &&
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(tx_ring->flags & IGB_RING_FLAG_TX_CTX_IDX))
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olinfo_status |= tx_ring->reg_idx << 4;
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/* insert L4 checksum */
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if (tx_flags & IGB_TX_FLAGS_CSUM) {
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olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
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/* insert IPv4 checksum */
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if (tx_flags & IGB_TX_FLAGS_IPV4)
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olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
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}
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return cpu_to_le32(olinfo_status);
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}
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#define IGB_MAX_TXD_PWR 16
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#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
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@ -4187,54 +4231,28 @@ static inline void igb_tx_queue(struct igb_ring *tx_ring,
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{
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union e1000_adv_tx_desc *tx_desc;
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struct igb_tx_buffer *buffer_info;
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u32 olinfo_status = 0, cmd_type_len;
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__le32 olinfo_status, cmd_type;
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unsigned int i = tx_ring->next_to_use;
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cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
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E1000_ADVTXD_DCMD_DEXT);
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if (tx_flags & IGB_TX_FLAGS_VLAN)
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cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
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if (tx_flags & IGB_TX_FLAGS_TSTAMP)
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cmd_type_len |= E1000_ADVTXD_MAC_TSTAMP;
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if (tx_flags & IGB_TX_FLAGS_TSO) {
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cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
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/* insert tcp checksum */
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olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
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/* insert ip checksum */
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if (tx_flags & IGB_TX_FLAGS_IPV4)
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olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
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} else if (tx_flags & IGB_TX_FLAGS_CSUM) {
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olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
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}
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if ((tx_ring->flags & IGB_RING_FLAG_TX_CTX_IDX) &&
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(tx_flags & (IGB_TX_FLAGS_CSUM |
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IGB_TX_FLAGS_TSO |
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IGB_TX_FLAGS_VLAN)))
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olinfo_status |= tx_ring->reg_idx << 4;
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olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
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cmd_type = igb_tx_cmd_type(tx_flags);
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olinfo_status = igb_tx_olinfo_status(tx_flags,
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paylen - hdr_len,
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tx_ring);
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do {
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buffer_info = &tx_ring->tx_buffer_info[i];
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tx_desc = IGB_TX_DESC(tx_ring, i);
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tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
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tx_desc->read.cmd_type_len =
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cpu_to_le32(cmd_type_len | buffer_info->length);
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tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
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tx_desc->read.cmd_type_len = cmd_type |
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cpu_to_le32(buffer_info->length);
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tx_desc->read.olinfo_status = olinfo_status;
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count--;
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i++;
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if (i == tx_ring->count)
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i = 0;
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} while (count > 0);
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tx_desc->read.cmd_type_len |= cpu_to_le32(IGB_ADVTXD_DCMD);
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tx_desc->read.cmd_type_len |= cpu_to_le32(IGB_TXD_DCMD);
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/* Force memory writes to complete before letting h/w
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* know there are new descriptors to fetch. (Only
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* applicable for weak-ordered memory model archs,
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@ -4309,21 +4327,22 @@ netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
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tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
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}
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if (skb->protocol == htons(ETH_P_IP))
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tx_flags |= IGB_TX_FLAGS_IPV4;
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/* record the location of the first descriptor for this packet */
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first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
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tso = igb_tso(tx_ring, skb, tx_flags, &hdr_len);
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if (tso < 0)
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if (tso < 0) {
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goto out_drop;
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else if (tso)
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tx_flags |= IGB_TX_FLAGS_TSO;
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else if (igb_tx_csum(tx_ring, skb, tx_flags) &&
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(skb->ip_summed == CHECKSUM_PARTIAL))
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} else if (tso) {
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tx_flags |= IGB_TX_FLAGS_TSO | IGB_TX_FLAGS_CSUM;
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if (skb->protocol == htons(ETH_P_IP))
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tx_flags |= IGB_TX_FLAGS_IPV4;
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} else if (igb_tx_csum(tx_ring, skb, tx_flags) &&
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(skb->ip_summed == CHECKSUM_PARTIAL)) {
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tx_flags |= IGB_TX_FLAGS_CSUM;
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}
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/*
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* count reflects descriptors mapped, if 0 or less then mapping error
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