mfd: rtsx: Support RTS5227
Support new model RTS5227. Signed-off-by: Roger Tseng <rogerable@realtek.com> Reviewed-by: Wei WANG <wei_wang@realsil.com.cn> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
This commit is contained in:
Roger Tseng
Samuel Ortiz
Родитель
88a7ee37f3
Коммит
e12379320b
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@ -9,7 +9,7 @@ obj-$(CONFIG_MFD_88PM805) += 88pm805.o 88pm80x.o
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obj-$(CONFIG_MFD_SM501) += sm501.o
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obj-$(CONFIG_MFD_ASIC3) += asic3.o tmio_core.o
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rtsx_pci-objs := rtsx_pcr.o rts5209.o rts5229.o rtl8411.o
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rtsx_pci-objs := rtsx_pcr.o rts5209.o rts5229.o rtl8411.o rts5227.o
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obj-$(CONFIG_MFD_RTSX_PCI) += rtsx_pci.o
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obj-$(CONFIG_HTC_EGPIO) += htc-egpio.o
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@ -0,0 +1,234 @@
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/* Driver for Realtek PCI-Express card reader
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*
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* Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2, or (at your option) any
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* later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*
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* Author:
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* Wei WANG <wei_wang@realsil.com.cn>
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* No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
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*
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* Roger Tseng <rogerable@realtek.com>
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* No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
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*/
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/mfd/rtsx_pci.h>
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#include "rtsx_pcr.h"
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static int rts5227_extra_init_hw(struct rtsx_pcr *pcr)
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{
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u16 cap;
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rtsx_pci_init_cmd(pcr);
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/* Configure GPIO as output */
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);
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/* Switch LDO3318 source from DV33 to card_3v3 */
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01);
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/* LED shine disabled, set initial shine cycle period */
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02);
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/* Configure LTR */
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pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &cap);
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if (cap & PCI_EXP_LTR_EN)
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LTR_CTL, 0xFF, 0xA3);
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/* Configure OBFF */
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OBFF_CFG, 0x03, 0x03);
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/* Configure force_clock_req
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* Maybe We should define 0xFF03 as some name
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*/
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 0xFF03, 0x08, 0x08);
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/* Correct driving */
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
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SD30_CLK_DRIVE_SEL, 0xFF, 0x96);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
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SD30_CMD_DRIVE_SEL, 0xFF, 0x96);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
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SD30_DAT_DRIVE_SEL, 0xFF, 0x96);
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return rtsx_pci_send_cmd(pcr, 100);
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}
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static int rts5227_optimize_phy(struct rtsx_pcr *pcr)
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{
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/* Optimize RX sensitivity */
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return rtsx_pci_write_phy_register(pcr, 0x00, 0xBA42);
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}
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static int rts5227_turn_on_led(struct rtsx_pcr *pcr)
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{
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return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02);
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}
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static int rts5227_turn_off_led(struct rtsx_pcr *pcr)
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{
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return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);
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}
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static int rts5227_enable_auto_blink(struct rtsx_pcr *pcr)
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{
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return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08);
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}
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static int rts5227_disable_auto_blink(struct rtsx_pcr *pcr)
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{
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return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00);
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}
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static int rts5227_card_power_on(struct rtsx_pcr *pcr, int card)
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{
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int err;
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rtsx_pci_init_cmd(pcr);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
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SD_POWER_MASK, SD_PARTIAL_POWER_ON);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
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LDO3318_PWR_MASK, 0x02);
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err = rtsx_pci_send_cmd(pcr, 100);
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if (err < 0)
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return err;
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/* To avoid too large in-rush current */
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udelay(150);
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rtsx_pci_init_cmd(pcr);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
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SD_POWER_MASK, SD_POWER_ON);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
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LDO3318_PWR_MASK, 0x06);
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err = rtsx_pci_send_cmd(pcr, 100);
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if (err < 0)
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return err;
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return 0;
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}
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static int rts5227_card_power_off(struct rtsx_pcr *pcr, int card)
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{
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rtsx_pci_init_cmd(pcr);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
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SD_POWER_MASK | PMOS_STRG_MASK,
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SD_POWER_OFF | PMOS_STRG_400mA);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
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LDO3318_PWR_MASK, 0X00);
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return rtsx_pci_send_cmd(pcr, 100);
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}
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static int rts5227_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
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{
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int err;
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u8 drive_sel;
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if (voltage == OUTPUT_3V3) {
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err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4FC0 | 0x24);
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if (err < 0)
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return err;
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drive_sel = 0x96;
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} else if (voltage == OUTPUT_1V8) {
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err = rtsx_pci_write_phy_register(pcr, 0x11, 0x3C02);
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if (err < 0)
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return err;
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err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4C80 | 0x24);
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if (err < 0)
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return err;
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drive_sel = 0xB3;
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} else {
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return -EINVAL;
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}
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/* set pad drive */
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rtsx_pci_init_cmd(pcr);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL,
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0xFF, drive_sel);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL,
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0xFF, drive_sel);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL,
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0xFF, drive_sel);
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return rtsx_pci_send_cmd(pcr, 100);
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}
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static const struct pcr_ops rts5227_pcr_ops = {
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.extra_init_hw = rts5227_extra_init_hw,
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.optimize_phy = rts5227_optimize_phy,
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.turn_on_led = rts5227_turn_on_led,
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.turn_off_led = rts5227_turn_off_led,
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.enable_auto_blink = rts5227_enable_auto_blink,
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.disable_auto_blink = rts5227_disable_auto_blink,
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.card_power_on = rts5227_card_power_on,
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.card_power_off = rts5227_card_power_off,
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.switch_output_voltage = rts5227_switch_output_voltage,
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.cd_deglitch = NULL,
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.conv_clk_and_div_n = NULL,
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};
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/* SD Pull Control Enable:
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* SD_DAT[3:0] ==> pull up
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* SD_CD ==> pull up
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* SD_WP ==> pull up
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* SD_CMD ==> pull up
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* SD_CLK ==> pull down
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*/
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static const u32 rts5227_sd_pull_ctl_enable_tbl[] = {
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RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
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RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
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0,
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};
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/* SD Pull Control Disable:
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* SD_DAT[3:0] ==> pull down
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* SD_CD ==> pull up
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* SD_WP ==> pull down
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* SD_CMD ==> pull down
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* SD_CLK ==> pull down
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*/
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static const u32 rts5227_sd_pull_ctl_disable_tbl[] = {
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RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
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RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
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0,
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};
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/* MS Pull Control Enable:
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* MS CD ==> pull up
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* others ==> pull down
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*/
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static const u32 rts5227_ms_pull_ctl_enable_tbl[] = {
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RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
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RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
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0,
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};
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/* MS Pull Control Disable:
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* MS CD ==> pull up
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* others ==> pull down
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*/
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static const u32 rts5227_ms_pull_ctl_disable_tbl[] = {
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RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
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RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
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0,
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};
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void rts5227_init_params(struct rtsx_pcr *pcr)
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{
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pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
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pcr->num_slots = 2;
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pcr->ops = &rts5227_pcr_ops;
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pcr->sd_pull_ctl_enable_tbl = rts5227_sd_pull_ctl_enable_tbl;
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pcr->sd_pull_ctl_disable_tbl = rts5227_sd_pull_ctl_disable_tbl;
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pcr->ms_pull_ctl_enable_tbl = rts5227_ms_pull_ctl_enable_tbl;
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pcr->ms_pull_ctl_disable_tbl = rts5227_ms_pull_ctl_disable_tbl;
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}
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@ -55,6 +55,7 @@ static DEFINE_PCI_DEVICE_TABLE(rtsx_pci_ids) = {
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{ PCI_DEVICE(0x10EC, 0x5209), PCI_CLASS_OTHERS << 16, 0xFF0000 },
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{ PCI_DEVICE(0x10EC, 0x5229), PCI_CLASS_OTHERS << 16, 0xFF0000 },
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{ PCI_DEVICE(0x10EC, 0x5289), PCI_CLASS_OTHERS << 16, 0xFF0000 },
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{ PCI_DEVICE(0x10EC, 0x5227), PCI_CLASS_OTHERS << 16, 0xFF0000 },
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{ 0, }
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};
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@ -998,6 +999,10 @@ static int rtsx_pci_init_chip(struct rtsx_pcr *pcr)
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case 0x5289:
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rtl8411_init_params(pcr);
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break;
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case 0x5227:
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rts5227_init_params(pcr);
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break;
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}
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dev_dbg(&(pcr->pci->dev), "PID: 0x%04x, IC version: 0x%02x\n",
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@ -31,5 +31,6 @@
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void rts5209_init_params(struct rtsx_pcr *pcr);
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void rts5229_init_params(struct rtsx_pcr *pcr);
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void rtl8411_init_params(struct rtsx_pcr *pcr);
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void rts5227_init_params(struct rtsx_pcr *pcr);
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#endif
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@ -581,8 +581,11 @@
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#define CARD_GPIO_DIR 0xFD57
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#define CARD_GPIO 0xFD58
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#define CARD_DATA_SOURCE 0xFD5B
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#define SD30_CLK_DRIVE_SEL 0xFD5A
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#define CARD_SELECT 0xFD5C
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#define SD30_DRIVE_SEL 0xFD5E
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#define SD30_CMD_DRIVE_SEL 0xFD5E
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#define SD30_DAT_DRIVE_SEL 0xFD5F
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#define CARD_CLK_EN 0xFD69
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#define SDIO_CTRL 0xFD6B
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#define CD_PAD_CTL 0xFD73
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@ -655,6 +658,8 @@
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#define MSGTXDATA3 0xFE47
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#define MSGTXCTL 0xFE48
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#define PETXCFG 0xFE49
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#define LTR_CTL 0xFE4A
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#define OBFF_CFG 0xFE4C
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#define CDRESUMECTL 0xFE52
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#define WAKE_SEL_CTL 0xFE54
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