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ARM: dts: sunxi: Convert to CCU index macros for HDMI controller 

When the HDMI controller device node was added, the needed PLL clock
macros were not exported. A separate patch addresses that, but it is
merged through a different tree.

Now that both patches are in mainline proper, we can convert the raw
numbers to proper macros.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This commit is contained in:
Chen-Yu Tsai 2017-12-04 16:44:01 +08:00 коммит произвёл Maxime Ripard
Родитель e2bf801ecd
Коммит e17e237cd6
4 изменённых файлов: 8 добавлений и 8 удалений
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4
arch/arm/boot/dts/sun4i-a10.dtsi
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@ -502,8 +502,8 @@
reg = <0x01c16000 0x1000>; reg = <0x01c16000 0x1000>;
interrupts = <58>; interrupts = <58>;
clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>, clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>,
<&ccu 9>, <&ccu CLK_PLL_VIDEO0_2X>,
<&ccu 18>; <&ccu CLK_PLL_VIDEO1_2X>;
clock-names = "ahb", "mod", "pll-0", "pll-1"; clock-names = "ahb", "mod", "pll-0", "pll-1";
dmas = <&dma SUN4I_DMA_NORMAL 16>, dmas = <&dma SUN4I_DMA_NORMAL 16>,
<&dma SUN4I_DMA_NORMAL 16>, <&dma SUN4I_DMA_NORMAL 16>,

4
arch/arm/boot/dts/sun5i-a10s.dtsi
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@ -82,8 +82,8 @@
reg = <0x01c16000 0x1000>; reg = <0x01c16000 0x1000>;
interrupts = <58>; interrupts = <58>;
clocks = <&ccu CLK_AHB_HDMI>, <&ccu CLK_HDMI>, clocks = <&ccu CLK_AHB_HDMI>, <&ccu CLK_HDMI>,
<&ccu 9>, <&ccu CLK_PLL_VIDEO0_2X>,
<&ccu 16>; <&ccu CLK_PLL_VIDEO1_2X>;
clock-names = "ahb", "mod", "pll-0", "pll-1"; clock-names = "ahb", "mod", "pll-0", "pll-1";
dmas = <&dma SUN4I_DMA_NORMAL 16>, dmas = <&dma SUN4I_DMA_NORMAL 16>,
<&dma SUN4I_DMA_NORMAL 16>, <&dma SUN4I_DMA_NORMAL 16>,

4
arch/arm/boot/dts/sun6i-a31.dtsi
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@ -429,8 +429,8 @@
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_AHB1_HDMI>, <&ccu CLK_HDMI>, clocks = <&ccu CLK_AHB1_HDMI>, <&ccu CLK_HDMI>,
<&ccu CLK_HDMI_DDC>, <&ccu CLK_HDMI_DDC>,
<&ccu 7>, <&ccu CLK_PLL_VIDEO0_2X>,
<&ccu 13>; <&ccu CLK_PLL_VIDEO1_2X>;
clock-names = "ahb", "mod", "ddc", "pll-0", "pll-1"; clock-names = "ahb", "mod", "ddc", "pll-0", "pll-1";
resets = <&ccu RST_AHB1_HDMI>; resets = <&ccu RST_AHB1_HDMI>;
reset-names = "ahb"; reset-names = "ahb";

4
arch/arm/boot/dts/sun7i-a20.dtsi
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@ -581,8 +581,8 @@
reg = <0x01c16000 0x1000>; reg = <0x01c16000 0x1000>;
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>, clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>,
<&ccu 9>, <&ccu CLK_PLL_VIDEO0_2X>,
<&ccu 18>; <&ccu CLK_PLL_VIDEO1_2X>;
clock-names = "ahb", "mod", "pll-0", "pll-1"; clock-names = "ahb", "mod", "pll-0", "pll-1";
dmas = <&dma SUN4I_DMA_NORMAL 16>, dmas = <&dma SUN4I_DMA_NORMAL 16>,
<&dma SUN4I_DMA_NORMAL 16>, <&dma SUN4I_DMA_NORMAL 16>,